TWI498975B - 封裝結構與基材的接合方法 - Google Patents

封裝結構與基材的接合方法 Download PDF

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Publication number
TWI498975B
TWI498975B TW101114983A TW101114983A TWI498975B TW I498975 B TWI498975 B TW I498975B TW 101114983 A TW101114983 A TW 101114983A TW 101114983 A TW101114983 A TW 101114983A TW I498975 B TWI498975 B TW I498975B
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Taiwan
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substrate
layer
package structure
silver
silver layer
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TW101114983A
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English (en)
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TW201344807A (zh
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殷宏林
謝哲偉
林立元
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亞太優勢微系統股份有限公司
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Priority to TW101114983A priority Critical patent/TWI498975B/zh
Priority to US13/836,807 priority patent/US8916449B2/en
Priority to CN201310129982.XA priority patent/CN103377956B/zh
Publication of TW201344807A publication Critical patent/TW201344807A/zh
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Publication of TWI498975B publication Critical patent/TWI498975B/zh

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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
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    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
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Description

封裝結構與基材的接合方法
本發明係關於一種晶圓對晶圓接合的方法，尤其是利用Ag3 Sn金屬間化合物來接合晶圓。
有別於以往半導體晶片利用後段封膠灌模及導線架或陶瓷基板等方式進行封裝，近年來許多微晶片採用晶圓級封裝(Wafer level package)，其利用一封蓋(cap)晶片來保護晶片上對外界環境敏感的電路或脆弱之結構，如含懸浮可動元件的微機電感測器晶片等。許多微機電感測器晶片如加速度計(accelerometer)或壓力計(pressure sensor)等通常會與一具凹槽(recess)結構的玻璃或矽晶片進行晶圓接合(wafer bonding)，以保護感測結構或薄膜，亦可提供如氣密(hermetic seal)、矽穿孔導線(TSV)等功能。
常用的晶圓接合技術包含熔融接合(fusion bonding)、陽極接合(anodic bonding)及介質接合如共晶接合(eutectic bonding)或高分子接合等。由於熔融接合及陽極接合僅分別適用於矽-矽或二氧化矽及矽-含鈉玻璃之接合，且對於晶圓表面的平整度要求較高，限制了其應用範圍，因此利用相容的介質來進行晶圓接合成為較常採用的方法。其中玻璃熔料(glass frit)已被大量使用在消費性電子晶片上，但由於其需利用網印(screen printing)的方式來將接合環(bond ring)圖案化，使得其接合環寬度大於100-200μm，對於逐漸微縮晶片尺寸的需求將構成嚴峻的挑戰。而高分子材料(如BCB或光阻等)可利用黃光微影的方式精確定義接合環，因此寬度可大幅縮小，但由於高分子材料在高溫時會有釋放氣體(out-gassing)的現象且其接合強度較弱，將影響產品的可靠度(reliability)。
而藉由特定金屬於較低溫時接觸互熔產生共晶的方式，將金屬層預先成形定義於微機電晶圓及封蓋晶圓上，當施加負載使兩晶圓接觸並升溫至共晶溫度之上維持一段時間後，即可將兩片晶圓接合。在此通常選擇半導體中常見或製程相容的金屬，如美國專利第7943411號教導利用鋁-鍺共晶的方式將封蓋晶圓接合於微機電元件晶圓之上，由於鋁-鍺的共晶溫度為419℃，因此欲形成一穩定的接合則其製程溫度一般需提高至430至450℃，此高溫可能會對部分膜層界面造成影響且所產生的熱應力(thermal stress)亦會造成感測薄膜變形或失效。美國專利第5668033號則是揭露利用金-矽共晶來接合加速度感測器晶片上之封蓋，由於Au-Si的共晶溫度為363℃，因此可略微降低製程所需的溫度(約390-410℃)，其缺點為金的成本較高且須克服矽表面生成自然氧化層(native oxide)的問題。因此需要開發另一與半導體製程相容的金屬共晶接合技術，來進行微機電元件的封蓋製程，同時需具有較低的共晶接合溫度及成本。美國專利第6229190號中提及可利用銀-鍚共晶的方式，在壓力感測元件晶圓及封蓋晶圓上分別成長銀或鍚後，對壓力感測元件進行封蓋接合。由於銀-鍚遠低於鋁-鍺及金-矽的共晶溫度僅約221℃，可大幅避免上述所提的熱應力等問題，其成本亦遠低於金，因此成為極具潛力的技術之一。然而此接合技術所遭遇的棘手問題在於鍚本身為一熔點低(約230℃)且強度較低的脆性材料，因此經由銀-鍚共晶接合後所產若仍含高比例的純鍚，不僅會降低接合界面強度，且當後續製程溫度高於鍚的熔點230℃時(如通過回焊爐溫度約為250℃)將對封裝結構造成破壞。
有鑑於此，本發明提出一特殊的封裝方式，以改良接合晶圓之品質，使技術能實際應用於產品量產之上。
根據本發明之一較佳實施例，本發明提供一種封裝結構，包含：一第一基材和一第二基材以及複數個金屬堆疊層設置於第一基材和第二基材之間，其中各個金屬堆疊層包含至少一第一銀層、一第二銀層和一合金層位在第一銀層和第二銀層之間，其中合金層包含Ag3 Sn金屬間化合物和錫基體(Sn matrix)。
根據本發明之另一較佳實施例，本發明提供一種基材的接合方法，包含：首先提供一第一基材和一第二基材，其中一第一銀層覆蓋第一基材之表面，一第二銀層覆蓋第二基材之表面以及一金屬層覆蓋第二銀層，其中金屬層包含一第一鍚層，接著進行一接合製程，將第一基材與第二基材對準，使得金屬層和第一銀層接觸，並且施加負載並加熱至一預定溫度以生成Ag3 Sn金屬間化合物，最後降溫並移除負載，完成接合製程。
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式，作詳細說明如下。
第1圖至第3圖為根據本發明之第一較佳實施例所繪示的基材的接合方法。請參閱第1圖，首先提供一第一基材10和一第二基材20，第一基材10和第二基材20可以為任何適用於電子裝置封裝之材料形成，例如矽、砷化鎵、藍寶石、金屬、陶瓷、及玻璃或其他半導體材料。第一基材10具有一第一表面12，第二基材20也有一第二表面22，第一表面12和第二表面22皆為為裝置面，先在第一基材10的第一表面12上依序形成一附著層14、一阻絶層16和一第一銀層18，另外在第二基材20的第二表面22上依序形成一附著層14、一阻絶層16、一第二銀層24和一金屬層26，其中前述之金屬層26包含一第一鍚層28。附著層14包含鉻或鈦而阻絶層16包含鎳或鉑，另外，第一銀層18、第二銀層24和金屬層26可以利用電子束蒸鍍、濺鍍或是電鍍來形成。如第2圖所示，進行微影和蝕刻製程或是舉離(lift-off)等方式，分別圖案化第一基材10上的附著層14、阻絶層16和第一銀層18，以及第二基材20上的附著層14、阻絶層16、第二銀層24和金屬層26，在圖案化之後，剩餘的附著層14、阻絶層16、第一銀層18、第二銀層24和金屬層26，將在後續步驟形成接合環。
然後進行一預清洗步驟，可使用濕式蝕刻的方式，例如含氫氟酸(HF)系水溶液來清洗第一銀層18和金屬層26的表面，或是利用乾式蝕刻的方式，例如氬離子電漿蝕刻等方式進行附著層14、阻絶層16、第一銀層18、第二銀層24和金屬層26的預清洗。如第3圖所示，進行一接合製程，將第一基材10和第二基材20對準，詳細來說，對準是指將第一基材10上的第一銀層18對準第二基材20上的金屬層26並且使第一銀層18和金屬層26接觸，之後再施加一均勻負載(loading)於第一基材10和第二基材20，並且使第一基材10和第二基材20以及其上的銀層18、24和金屬層26升溫至一預定溫度，在預定溫度維持一預定時間，前述的預定溫度需超過銀和鍚的共晶溫度，根據本發明之較佳實施例，預定溫度為250至350度之間，而預定時間約為30分鐘，然後降溫及移除負載即完成接合製程。請參同時參閱第3圖和第4圖，第4圖繪示了Ag3 Sn金屬間化合物和錫基體混合之示意圖。在接合製程中，部分的第一銀層18、部分的第二銀層24會和第一鍚層28會反應形成Ag3 Sn金屬間化合物(intermetallic compound)32，未和銀結合的第一鍚層28會聚集成為錫基體34，前述的Ag3 Sn金屬間化合物32和錫基體34定義為一合金層30。由於可藉由第一銀層18及第二銀層24同時與第一錫層28產生共晶反應，因此共晶合金層中Ag3 Sn金屬間化合物32會均勻分布於錫基體34中，除提升接合強度外，由於此金屬堆疊層50為一對稱結構，因此可進一步降低接合所產生之梯度應力(gradient stress)。
另外，為強化共晶反應及接合強度，可選擇性地將接合完成之基材10、20進行接合後退火(post-bond annealing)，例如將接合的基材10、20在爐管或烤箱內進行退火，以確保大量的鍚充分共晶成為Ag3 Sn，退火溫度較佳介於350至450度之間，由於可批次大量進行接合晶圓後的退火製程，相較以單次進行長時間的接合製程，利用接合後退火處理來改善接合強度更符合量產之需求。
第5圖至第6圖為根據本發明之第二較佳實施例所繪示的基材的接合方法，第二較佳實施例為第一較佳實施例的變化型，其和第一實施例的差異點在於形成在第二基材20上的金屬層26之組成，如第5圖所示，第二基材20上的金屬層26可以由銀金屬層和鍚金屬層交替堆疊而組成，舉例而言，在第一較佳實施例中的第一鍚層28形成之後，依序另形成一第三銀層36和一第二鍚層38，當然，本發明之金屬層26可依據產品需求，交替形成適當的銀金屬層和鍚金屬層，之後再進行進行微影和蝕刻製程或是舉離製程。後續的接合製程和退火製程步驟，都和第一實施例中描述的相同，在此不再贅述。請同時參閱第4圖和第6圖，在接合製程中，部分的第一銀層18、部分的第二銀層24和部分的第三銀層36會分別和第一鍚層28和第二鍚層38反應形成Ag3 Sn金屬間化合物32，未和銀結合的第一鍚層28和第二鍚層38會被打散成為錫基體34，前述的Ag3 Sn金屬間化合物32和錫基體34定義為一合金層30。本實施例中，合金層30有二層，而在二層合金層30中間夾著第三銀層36。
依據本發明第一較佳實施例和第二較佳實施例之精神，發明人調整金屬層26的組成以及退火時間，將基材接合方式分成五組，然後將其切割成複數個相同尺寸之晶粒，最後再對分別利用這五種製程方式所接合的封裝晶粒進行強度測試，包括剪力測試和水滲透測試。各組的製程條件分述如下：
第1組
請參閱第7圖，第1組之第一基材10上和配置就如第一實施例中所述，第二基材20上的金屬層26也和第一實施例中相同，只有含有第一鍚層28，和第一實施例不同的是第1組中的第二基材20上沒有第二銀層24，而且第1組的第一基材10和第二基材20，在接合後，未進行退火步驟。
第2組
請復參閱第7圖，第2組的第一銀層18和金屬層26的配置就如第1組中所述，不同的是第2組的退火步驟時間為1小時。
第3組
請參閱第2圖，第3組之第一基材10和第二基材20上的第一銀層18、第二銀層24和金屬層26的配置就如第一實施例中所述，不同的是第3組的退火步驟的進行時間為1小時。
第4組
請復參閱第2圖，第4組的第一銀層18、第二銀層24和金屬層26的配置就如第一實施例中所述，不同的是第4組的退火步驟時間為1.5小時。
第5組
請參閱第5圖，第5組之第一基材10和第二基材20上的第一銀層18、第二銀層24和金屬層26的配置就如第二實施例中所述，不同的是第5組的基材退火步驟的進行時間為1小時。
表一為第1組至第5組的實驗數據表，測試利用本發明接合技術所完成的封裝結構之剪力和水滲透數據。
表一顯示針對五組基材接合方式分別做剪力測試和水滲透測試的實驗結果
如表一所示，比較第1組和第2組可發現第1組由於未經接合後退火處理，因此其強度較差，因此在接合製程之後兩片晶圓隨即分離，而第2組經接合後退火處理後仍具一定強度，顯見接合後退火製程確能促使Ag3 Sn金屬間化合物的生成，因而增加接合強度。另比較第2、3及5組可知，第2組的第二晶圓20上未含銀層，所以在相同的接合及退火時間下Ag3 Sn金屬間化合物32的生成仍較第3和第5組不完全，因此其強度較弱，且以水滲透的方式測試第2組的密封性，在223晶粒中僅10個晶粒通過測試；反觀第3及第5組在接合製程之前，第二晶圓20上有第一銀層18、第二銀層24和金屬層26和第一鍚層28或第二鍚層38堆疊結構，因此在合金層30中，其Ag3 Sn金屬間化合物32的生成的比例較高，剩餘的錫基體34比例較低，所以接合強度較強，且密封性亦較佳。因此得以驗證，在接合製程中，利用銀層和鍚層堆疊結構的確可得到較佳的接合強度及密封性。另比較第3及第4組可發現，由於第4組的退火時間較長，使其合金層30中Ag3 Sn金屬間化合物32的比例較第3組高，因此其強度亦較為提升。
第3圖繪示的是根據本發明的第三較佳實施例所繪示的封裝結構。第三較佳實施例係利用本發明之基材接合方法所形成，如第3圖所示，本發明之封裝結構包含一第一基材10、一第二基材20和以及複數個金屬堆疊層50設置於第一基材10和第二基材20之間，其中各個金屬堆疊層50包含至少一第一銀層18、一第二銀層24和一合金層30位在第一銀層18和第二銀層24之間，請同時參閱第4圖，值得注意的是合金層30包含Ag3 Sn金屬間化合物32和錫基體34，其中Ag3 Sn金屬間化合物32和錫基體34較佳為均勻混合。
再者，前述的第一基材10和第二基材20可以為任何適用於電子裝置封裝之材料形成，例如矽晶圓、砷化鎵、藍寶石、金屬、陶瓷、及玻璃或其他半導體材料。在本發明中基材的材料以晶圓為例，通常，晶圓中可以包含單晶矽、覆矽絕緣層、矽-鍺基材或是前述之組合。另外，前述的第一銀層18係與第一基材10之第一表面22接觸，第二銀層24係與第二基材20之第二表面22接觸，一附著層16，例如鉻或鈦，係位在各個金屬堆疊層50和第一基材10之間以及各個金屬堆疊層50和第二基材20之間，再者附著層14和各個金屬堆疊層50之間具有一阻絕層16，阻絕層16包含鎳和鉑。
第6圖繪示的是根據本發明的第四較佳實施例所繪示的封裝結構。請參閱第6圖，第四實施例和第三實施例的差別在於第四實施例的金屬堆疊層50中，除了第一銀層18和第二銀層24之外，還另包含二層合金層30和一層第三銀層36，第三銀層36夾在合金層30之間。
第8圖是根據本發明的第五較佳實施例所繪示的封裝結構。本發明的接合方式適用於接合各個不同的晶圓，如第8圖所示，第一基材10可以為一封蓋晶圓或是一微機電晶圓，而第二基材20可以為一封蓋晶圓或是一微機電晶圓，但第一基材10和第二基20材為不同種類的晶圓，舉例而言，第一基材10可以為一封蓋晶圓，其上設有至少一個凹槽52，第二基材20可以為一微機電晶圓，其上設有至少一微機電元件54，而第三實施例或第四實施例中的金屬堆疊層50，可設置於第一基材10和第二基材20之間。同樣地，金屬堆疊層50至少包含合金層30、第一銀層18和第二銀層24，另外，附著層14和阻絕層16則可以選擇性設置。
第9圖是根據本發明的第六較佳實施例所繪示的封裝結構。第六較佳實施例為第五較佳實施例的變化型，其中第一基材10可以為一封蓋晶圓，其上設有至少一個凹槽52，第二基材20可以為一微機電晶圓，其上設有至少一微機電元件54，而第三實施例或第四實施例中的金屬堆疊層50，可設置於第一基材10和第二基材20之間，同樣地，金屬堆疊層50至少包含合金層30、第一銀層18和第二銀層24，另外，附著層14和阻絕層16則可以選擇性設置。
此外，第一基材10和第二基材20之間另設有至少一焊墊56，焊墊56係和微機電元件54電連結，再者，焊墊56亦含有包含Ag3 Sn金屬間化合物，另外，第一基材10上具有至少一穿孔58，穿孔58對應於前述焊墊56，在穿孔58內設有一金屬層60，與焊墊56電性相連可將微機電元件54的電子訊號做輸出。
第10圖是根據本發明的第七較佳實施例所繪示的封裝結構，其和第六實施例的差異點在於其微機電元件54的電子訊號輸出並非藉由金屬層60而是直接利用打線61的方式直接將訊號線拉線連結至另一電子電路裝置上(圖中未標示)。
第11圖是根據本發明的第八較佳實施例所繪示的封裝結構。如第11圖所示，第一基材10可以為一微機電晶圓，其上設有至少一微機電元件54，而第二基材20可以為CMOS晶圓，其上設有至少一電子電路元件62，而第三實施例或第四實施例中的金屬堆疊層50，可設置於第一基材10和第二基材20之間用來密封接合微機電元件54，並且作為第一基材10和第二基材20之機械及電性接點，同樣地，金屬堆疊層50至少包含合金層30、第一銀層18和第二銀層24，另外，附著層14和阻絕層16則可以選擇性設置。
此外，第一基材和第二基材之間設有至少一焊墊56，焊墊56亦含有包含Ag3 Sn金屬間化合物，焊墊56與微機電元件54以及電子電路元件62電連結，因此，微機電元件54之電子訊號可藉由焊墊56傳遞至CMOS晶圓上的電子線路，再經由金屬內連線輸出。
本發明揭露一種封裝結構及基材接合的方法，在一晶圓上形成銀層，並在另一晶圓上交替形成銀和鍚的堆疊層。進行晶圓接合時，由於Ag3 Sn金屬間化合物的可由鍚與上下兩層銀接觸之界面開始生成，因此可縮短相互擴散所需之時間，在較短的時間內使銀和鍚形成Ag3 Sn共晶。另外，在接合製程完成後，加入一接合後退火步驟，使純鍚大量轉化Ag3 Sn金屬間化合物，進一步提升接合的強度及密封等特性。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．第一基材
12．．．第一表面
14．．．附著層
16．．．阻絶層
18．．．第一銀層
20．．．第二基材
22．．．第二表面
24．．．第二銀層
26．．．金屬層
28．．．第一鍚層
30．．．合金層
32．．．Ag3 Sn金屬間化合物
34．．．錫基體
36．．．第三銀層
38．．．第二鍚層
50．．．金屬堆疊層
52．．．凹槽
54．．．微機電元件
56．．．焊墊
58．．．穿孔
60．．．金屬層
61．．．打線
62．．．電子電路元件
第1圖至第3圖為根據本發明之第一較佳實施例所繪示的基材的接合方法。
第4圖繪示的是合金層之放大示意圖。
第5圖至第6圖為根據本發明之第二較佳實施例所繪示的基材的接合方法。
第7圖繪示的是本發明之第1組的基材結構配置。
第8圖是根據本發明的第五較佳實施例所繪示的封裝結構。
第9圖是根據本發明的第六較佳實施例所繪示的封裝結構。
第10圖是根據本發明的第七較佳實施例所繪示的封裝結構。
第11圖是根據本發明的第八較佳實施例所繪示的封裝結構。
10．．．第一基材
12．．．第一表面
14．．．附著層
16．．．阻絶層
18．．．第一銀層
20．．．第二基材
22．．．第二表面
24．．．第二銀層
30．．．合金層
50．．．金屬堆疊層

Claims (21)

  1. 一種封裝結構，包含：一第一基材；一第二基材；以及複數個金屬堆疊層設置於該第一基材和該第二基材之間，其中各該金屬堆疊層包含至少一第一銀層、一第二銀層和一合金層位在該第一銀層和該第二銀層之間，其中該合金層包含Ag3 Sn金屬間化合物和錫基體。
  2. 如申請專利範圍第1項所述之封裝結構，其中該第一銀層接觸該第一基材之表面，該第二銀層接觸該第二基材之表面。
  3. 如申請專利範圍第1項所述之封裝結構，其中該Ag3 Sn金屬間化合物和錫基體為均勻混合。
  4. 如申請專利範圍第1項所述之封裝結構，其中該第一基材及該第二基材可為矽、砷化鎵、藍寶石、金屬、陶瓷、及玻璃或其他半導體材料。
  5. 如申請專利範圍第1項所述之封裝結構，另包含一附著層位在各該金屬堆疊層和該第一基材之間以及各該金屬堆疊層和該第二基材之間。
  6. 如申請專利範圍第5項所述之封裝結構，其中該附著層包含鉻或鈦。
  7. 如申請專利範圍第5項所述之封裝結構，其中該附著層和各該金屬堆疊層之間具有一阻絕層，該阻絕層包含鎳或鉑。
  8. 如申請專利範圍第1項所述之封裝結構，另包含至少一微機電元件設置於該第一基材上。
  9. 如申請專利範圍第8項所述之封裝結構，另包含一焊墊與該微機電元件電性相連，其中該焊墊包含Ag3 Sn金屬間化合物。
  10. 如申請專利範圍第9項所述之封裝結構，另包含至少一電子電路元件設置於該第二基材上。
  11. 如申請專利範圍第10項所述之封裝結構，其中該焊墊為該微機電元件與該電子電路元件間的機械及電性接點。
  12. 如申請專利範圍第9項所述之封裝結構，另包含複數個凹槽設置於該第二基材上。
  13. 如申請專利範圍第12項所述之封裝結構，其中該第二基材上包含至少一貫穿孔，該貫穿孔對應與該微機電元件電性相連之該焊墊，可利用一位在該貫穿孔內的金屬層或打線的方式，來傳導該焊墊之電子訊號。
  14. 一種基材的接合方法，包含：提供一第一基材和一第二基材，其中一第一銀層覆蓋該第一基材之表面，一第二銀層覆蓋該第二基材之表面以及一金屬層覆蓋該第二銀層，其中該金屬層包含一第一鍚層；進行一接合製程，將該第一基材與該第二基材對準，使得該金屬層和該第一銀層接觸，並且施加負載並加熱至一預定溫度以生成Ag3 Sn金屬間化合物；以及降溫並移除負載，完成接合製程。
  15. 如申請專利範圍第14項所述之基材的接合方法，另包含在接合製程之後，進行一退火步驟。
  16. 如申請專利範圍第15項所述之基材的接合方法，其中該退火步驟的溫度範圍為350-450度。
  17. 如申請專利範圍第14項所述之基材的接合方法，其中該預定溫度範圍為250-350度。
  18. 如申請專利範圍第14項所述之基材的接合方法，另包含形成一附著層位在該第一銀層和該第一基材之間以及該第二銀層和該第二基材之間。
  19. 如申請專利範圍第18項所述之基材的接合方法，其中該附著層包含鉻或鈦。
  20. 如申請專利範圍第18項所述之基材的接合方法，另包含形成一阻絕層位在該附著層和該第一銀層之間以及該附著層和該第二銀層之間，該阻絕層包含鎳或鉑。
  21. 如申請專利範圍第14項所述之基材的接合方法，另包含在接合製程之前形成一第三銀層於該第一鍚層上，再形成一第二錫層於該第三銀層上。
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
FR3006236B1 (fr) * 2013-06-03 2016-07-29 Commissariat Energie Atomique Procede de collage metallique direct
KR20160038094A (ko) * 2014-09-26 2016-04-07 코닝정밀소재 주식회사 발광 다이오드의 색변환용 기판 및 그 제조방법
US9564418B2 (en) * 2014-10-08 2017-02-07 Micron Technology, Inc. Interconnect structures with intermetallic palladium joints and associated systems and methods
CN104599976B (zh) * 2014-12-24 2018-01-09 中国科学院苏州纳米技术与纳米仿生研究所 无铅焊料合金及其制备方法和应用
US9564409B2 (en) * 2015-01-27 2017-02-07 Semiconductor Components Industries, Llc Methods of forming semiconductor packages with an intermetallic layer comprising tin and at least one of silver, copper or nickel
US9953941B2 (en) * 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
CN105197881A (zh) * 2015-08-28 2015-12-30 中国科学院半导体研究所 一种利用金属材料扩散互溶实现硅-硅键合的方法
CN107848789B (zh) * 2015-09-17 2020-10-27 株式会社村田制作所 Mems设备及其制造方法
JP6315014B2 (ja) * 2016-03-23 2018-04-25 日亜化学工業株式会社 半導体装置の製造方法
US10081539B2 (en) * 2016-07-12 2018-09-25 Invensense, Inc. Two different conductive bump stops on CMOS-MEMS bonded structure
WO2018173764A1 (ja) * 2017-03-21 2018-09-27 富士フイルム株式会社 積層デバイス、積層体および積層デバイスの製造方法
FR3076126A1 (fr) * 2017-12-26 2019-06-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation d'un resonateur acoustique a ondes de volume a capacite parasite reduite
KR102744178B1 (ko) 2019-08-19 2024-12-19 삼성전자주식회사 반도체 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030156969A1 (en) * 2002-02-15 2003-08-21 International Business Machines Corporation Lead-free tin-silver-copper alloy solder composition
JP2005150417A (ja) * 2003-11-17 2005-06-09 Nec Toppan Circuit Solutions Inc 半導体装置用基板及びその製造方法並びに半導体装置
US20070002422A1 (en) * 2005-07-01 2007-01-04 O'shaughnessy Dennis J Transparent electrode for an electrochromic switchable cell
US20070042211A1 (en) * 2005-08-17 2007-02-22 Sun Microsystems, Inc. Ternary alloy column grid array

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3613838B2 (ja) 1995-05-18 2005-01-26 株式会社デンソー 半導体装置の製造方法
US6229190B1 (en) 1998-12-18 2001-05-08 Maxim Integrated Products, Inc. Compensated semiconductor pressure sensor
DE10251658B4 (de) * 2002-11-01 2005-08-25 Atotech Deutschland Gmbh Verfahren zum Verbinden von zur Herstellung von Mikrostrukturbauteilen geeigneten, mikrostrukturierten Bauteillagen sowie Mikrostrukturbauteil
EP1600249A1 (en) * 2004-05-27 2005-11-30 Koninklijke Philips Electronics N.V. Composition of a solder, and method of manufacturing a solder connection
US20070059548A1 (en) * 2005-08-17 2007-03-15 Sun Microsystems, Inc. Grid array package using tin/silver columns
US7626274B2 (en) * 2006-02-03 2009-12-01 Texas Instruments Incorporated Semiconductor device with an improved solder joint
WO2008041350A1 (en) * 2006-09-29 2008-04-10 Kabushiki Kaisha Toshiba Joint with first and second members with a joining layer located therebetween containing sn metal and another metallic material; methods for forming the same joint
US7943411B2 (en) 2008-09-10 2011-05-17 Analog Devices, Inc. Apparatus and method of wafer bonding using compatible alloy
TW201029059A (en) * 2009-01-22 2010-08-01 Univ Nat Central Tin/silver bonding structure and its method
FR2961638B1 (fr) * 2010-06-21 2012-07-06 Commissariat Energie Atomique Microbatterie et procede de fabrication d'une microbatterie

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030156969A1 (en) * 2002-02-15 2003-08-21 International Business Machines Corporation Lead-free tin-silver-copper alloy solder composition
US6805974B2 (en) * 2002-02-15 2004-10-19 International Business Machines Corporation Lead-free tin-silver-copper alloy solder composition
JP2005150417A (ja) * 2003-11-17 2005-06-09 Nec Toppan Circuit Solutions Inc 半導体装置用基板及びその製造方法並びに半導体装置
US20070002422A1 (en) * 2005-07-01 2007-01-04 O'shaughnessy Dennis J Transparent electrode for an electrochromic switchable cell
US20070042211A1 (en) * 2005-08-17 2007-02-22 Sun Microsystems, Inc. Ternary alloy column grid array

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