TWI569332B - Semiconductor device and fabrication method thereof - Google Patents

Description

Semiconductor element structure and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a field effect transistor device having a metal gate structure and a method of fabricating the same.

As the critical dimensions of the semiconductor shrink, the size of the field effect transistor and the thickness of the gate dielectric layer are also limited. However, the reduction in the thickness of the gate dielectric layer will result in the occurrence of leakage current. In order to reduce the occurrence of dew current, a high dielectric constant (high-k) material is used to fabricate the gate dielectric layer, and a metal gate electrode is used to replace the polysilicon gate electrode with a higher resistance value, thereby improving the performance of the device.

A method for fabricating a metal gate electrode transistor is to form a dummy gate eletrode. After the metal-oxide-semiconductor transistor main structure is completed, the polysilicon dummy gate is removed by an etching step, and The original polysilicon virtual gate is replaced by metal deposition.

However, removing the polysilicon dummy gate and metal deposition process is likely to affect the process integration of the transistor component with other semiconductor components. For example, a polycrystalline germanium layer is typically used to fabricate polycrystalline germanium virtual gate electrodes for transistors and polysilicon stacks of resistors (or other passive components). When the polysilicon gate removal etching is performed, the polysilicon element layer must be masked with photoresist to perform etching. However, this often causes a high and low drop between the polysilicon device layer of the passive component and the metal gate electrode. In turn, resulting in subsequent metal deposition and metal contact processes, Metal residues are generated around the passive components, affecting the performance of the components.

Therefore, it is necessary to provide an advanced semiconductor component and a manufacturing method thereof, and effectively integrate the process of the field effect transistor and the passive component to improve the working efficiency of the component.

In view of this, the present invention provides a semiconductor device structure including a metal gate electrode, a passive component, and a hard mask layer. The passive component has a polycrystalline germanium component layer. The hard mask layer covers the metal gate electrode and the passive component, and has a first opening and a second opening substantially coplanar to expose the metal gate electrode and the polysilicon component layer respectively. Wherein, the distance between the first opening and the metal gate electrode is substantially smaller than the distance between the second opening and the polysilicon assembly layer.

In an embodiment of the invention, the semiconductor device structure further includes a substrate, a drain/source structure, and a gate dielectric layer. Wherein the drain/source structure is located in the substrate adjacent to the metal gate electrode. The gate dielectric layer is between the drain/source structure and the metal gate electrode.

In an embodiment of the invention, the gate dielectric layer includes an interfacial layer (IL) and a high dielectric constant material layer sequentially stacked on the substrate. In one embodiment of the invention, the passive component is a resistor. In an embodiment of the invention, the semiconductor device structure further includes a capping layer between the high-k material layer and the metal gate electrode.

In an embodiment of the invention, the semiconductor device structure further includes a first spacer and a second spacer. Wherein, a first spacer is located between the metal gate electrode and the hard mask layer; and a second spacer is located between the polysilicon assembly layer and the hard mask layer.

The present invention further provides a method of fabricating a semiconductor device structure, including the following Step: First, a dummy gate and a passive component are provided, wherein the dummy gate has a polysilicon gate electrode layer and the passive component has a polysilicon layer. Next, a hard mask layer is formed on the dummy gate and the passive component. Then, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the polysilicon device layer to the outside. Thereafter, an inner layer dielectric (ILD) is formed on the dummy gate and the passive component; and the inner dielectric layer is planarized by using the hard mask layer as a polishing stop layer. Subsequently, a second etching process is performed to remove the polysilicon gate electrode layer and form a metal gate electrode at the original position of the polysilicon gate electrode layer.

In one embodiment of the invention, the first etch process also removes a portion of the polysilicon assembly layer to form an recess in the passive component to expose the remaining polysilicon component layer.

In an embodiment of the invention, the formation of the dummy gate and the passive component comprises the steps of first forming a dielectric material layer and a polysilicon material layer sequentially on the substrate. Next, the polysilicon material layer and the dielectric material layer are patterned to form a polysilicon gate electrode and a polysilicon device layer on the patterned dielectric material layer. Thereafter, a first spacer and a second spacer are formed on the sidewalls of the polysilicon gate electrode and the polysilicon assembly layer, respectively.

In an embodiment of the invention, the dielectric material layer comprises: an interface layer sequentially stacked on the substrate and a high dielectric constant material layer. In an embodiment of the invention, the method further includes forming a cover layer between the high dielectric constant material layer and the polysilicon material layer. In an embodiment of the invention, before forming the metal gate electrode, the method further comprises: forming at least one working function layer on the cover layer.

In an embodiment of the present invention, before performing the second etching process, the method further comprises: forming a gate/source structure in the substrate by using a dummy gate to cover the substrate. in In one embodiment of the present invention, before forming the metal gate electrode, the method further comprises: forming a high dielectric constant material layer at an original position of the polysilicon gate electrode layer; and forming at least one work function on the high dielectric constant material layer Floor.

In an embodiment of the invention, the second etching process includes dry etching and wet etching. In one embodiment of the invention, planarization of the inner dielectric layer includes chemical mechanical polishing (CMP).

In accordance with the above, embodiments of the present invention provide a semiconductor device structure that integrates a metal gate electrode transistor with a passive component. The way of making it is to cover the polysilicon virtual gate electrode and the passive component with a hard mask. The passive component is then subjected to a first etching process to remove a portion of the hard mask and expose a portion of the polysilicon component layer of the passive component. Thereafter, a second etching process is performed to remove the polysilicon dummy gate. Metal gate electrode deposition and planarization processes are subsequently performed to form metal gate electrodes and passive components that are coplanar with each other.

By means of two etching processes, respectively thinning the moving component and removing the dummy gate, the passive component and the metal gate electrode can be subjected to a subsequent metal contact process on the same plane, thereby reducing the metal residue of the passive component polysilicon component layer. Improve the performance of components.

The present invention is to provide a semiconductor device structure and a method of fabricating the same, which can integrate a metal gate electrode transistor with a passive component and improve device performance. The above and other objects, features and advantages of the present invention will become more <RTIgt;

Referring to FIG. 1A to FIG. 1G, FIG. 1A to FIG. 1G illustrate a series of processes for fabricating a semiconductor device structure 100 according to a preferred embodiment of the present invention. Structural profile. The method for manufacturing the semiconductor device structure 100 includes the steps of: sequentially forming a dielectric material layer 104, a cap layer 120, and a polysilicon layer 105 (as shown in FIG. 1A) on the substrate 101. In the present embodiment, the dielectric material layer 104 includes an interface layer 104a and a high-k material layer 104b which are sequentially stacked on the substrate 101. The material of the interface layer 104a is preferably cerium oxide, tantalum nitride, lanthanum oxynitride or lanthanum oxynitride; the material of the high dielectric constant material layer 104b is preferably bismuth telluride, cerium oxide, cerium oxide or oxynitride. Hey. The material of the cover layer 120 is preferably titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments of the present invention, further comprising forming at least one hard mask layer (not shown) on the polysilicon material layer 105.

Thereafter, the polysilicon material layer 105 and the dielectric material layer 104 are patterned to form a polysilicon gate electrode 106 and a polysilicon device layer 107 on the patterned dielectric layer 104 (wherein the polysilicon gate electrode 106 is located under the polysilicon gate electrode 106). The patterned dielectric layer 104, hereinafter referred to as the gate dielectric layer 108).

The first spacers 109 and the second spacers 110 are formed on the sidewalls of the polysilicon gate electrode 106 and the polysilicon device layer 107, respectively, by a deposition and etching process. Further, a dummy gate 102 and a passive component 103 are provided on the substrate 101. Among them, the passive component 103 is preferably a resistor.

Before forming the first spacers 109 and the second spacers 110, the method further includes: using the polysilicon gate electrode 106 and the gate dielectric layer 108 as a mask, performing a plurality of light doping processes, thereby forming in the substrate 101. A Light Doped Drain (LDD) structure is adjacent to the gate dielectric layer 108. After forming the first spacer 109 and the second spacer 110, the dummy gate 102 is used as a mask to perform a series of ion implantation processes on the lightly doped gate structure to form a drain in the substrate 101. The source structure 119 (as shown in FIG. 1B).

Then, on the dummy gate 102 and the passive component 103, a hard mask layer 111 is formed, and a patterned photoresist layer 112 is formed on the hard mask layer 111 to place a portion of the hard mask layer above the polysilicon component layer 107. 111 is exposed (as shown in Figure 1C). Then, a first etching process is performed to remove a portion of the hard mask layer 111, whereby an opening 111a is defined on the hard mask layer 111 to expose a portion of the polysilicon device layer 107.

In some embodiments of the present invention, the hard mask layer 111 may be a single layer or a plurality of layers of tantalum nitride (SiN), tantalum carbide (SiC) or tantalum carbonitride (SiCN). Contact Etch Stop Layer (CESL). Preferably, a layer of tantalum nitride which can be stressed is applied.

In some embodiments of the present invention, the first etching process 113 preferably further removes a portion of the polysilicon component layer 107, thereby forming an recess 113 in the passive component 103, and the remaining polysilicon components. Layer 107 is exposed to the outside by opening 111a (as depicted in Figure ID).

Subsequently, on the dummy gate 102 and the passive component 103, an inner dielectric layer 114 is formed and the recess 113 is filled. Thereafter, the inner dielectric layer 114 is planarized by using the hard mask layer 111 as a polishing stop layer (as shown in FIG. 1E). In a preferred embodiment of the invention, the planarization of the inner dielectric layer 114 includes a chemical mechanical polishing process.

Thereafter, using the capping layer 120 as an etch stop layer, a second etching process is performed to remove a portion of the hard mask layer 111 overlying the dummy gate 102, and the polysilicon gate electrode 106 located in the dummy gate 102, The opening 111b is defined on the hard mask layer 111, and the recess 115 is formed in the dummy gate 102, and the cover layer 120 is exposed to the outside via the recess 115 and the opening 111b (as shown in FIG. 1F).

In some embodiments of the invention, the second etching process can be used simultaneously Etching and wet etching are two etching methods. In the present embodiment, the hard mask layer 111 is first removed by dry etching; the polysilicon gate electrode 106 is removed by wet etching.

Thereafter, on the cover layer 120 in the recess 115, at least one work function layer 116, such as titanium nitride or titanium aluminum alloy (TiAl), is formed; a metal layer is deposited on the work function layer 116, and the metal layer is flattened. The metal gate structure 118 including the metal gate electrode 117 is formed to complete the fabrication of the semiconductor device structure 100 (as shown in FIG. 1G). Subsequent to the metal gate structure 118 and the passive component 103, a metal contact process is performed to form a plurality of metal contacts (not shown) that are in electrical contact with the metal interconnects.

Referring to FIG. 2A to FIG. 2G, FIG. 2A to FIG. 2G are cross-sectional views showing a series of process structures for fabricating the semiconductor device structure 200 according to another preferred embodiment of the present invention. The method for manufacturing the semiconductor device structure 200 includes the steps of: sequentially forming a dielectric material layer 204 and a polysilicon material layer 205 (as shown in FIG. 2A ) on the substrate 201 . In the present embodiment, the dielectric material layer 204 is preferably hafnium oxide, hafnium nitride, hafnium oxynitride or niobium nitrite.

Thereafter, the polysilicon material layer 205 and the dielectric material layer 204 are patterned to form a polysilicon gate electrode 206 and a polysilicon device layer 207 on the patterned dielectric material layer 204. A first spacer 209 and a second spacer 210 are formed on the sidewalls of the polysilicon gate electrode 206 and the polysilicon device layer 207, respectively, by a deposition and etching process. Further, a dummy gate 202 and a passive component 203 (preferably a resistor) are provided on the substrate 201.

Before the first spacer 209 and the second spacer 210 are formed, the polysilicon gate electrode 206 and the gate dielectric layer 208 are used as a mask to perform a plurality of light doping processes to form a substrate 201. Lightly doped bungee structure, with gate Dielectric layer 108 is contiguous. Then, with the dummy gate 202 as a mask, a drain/source structure 219 is formed in the substrate 201 (as shown in FIG. 2B).

Next, a hard mask layer 211 is formed on the dummy gate 202 and the passive component 203, and a patterned photoresist layer 212 is formed on the hard mask layer 211 to place a portion of the hard mask layer 211 above the polysilicon component layer 207. Exposed (as shown in Figure 2C). In some embodiments of the present invention, the hard mask layer 211 may be a contact etch stop layer composed of a single layer or a plurality of layers of tantalum nitride, tantalum carbide or tantalum carbonitride. Preferably, a layer of tantalum nitride which can be stressed is applied.

Then, a first etching process is performed to remove a portion of the hard mask layer 211 and a portion of the polysilicon device layer 207, thereby defining an opening 211a on the hard mask layer 211, and among the passive components 203, An alcove 213 is formed to expose the remaining polysilicon component layer 207 to the outside via the opening 211a (as shown in FIG. 2D).

Subsequently, on the dummy gate 202 and the passive component 203, an inner dielectric layer 214 is formed and the recess 213 is filled. Thereafter, the inner dielectric layer 214 is planarized by using the hard mask layer 211 as a polishing stop layer (as shown in FIG. 2E). In a preferred embodiment of the invention, the planarization of the inner dielectric layer 214 includes a chemical mechanical polishing process.

Thereafter, a second etching process is performed using the dielectric material layer 204 as an etch stop layer to remove a portion of the hard mask layer 211 overlying the dummy gate 202, and the polysilicon gate electrode 206 located in the dummy gate 202. Therefore, the opening 211b is defined on the hard mask layer 211, and the concave chamber 215 is formed in the dummy gate 202, so that the dielectric material layer 204 is exposed to the outside through the concave chamber 215 and the opening 211b (as shown in FIG. 2F). Show).

In some embodiments of the present invention, the second etching process may use both dry etching and wet etching. In this embodiment, it is first The hard mask layer 211 is removed by dry etching; the polysilicon gate electrode 206 is removed by wet etching.

After the polysilicon gate electrode 206 is removed, a gate dielectric layer 208 having a high dielectric constant is formed on the dielectric material layer 204 exposed through the recess 215 and the opening 211b. In the present embodiment, the gate dielectric layer 208. The method includes: a high-k material layer 208a and a cover layer 208b stacked on the interface material layer 204 in sequence.

Next, at least one work function layer 216 is formed on the high dielectric constant material layer 208a; a metal layer is deposited on the work function layer 216; and the metal layer is planarized to form a metal gate including the metal gate electrode 217. Structure 218 completes the fabrication of semiconductor device structure 200 (as depicted in Figure 2G). Subsequent metal contact processes are performed to form a plurality of metal contacts that are in electrical contact with the metal interconnects (not shown).

Referring again to FIG. 2G, the semiconductor device structure 200 includes a metal gate structure 218, a hard mask layer 211, and a passive component 203. The hard mask layer 211 covers the metal gate structure 218 and the sidewalls of the passive component 203, and conforms to the metal gate structure 218 and the first spacer 209 of the passive component 203 and the second spacer 210.

In addition, the hard mask layer 211 has two openings, such as openings 211a and 211b, for respectively exposing the metal gate electrode 217 of the metal gate structure 218 and the polysilicon component layer 207 of the passive component 203 to the outside. Although openings 211a and 211b are defined by two different etching processes, respectively. However, since after two different etching processes, the hard mask layer 211 will again undergo at least one planarization step such that the openings 211a and 211b are substantially coplanar with each other. That is to say, both the metal gate structure 218 and the passive component 203 can perform subsequent metal contact processes on the same plane.

Further, since the polysilicon component layer 207 constituting the passive component 203 is being carried out During the first etching process, partial removal is performed such that the thickness of the polysilicon device layer 207 is less than the thickness of the metal gate electrode 217, the gate dielectric layer 208, and the work function layer 216 of the replacement polysilicon gate electrode 206. Therefore, after the metal gate electrode 217, the gate dielectric layer 208 and the work function layer 216 pass through the metal planarization step, there is still a height drop H between the polysilicon component layer 207 and the opening 211b. That is, although the openings 211b and 211a exposing the metal gate electrode 217 and the polysilicon device layer 207 are substantially coplanar with each other, the distance between the opening 211b and the metal gate electrode 217 is substantially smaller than the opening 211a and the polysilicon component layer 207. the distance between.

In accordance with the above, embodiments of the present invention provide a semiconductor device structure that integrates a metal gate electrode transistor with a passive component. The way of making it is to cover the polysilicon virtual gate electrode and the passive component with a hard mask. The passive component is then subjected to a first etching process to remove a portion of the hard mask and expose a portion of the polysilicon component layer of the passive component. Thereafter, a second etching process is performed to remove the polysilicon dummy gate. Metal gate electrode deposition and planarization processes are subsequently performed to form metal gate electrodes and passive components that are coplanar with each other.

By thinning the passive component and removing the dummy gate by two etching processes, the passive component and the metal gate electrode can perform subsequent metal contact processes on the same plane, and reduce the metal residue of the passive component polysilicon component layer. Improve the performance of components.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧Semiconductor component structure

101‧‧‧Substrate

102‧‧‧virtual gate

103‧‧‧ Passive components

104‧‧‧Dielectric material layer

104a‧‧‧Interface

104b‧‧‧High dielectric constant material layer

105‧‧‧ Polysilicon layer

106‧‧‧Polysilicon gate electrode

107‧‧‧ Polysilicon component layer

108‧‧‧gate dielectric layer

109‧‧‧First gap

110‧‧‧Second gap

111‧‧‧hard mask layer

111a‧‧‧ openings

111b‧‧‧ openings

112‧‧‧ patterned photoresist layer

113‧‧ ‧ alcove

114‧‧‧ Inner dielectric layer

115‧‧ ‧ alcove

116‧‧‧Work function layer

117‧‧‧Metal gate electrode

118‧‧‧Metal gate structure

119‧‧‧汲polar/source structure

120‧‧‧ Coverage

200‧‧‧Semiconductor component structure

201‧‧‧Substrate

202‧‧‧virtual gate

203‧‧‧ Passive components

204‧‧‧Dielectric material layer

205‧‧‧ Polysilicon layer

206‧‧‧Polysilicon gate electrode

207‧‧‧ Polysilicon component layer

208‧‧‧gate dielectric layer

208a‧‧‧High dielectric constant material layer

208b‧‧‧ Coverage

209‧‧‧ first gap wall

210‧‧‧Second gap

211‧‧‧ Hard mask layer

211a‧‧‧ openings

211b‧‧‧ openings

212‧‧‧ patterned photoresist layer

213‧‧ ‧ alcove

214‧‧‧ Inner dielectric layer

215‧‧ ‧ alcove

216‧‧‧Work function layer

217‧‧‧Metal gate electrode

218‧‧‧Metal gate structure

219‧‧‧Bunging/source structure

H‧‧‧ height drop

1A through 1G are cross-sectional views showing a series of process structures for fabricating a semiconductor device structure in accordance with a preferred embodiment of the present invention.

2A through 2G are cross-sectional views showing a series of process structures for fabricating a semiconductor device structure in accordance with another preferred embodiment of the present invention.

200‧‧‧Semiconductor component structure

201‧‧‧Substrate

203‧‧‧ Passive components

204‧‧‧Dielectric material layer

207‧‧‧ Polysilicon component layer

208‧‧‧gate dielectric layer

208a‧‧‧High dielectric constant material layer

208b‧‧‧ Coverage

209‧‧‧ first gap wall

210‧‧‧Second gap

211‧‧‧ Hard mask layer

211a‧‧‧ openings

211b‧‧‧ openings

214‧‧‧ Inner dielectric layer

216‧‧‧Work function layer

217‧‧‧Metal gate electrode

218‧‧‧Metal gate structure

219‧‧‧Bunging/source structure

H‧‧‧ height drop

Claims (14)

A semiconductor device structure comprising: a metal gate structure having a metal gate electrode; a passive component on an isolation structure adjacent to the metal gate structure and having a polysilicon component layer, wherein the passive component is a And a hard mask layer covering the metal gate structure and the passive component, and having a first opening and a second opening substantially coplanar to respectively form the metal gate electrode and the polysilicon component layer Exposed to the outside; wherein an upper surface of the metal gate electrode has a height difference from an upper surface of the polysilicon component layer. The semiconductor device structure of claim 1, further comprising: a substrate; a drain/source structure located in the substrate adjacent to the metal gate electrode; and a gate dielectric layer, Located between the drain/source structure and the metal gate electrode. The semiconductor device structure of claim 2, wherein the gate dielectric layer comprises: an interfacial layer (IL) sequentially stacked on the substrate and a high-k material layer. The semiconductor device structure of claim 3, further comprising a capping layer between the high-k material layer and the metal gate electrode. The semiconductor device structure of claim 1, further comprising: a first spacer between the metal gate electrode and the hard mask layer; and a second spacer disposed on the polysilicon assembly layer Between the hard mask layers. A method of fabricating a semiconductor device structure, comprising: providing a dummy gate structure and a passive component, wherein the dummy gate has a polysilicon gate electrode, and the passive component has a polysilicon device layer; Forming a hard mask layer on the passive component; performing a first etching process to remove a portion of the hard mask layer, thereby exposing a portion of the polysilicon component layer to the outside, and removing one Part of the polysilicon component layer, thereby exposing the remaining polysilicon device layer to the outside; forming an inner layer dielectric (ILD) on the dummy gate and the passive component; The curtain layer is a polishing termination layer, planarizing the inner dielectric layer; performing a second etching process to remove the polysilicon gate electrode; and forming a metal gate electrode at the original position of the polysilicon gate electrode. The method for fabricating a semiconductor device structure according to claim 6, wherein the step of forming the dummy gate and the passive component comprises: forming a dielectric material layer and a polysilicon material layer sequentially on a substrate. Patterning the polysilicon material layer and the dielectric material layer to form the polysilicon gate electrode and the polysilicon device layer on the patterned dielectric material layer; A first spacer and a second spacer are formed on the sidewalls of the polysilicon gate electrode and the polysilicon assembly layer, respectively. The method of fabricating a semiconductor device structure according to claim 7, wherein the dielectric material layer comprises: an interface layer sequentially stacked on the substrate and a high dielectric constant material layer. The method for fabricating a semiconductor device structure according to claim 8, further comprising forming a cap layer between the high dielectric constant material layer and the polysilicon material layer. The method of fabricating a semiconductor device structure according to claim 9, wherein before forming the metal gate electrode, further comprising: forming at least one work function layer on the cover layer. The manufacturing method of the semiconductor device structure of claim 7, wherein before the performing the second etching process, the method further comprises: forming a drain/source in the substrate by using the dummy gate as a mask Pole structure. The method for fabricating a semiconductor device structure according to claim 7, wherein before forming the metal gate electrode, further comprising: forming a high dielectric constant material layer at an original position of the polysilicon gate electrode; At least one work function layer is formed on the high dielectric constant material layer. The method of fabricating a semiconductor device structure according to claim 6, wherein the second etching process comprises a dry etching and a wet etching. The method of fabricating a semiconductor device structure according to claim 6, wherein the planarization of the inner dielectric layer comprises: a chemical mechanical polishing (CMP).