TWI852004B - Processing method and system of checking offset between rfid tag's antenna and chip - Google Patents

Abstract

A processing method and system of checking offset between RFID tag's antenna and chip is provided. The processing system comprises a storage device and a process unit. The process unit performs the following steps. Fetch a input image and the input image comprises a first anchor point and a second anchor point. Perform a chip image process for the input image and outputs a chip edge image. Perform an antenna image process for the input image and output an antenna edge image. Perform a Hough transform process for the chip edge image and the antenna edge image, and output a Hough chip edge image and a Hough antenna edge image. Calculating an offset angle according to an antenna edge of the Hough antenna edge image and a chip edge of the Hough chip edge image. Generating a connecting line according to the first anchor point and the second anchor point. Acquiring an antenna image midpoint according to the Hough antenna edge image and the connecting line. Acquiring a chip image midpoint according to the Hough chip edge image. Calculating a offset distance according to the antenna image midpoint and the chip image midpoint. Generating a compare result according to the offset angle and the offset distance.

Description

Processing method and system for detecting the position accuracy of antenna and chip of RFID tag

A method and system for detecting object deviation using digital images, and in particular, a processing method and system for detecting the position accuracy of antenna and chip of RFID tags.

With the rapid growth of communication technology, the packaging demand for antennas and chips has also been driven. For example: the antenna and chip packaging of Radio Frequency Identification (RFID) tags. During the packaging process, the chip may be affected by interference, causing the chip position to shift outside the preset position. Therefore, the packaging results need to be inspected during production. Since the antenna and chip after packaging are too small, it is difficult for inspectors to directly judge whether the chip position is offset with the naked eye. In addition, if the chip position offset or missing (chip not attached) can be immediately discovered during the production process, the machine can be stopped as soon as possible to correct the oversight of the production process, reduce waste and improve production yield.

In view of this, in some embodiments, a processing method for detecting the position accuracy of the antenna and chip of an RFID tag is provided, which is used to determine whether the chip in the antenna is skewed or misaligned through object recognition and related processing of digital images, and combined with a fast processing Hough transformation program. The processing method for detecting the position accuracy of the antenna and chip of an RFID tag includes the following steps: obtaining an input image, the input image includes a first positioning area; executing a chip image program on the input image to generate a chip outline block; executing an antenna image program on the input image to generate an antenna outline block; executing a Hough transformation program on the chip outline block and the antenna outline block respectively, generating a Hough chip outline block and a Hough antenna outline block respectively; selecting a Hough An antenna boundary of the antenna outline block and a chip boundary of the Hough chip outline block; obtain an offset angle according to the antenna boundary and the chip boundary; obtain a connecting line segment passing through the first positioning area; obtain the center point of the antenna block according to the Hough antenna outline block and the connecting line segment; obtain the center point of the chip block according to the Hough chip outline block; obtain an offset according to the center point of the antenna block and the center point of the chip block; generate a comparison result according to the offset angle and the offset.

In some embodiments, the chip image processing includes a chip contour recognition process, which further includes: identifying multiple rectangular blocks in the chip binary image; judging whether the target chip exists in the rectangular block in the chip selection box; if the target chip exists in the chip binary image, removing the rectangular blocks of other non-target chips in the chip binary image and generating a chip contour block; if the target chip does not exist in the chip binary image, generating a judgment result of "unqualified".

In some embodiments, the antenna image program includes an antenna outline recognition program in the execution, and the step further includes: identifying multiple rectangular blocks in the antenna binary image; determining whether the rectangular block in the antenna selection box contains a target antenna; if the target antenna exists in the antenna binary image, removing the rectangular blocks of other non-target antennas in the antenna binary image and generating an antenna outline block; if the target antenna does not exist in the antenna binary image, generating a judgment result of "unqualified".

In some embodiments, after generating the chip outline block and the antenna outline block, the step further includes: determining whether the antenna outline block contains the chip outline block; if the antenna outline block contains the chip outline block, the chip outline block and the antenna outline block perform a Hough transformation procedure; if the antenna outline block does not contain the chip outline block, a judgment result of "unqualified" is generated.

In some embodiments, the step of executing a Hough transformation process on a chip outline block to generate a Hough chip outline block includes: obtaining a selected line segment of the chip outline block in a first dimensional space, wherein the selected line segment has a plurality of chip boundary coordinates; setting a chip transformation angle interval in a second dimensional space; executing a Hough transformation process according to the chip boundary coordinates and the chip transformation angle interval to generate a plurality of chip boundary coordinates in the second dimensional space; chip boundary curves; obtain Hough intersections according to the chip boundary curves, and select at least one Hough intersection; select the target intersection with the largest number of intersections from the Hough intersections; transform the coordinates of the target intersection in the second dimensional space into Hough line segments in the first dimensional space; repeatedly obtain other selected line segments and generate other Hough line segments; draw the Hough chip outline block according to the Hough line segments.

In some embodiments, the step of drawing a Hough chip outline block further includes determining whether the Hough chip outline block is complete.

In some embodiments, the step of executing a Hough transformation procedure on an antenna outline block to generate a Hough antenna outline block includes: obtaining a selected line segment of the antenna outline block in a first dimensional space, wherein the selected line segment has a plurality of antenna boundary coordinates; setting an antenna transformation angle interval in a second dimensional space; executing a Hough transformation procedure according to the antenna boundary coordinates and the antenna transformation angle interval to generate a plurality of antenna boundary coordinates in the second dimensional space. Hough antenna boundary curves; obtain Hough intersections according to the Hough antenna boundary curves, and select at least one Hough intersection; select the target intersection with the largest number of intersections from the Hough intersections; transform the coordinates of the target intersection in the second dimensional space into Hough line segments in the first dimensional space; repeatedly obtain other selected line segments and generate other Hough line segments; draw a Hough antenna outline block according to the Hough line segments.

In some embodiments, the step of drawing a Hough antenna outline block further includes determining whether the Hough antenna outline block is complete.

In some embodiments, a processing system for detecting the position accuracy of the antenna and chip of an RFID tag includes a storage device and a processor. The storage device stores an input image, a chip image program, an antenna image program, a Hough transformation program, and a comparison result, and the input image includes at least a first positioning area; the processor is electrically connected to the storage device, and the processor executes the chip image program and the antenna image program respectively according to the input image, and generates a chip outline block and an antenna outline block; the processor executes the Hough transformation program on the chip outline block and the antenna outline block respectively, and generates a Hough chip outline block and a Hough antenna outline block respectively, and the processor selects the Hough antenna. The processor compares an antenna boundary of a line contour block with a chip boundary of a Hough chip contour block; the processor obtains an offset angle according to the antenna boundary and the chip boundary; the processor obtains a connecting line segment passing through the first positioning area; the processor obtains the center point of the antenna block according to the Hough antenna contour block and the connecting line segment; the processor obtains the center point of the chip block according to the Hough chip contour block; the processor obtains an offset according to the center point of the antenna block and the center point of the chip block; the processor generates a comparison result according to the offset angle and the offset.

In some embodiments, the step of executing a Hough transformation process on a chip outline block by a processor to generate a Hough chip outline block includes: the processor obtains a selected line segment of the chip outline block in a first dimensional space, wherein the selected line segment has a plurality of chip boundary coordinates; the processor sets a chip transformation angle interval in a second dimensional space; the processor executes a Hough transformation process according to the chip boundary coordinates and the chip transformation angle interval to generate a plurality of chip transformation angles in the second dimensional space. Hough chip boundary curves; the processor obtains Hough intersections according to the Hough chip boundary curves and selects at least one Hough intersection; the processor selects the one with the largest number of intersections from the Hough intersections as the target intersection; the processor converts the coordinates of the target intersection in the second dimensional space into a Hough line segment in the first dimensional space; repeatedly obtains other selected line segments and generates other Hough line segments; the processor draws a Hough chip outline block according to the Hough line segments.

In some embodiments, the step of executing a Hough transformation process on the antenna outline block to generate a Hough antenna outline block in a processor includes: the processor obtains a selected line segment of the antenna outline block in a first dimensional space, wherein the selected line segment has a plurality of antenna boundary coordinates; the processor sets an antenna transformation angle interval in a second dimensional space; the processor executes a Hough transformation process according to the antenna boundary coordinates and the antenna transformation angle interval to generate a plurality of antenna boundary coordinates in the second dimensional space. Hough antenna boundary curves; the processor obtains Hough intersections according to the Hough antenna boundary curves and selects at least one Hough intersection; the processor selects the target intersection with the largest number of intersections from the Hough intersections; the processor converts the coordinates of the target intersection in the second dimensional space into Hough line segments in the first dimensional space; repeatedly obtains other selected line segments and generates other Hough line segments; the processor draws a Hough antenna outline block according to the Hough line segments.

The processing method and system for detecting the position accuracy of the antenna and chip of the RFID tag are applied to the antenna image of the target chip to identify whether the position of the chip is offset. The processing method and system for detecting the position accuracy of the antenna and chip of the RFID tag also modify the calculation method of the Hough transform program so that the computational load of the processing system can be reduced and retain high-precision identification results.

100:Processing system

110: Storage equipment

111: Chip imaging program

112: Antenna imaging program

113: Hough Transformation Procedure

114:Comparison results

115: Gray-level program

116: Binarization procedure

117: Wafer profile recognition process

118: Smoothing program

119: Antenna profile recognition procedure

120: Processor

130: Input image

131: Target antenna

132: Chip packaging structure

133: Target chip

134: Carrier

140: Camera unit

410:Chip binary image

411: Rectangular block

412: Edge detection frame

413: Chip selection box

420: chip outline block

510: Smooth Image

511: Antenna selection box

520: Antenna binary image

530: Antenna outline block

610: Select line segment

621: Hough intersection

631: Target intersection

640: Hough line segment

650: Hoff chip outline block

660:Chip block center point

710: Hough antenna outline block

811: Antenna boundary

812: Chip boundary

813:Offset angle

814:Offset

911: First positioning area

912: First center point

921: Second positioning area

922: Second center point

931:Connecting line segment

941: Antenna block center line

942: Center point of antenna block

[Figure 1] is a schematic diagram of the processing system architecture for detecting the antenna and chip position accuracy of the RFID tag in this embodiment.

[Figure 2] is a schematic diagram of an input image of an embodiment.

[Figure 3A] is a schematic diagram of the operation status of a processing method for detecting the position accuracy of the antenna and chip of an RFID tag according to an embodiment.

[Figure 3B] is a schematic diagram of a detection and judgment method for detecting the position accuracy of the antenna and chip of an RFID tag according to an embodiment.

[Figure 4A] is a schematic diagram of a chip binary image of an embodiment.

[Figure 4B] is a schematic diagram of a chip outline block of an embodiment.

[Figure 5A] is a schematic diagram of an input image and a smoothed image of an embodiment.

[Figure 5B] is a schematic diagram of an antenna outline block before removing the rectangular block in an embodiment.

[Figure 6A] is a schematic diagram of a selected line segment and its pixels according to an embodiment.

[Figure 6B] is a schematic diagram of the first dimensional space and the second dimensional space of an embodiment.

[Figure 6C] is a schematic diagram of the selected line segments and Hough line segments of an embodiment.

[Figure 6D] is a schematic diagram of a Hoff chip outline block of an embodiment.

[Figure 7] is a schematic diagram of a Hough antenna outline block of an embodiment.

[Figure 8A] is a schematic diagram of generating a connecting line segment based on the first positioning area according to an embodiment.

[Figure 8B] is a schematic diagram of the offset angle of an embodiment.

[Figure 9] is a schematic diagram of the offset of an embodiment.

Please refer to FIG. 1, which is a schematic diagram of the processing system architecture for detecting the antenna and chip position accuracy of an RFID tag in this embodiment. The processing system for detecting the antenna and chip position accuracy of an RFID tag (hereinafter referred to as the processing system 100) can be applied to electronic devices with computing capabilities such as personal computers, servers, laptops, tablet computers or mobile communication devices. In addition to being able to be executed locally, the processing system 100 can also be connected to a remote server through a network to perform digital image detection.

The processing system 100 at least includes a storage device 110 and a processor 120. The processor 120 is electrically connected to the storage device 110. The processor 120 can be selectively connected to the imaging unit 140. The storage device 110 stores the input image 130, the chip image program 111, the antenna image program 112, the Hough transform program 113 and the comparison result 114. The chip image program 111 is a collection of a grayscale program 115, a binarization program 116 and a chip contour recognition program 117. The antenna image program 112 at least includes a smoothing program 118, a binarization program 116 and an antenna contour recognition program 119.

The input image 130 can be imported from an external file, or obtained by photographing a wireless radio frequency device through the camera unit 140, or a partial block of a digital image can be used as the input image 130. Please refer to Figure 2, the input image 130 is a frontal image of at least the target chip 133 and the target antenna 131 of the RFID tag taken from a top view, which is a schematic diagram of the input image of an embodiment. The upper part of Figure 2 is a schematic diagram of the photographed image of the complete target antenna 131 and the target chip 133 in the RFID tag; the lower part of Figure 2 is a partial enlarged view of the RFID tag of the aforementioned input image 130; wherein the input image 130 at the lower part of Figure 2 corresponds to the dotted frame of the photographed image at the upper part of Figure 2.

Please continue to refer to Figure 2. The central blunt-cornered square structure of the input image 130 is a chip package structure 132, and the rest is a carrier 134. The chip package structure 132 includes a target chip 133. The chip package structure 132 is a structure formed by bonding the target chip 133 and the target antenna 131 with conductive glue. Generally speaking, the chip package structure 132 of Figure 2 is a correctly bonded state. In actual situations, the chip package structure 132 may fail to bond to the two target antennas 131, or only one side is connected to the target antenna 131.

In order to distinguish the difference between the target antenna 131 and the target chip 133, a horizontal line is used in the target antenna 131. The target chip 133 packaged in the target antenna 131 is represented by a grid. There are multiple holes distributed in the target antenna 131 and the target chip 133, which represent bubbles or other dust generated during packaging. In addition, the black area of the chip packaging structure 132 is also a defect generated during the packaging process. The input image 130 can be a color image or a grayscale image.

Please refer to FIG. 3A and FIG. 3B, which are schematic diagrams of the operation state and detection judgment of a processing method for detecting the position accuracy of the antenna and chip of an RFID tag in an embodiment. After the processor 120 obtains the input image 130, the processing method for detecting the position accuracy of the antenna and chip of the RFID tag includes the following steps: Step S210: obtaining the input image 130, the input image 130 includes the first positioning area 911 and the second positioning area 921; Step S220: executing the chip image program 111 on the input image 130 to generate a chip wheel Step S230: Execute the antenna image program 112 on the input image 130 to generate the antenna outline block 530; Step S240: Execute the Hough transformation program 113 on the chip outline block 420 and the antenna outline block 530 to generate the Hough chip outline block 650 and the Hough antenna outline block 710 respectively; Step S250: Select the Hough antenna The antenna boundary 811 of the outline block 710 and the chip boundary 812 of the Hough chip outline block 650; Step S260: Obtain an offset angle 813 according to the antenna boundary 811 and the chip boundary 812; Step S270: Generate a connecting line segment 931 according to the first positioning area 911 and the second positioning area 921; Step S280: Generate a connecting line segment 931 according to the Hough antenna outline block 710 and the connecting line segment 931; Step S281: Generate a connecting line segment 931 according to the Hough antenna outline block 710 and the connecting line segment 931; Step S290: Generate a connecting line segment 931 according to the Hough antenna outline block 710 and the connecting line segment 931; Step S291: Generate a connecting line segment 931 according to the Hough antenna outline block 710 and the connecting line segment 931; Step S292: Generate a connecting line segment 931 according to the Hough antenna outline block 710 and the connecting line segment 931; Step S293: Generate a connecting line segment 931 according to the Hough antenna outline block 710 and the connecting line segment 931; Step S294: Generate a connecting line segment 931 according to the Hough antenna outline block 710 and the connecting line segment 931; Step S295: Generate a connecting line segment 931 according to the Hough antenna outline block 710 and the connecting line segment 931; Step S296: Generate a connecting line segment 931 according to the Hough antenna outline block 710 and the connecting line segment 931; Step S297: Generate a connecting line segment 931 according to the Hough antenna outline block 710 and the connecting line segment 931; Step S298: Generate a connecting line segment 931 according to the Hough antenna outline block 71 Line segment 931 is used to obtain the center point 942 of the antenna block; step S290: obtaining the center point 660 of the chip block according to the Hough chip outline block 650; step S300: obtaining the offset 814 according to the center point 942 of the antenna block and the center point 660 of the chip block; and step S310: generating a comparison result 114 according to the offset angle 813 and the offset 814.

First, the processing system 100 obtains the input image 130. The processor 120 loads the input image 130 into the chip imaging program 111 and the antenna imaging program 112 respectively. The processor 120 can execute the chip imaging program 111 or the antenna imaging program 112 in time-sharing or synchronous manner according to its computing power.

Please refer to FIG. 2 , which is a chip imaging program 111 as a priority. If the input image 130 is a color image, the processor 120 executes the grayscale program 115 on the input image 130 and generates a grayscale image. The pixel grayscale distribution of the grayscale program 115 can be linearly adjusted according to the input image 130. If the input image 130 is a grayscale image, the processor 120 can choose to skip the execution of this grayscale program 115.

Please refer to FIG. 3A, FIG. 3B and FIG. 4A, wherein FIG. 4A is a schematic diagram of a chip binary image of an embodiment. The processor 120 performs a binary process 116 on the grayscale image and generates a chip binary image 410. Then, the processor 120 loads the chip binary image 410 into the chip contour recognition process 117. The chip contour recognition process 117 recognizes and removes the target chip 133 and the rectangular block 411 from the chip binary image 410. The chip contour recognition procedure 117 includes the following steps: step S410: identifying multiple rectangular blocks 411 in the chip binary image 410; step S420: judging whether the rectangular block 411 in the chip selection box 413 contains the target chip 133; step S430: if the rectangular block 411 of the target chip 133 exists in the chip binary image 410, then removing the rectangular blocks 411 of other non-target chips 133 in the chip binary image 410 and generating a chip contour block 420; and step S440: if the target chip 133 does not exist in the chip binary image 410, then generating a judgment result of "unqualified".

Please refer to FIG. 4A , the chip contour recognition program 117 is mainly aimed at the range of the chip package structure 132 in the chip binary image 410. The chip contour recognition program 117 moves an edge detection frame 412 of n*m pixels in the chip binary image 410 and identifies the rectangular block 411 covered by the edge detection frame 412. The upper part of FIG. 4A is a partial enlarged schematic diagram of the edge of the target chip 133 in the chip package structure 132. Assuming that the edge detection frame 412 is 3*3 pixels in size, the chip contour recognition program 117 regards the edge adjacent pixel combination of the target chip 133 in the edge detection frame 412 as a rectangular block 411. Next, the chip contour recognition program 117 performs splicing based on the edge detection frame 412 and the detected rectangular block 411. The chip contour recognition program 117 determines that the set of rectangular blocks 411 in different areas of the chip binary image 410 is the target chip 133 or a package defect.

Please refer to FIG4B. After the chip contour recognition program 117 marks all the rectangular blocks 411 of the chip binary image 410, the chip contour recognition program 117 determines whether the chip binary image 410 has the target chip 133 according to the area range of the chip selection box 413. Generally speaking, the area range of the chip selection box 413 is determined according to the size specifications of the chip type. The solid line box above FIG4B is a schematic diagram of the chip selection box 413. The default position and size of the chip selection box 413 can be determined according to the type of wireless radio frequency equipment. For example, it can be preset to a rectangular range equivalent to the chip area in FIG4B. Because the target chip 133 is disturbed and displaced during the packaging process. Therefore, the target chip 133 in the input image 130 may not be in the preset position, or the target chip 133 may be slightly skewed. Therefore, the range of the chip selection box 413 will be slightly larger than the target chip 133. The chip contour recognition program 117 can recognize the target chip 133 and its position in the chip binary image 410 through the chip selection box 413.

Please refer to FIG. 4B , which is a schematic diagram of a chip outline block 420 of an embodiment. Since the target chip 133 is disturbed and displaced during the packaging process, the target chip 133 may not be in the preset position in the input image 130, or the target chip 133 may be slightly skewed. The chip outline recognition program 117 determines whether the overlapping area range ratio of the chip selection box 413 and the target chip 133 meets the threshold value. If the overlapping area of the chip selection box 413 and the target chip 133 does not meet the threshold value, the chip outline recognition program 117 determines that the target chip 133 generates a corresponding judgment result of "unqualified". Taking FIG. 4B as an example, the target chip 133 is represented by a black block. The chip contour recognition program 117 compares the black area of the target chip 133 with the area of the chip selection box 413, and the chip contour recognition program 117 can determine whether the ratio of the target chip 133 to the chip selection box 413 meets the threshold value.

The chip contour recognition program 117 removes all the rectangular blocks 411 of other non-target chips. The rectangular block 411 in FIG. 4B is represented by a dashed frame. The upper part of FIG. 4B shows the chip package structure 132 without removing the rectangular block 411, and the lower part of FIG. 4B shows the chip contour block 420. The overall image size of the chip contour block 420 is the same as the input image 130, and FIG. 4B only shows the target chip 133 in the chip contour block 420. If the chip contour recognition program 117 cannot recognize the target chip 133 from the chip binary image 410, the chip contour recognition program 117 generates a judgment result of "unqualified".

The processor 120 also executes the antenna image program 112, which is composed of a smoothing program 118, a binarization program 116, and an antenna contour recognition program 119. The processor 120 loads the input image 130 into the smoothing program 118 and generates a smoothed image 510, as shown in FIG5A. In other embodiments, the antenna image program 112 is composed of a grayscale program 115, a smoothing program 118, a binarization program 116, and an antenna contour recognition program 119. Therefore, the processor 120 can also selectively execute the grayscale program 115 on the smoothed image 510 to generate a smoothed grayscale image (no label), as shown in FIG3A and FIG3B. The following antenna image program 112 is described as a combination of the smoothing program 118 and the binarization program 116.

The smoothing program 118 may be, but is not limited to, a smoothing linear filter, a median filter, an ideal lowpass filter (2-D ILPF), or a Butterworth Ideal lowpass filter. , BILF) or Gaussian lowpass filter (Gaussian lowpass filter, GLPF) implementation. The input image 130 is passed through the smoothing process 118 to reduce noise in the image. In FIG. 5A , the input image 130 is generated into a smoothed image 510 after being processed by the smoothing process 118 . The smooth image 510 can filter out multiple smaller range noises in the input image 130 .

The processor 120 executes the binarization process 116 on the smoothed image 510 to generate an antenna binarization image 520 corresponding to the smoothed image 510. Then, the processor 120 loads the antenna binarization image 520 into the antenna contour recognition process 119. The antenna contour recognition process 119 recognizes and removes the rectangular block 411 from the antenna binarization image 520. The antenna outline recognition procedure 119 includes the following steps, and please refer to FIG. 3B: Step S510: Identify multiple rectangular blocks 411 in the antenna binary image 520; Step S520: Determine whether there is a target antenna 131 according to the rectangular block 411 in the antenna selection box 511; Step S530: If there is a rectangular block 411 of the target antenna 131 in the antenna binary image 520, remove the rectangular blocks 411 of other non-target antennas 131 in the antenna binary image 520, and generate an antenna outline block 530; and Step S540: If there is no target antenna 131 in the antenna binary image 520, generate a judgment result of "unqualified".

The antenna contour recognition process 119 recognizes the rectangular block 411 in the antenna binary image 520. As described in the chip contour recognition process 117, the antenna contour recognition process 119 also adopts the recognition process of the edge detection frame 412. The size of the edge detection frame 412 of the antenna contour recognition process 119 can be different from or the same as the size of the edge detection frame 412 of the chip contour recognition process 117. The antenna contour recognition process 119 is for the entire range of the input image 130, which includes the target antenna 131 and the chip package structure 132. The antenna contour recognition process 119 removes all the rectangular blocks 411 of other non-target antennas 131 to obtain the block image of the target antenna 131. Please refer to FIG. 5B , which is a schematic diagram of an antenna outline block with the rectangular block 411 removed according to an embodiment.

The antenna contour recognition program 119 determines whether the target antenna 131 exists in the rectangular block 411 according to the antenna selection box 511. As in the determination method of the chip selection box 413 described above, the antenna contour recognition program 119 determines whether the overlapping area ratio of the antenna selection box 511 and the target antenna 131 meets the threshold value. If the overlapping area of the antenna selection box 511 and the target antenna 131 meets the threshold value, the antenna contour recognition program 119 will regard the target antenna 131 as existing. On the contrary, when the overlapping area of the antenna selection box 511 and the target antenna 131 does not meet the threshold value, the antenna contour recognition program 119 generates a judgment result of "failure".

After completing the chip profile block 420 and the antenna profile block 530, the processor 120 executes the Hough transformation program 113 on the chip profile block 420 and the antenna profile block 530 respectively. The processor 120 can execute the chip profile block 420 and the antenna profile block 530 in time-sharing or synchronous manner according to its computing power. First, the operation of the Hough transformation program 113 is explained using the chip profile block 420.

Step S610: obtaining a selected line segment 610 of a chip outline block 420 in a first dimension space; Step S620: setting a chip conversion angle interval in a second dimension space; Step S630: executing a Hough transformation procedure 113 according to the chip boundary coordinates and the chip conversion angle interval to generate a plurality of Hough chip boundary curves in the second dimension space; Step S640: obtaining a Hough intersection 621 according to the Hough chip boundary curve, and selecting at least one Hough intersection point 621; step S650: select the target intersection 631 with the largest number of intersections from the Hough intersections 621; step S660: transform the coordinates of the target intersection 631 in the second dimensional space into a Hough line segment 640 in the first dimensional space; step S670: repeatedly obtain other selected line segments 610 and generate corresponding Hough line segments 640; and step S680: draw a Hough chip outline block 650 based on the Hough line segment 640.

The processor 120 selects a selected line segment 610 in any boundary of the chip outline block 420. In order to clearly explain the operation process of the Hough transform program 113, the pixel coordinate set of the input image 130 is regarded as the first dimensional space (no label). Since the input image 130 is a plane image, the first dimensional space is also a two-dimensional space. The origin of the first dimensional space can be the edge corner of the input image 130, or it can be determined by the user. In the following, the upper left corner of the input image 130 is used as the origin, and the boundary of the first dimensional space is the image length and width of the input image 130.

Since the chip outline block 420 can be regarded as a pixel set in the first dimensional space, each pixel of the chip outline block 420 can correspond to a different coordinate in the first dimensional space, as shown in FIG6A. The coordinate set of the aforementioned selected line segment 610 is called the chip boundary coordinate. The processor 120 sets the chip conversion angle interval of the second dimensional space generated by the Hough transformation program 113. The Hough transformation program 113 can represent the rectangular coordinates (x, y) of the first dimensional space with polar coordinates (ρ, θ), where ρ is the intercept between the origin of the first dimensional space and the selected straight line, and θ is the angle between the intercept and the horizontal axis X. The conversion formula between polar coordinates and rectangular coordinates is as follows: x cos(θ)+y sin(θ)=ρ, where ρ is the intercept from the origin to the target, and θ is the angle.

The wafer conversion angle interval is the interval range of the included angle θ. The processor 120 may determine the range of the wafer conversion angle interval based on the computing power or the size of the wafer outline block 420 . The range of the wafer conversion angle interval may be but is not limited to [-180°~+180°]. Next, one of the wafer boundary coordinates is selected as the target coordinate (no label). The processor 120 performs the Hough transformation procedure 113 on the target coordinates according to the wafer conversion angle intervals, and obtains the generation results of the target coordinates for all wafer conversion angle intervals. After passing through the Hough transformation procedure 113, the wafer transformation angle interval of the target coordinates will generate a Hough wafer boundary curve in the second dimensional space (unlabeled).

Next, the processor 120 performs the aforementioned Hough transformation procedure 113 on the remaining chip boundary coordinates. Please refer to FIG. 6B , the upper part of FIG. 6B is the first dimensional space, and the lower part of FIG. 6B is the Hough chip boundary curve after the chip boundary coordinates are converted to the second dimensional space. Different Hough chip boundary curves will intersect with each other, and the position where different curves intersect is called the Hough intersection 621. The processor 120 will count the number of intersections of each Hough intersection 621, and the number of intersections is the number of curves passing through the Hough intersection 621. If the Hough chip boundary curves cannot intersect with each other to generate the Hough intersection 621, it means that there may be an abnormal problem in the chip contour block 420.

The processor 120 selects the one with the largest number of intersections from all the Hough intersections 621 in the chip conversion angle interval as the target intersection 631. The processor 120 converts the coordinates of the target intersection 631 into the first dimension space, and records the Hough line segment 640 of the target intersection 631 in the first dimension space. FIG. 6C corresponds to the chip outline block 420 of FIG. 6A. The selected line segment 610 of FIG. 6A is processed as described above to obtain the Hough line segment 640 of FIG. 6C. The processor 120 repeatedly selects other selected line segments 610 from the chip outline block 420 to obtain the corresponding Hough line segment 640, as shown in FIG. 6D. The processor 120 draws a Hough chip outline block 650 based on all the Hough line segments 640. The chip outline block 420 in FIG. 6D is only used to illustrate the relative position of the Hough line segment 640. In fact, the chip outline block 420 does not need to be displayed. The chip outline block 420 in FIG. 6D is represented by a gray dotted line block.

Next, the processor 120 performs a Hough transformation procedure 113 on the antenna outline block 530. The Hough transformation procedure 113 for the antenna outline block 530 includes the following steps: Step S710: Obtain the selected line segment 610 of the antenna outline block 530 in the first dimension space; Step S720: Set the antenna transformation angle interval in the second dimension space; Step S730: Execute the Hough transformation procedure 113 according to the antenna boundary coordinates and the antenna transformation angle interval to generate multiple Hough antenna boundary curves in the second dimension space; Step S740: Obtain the Hough intersection according to the Hough antenna boundary curve point 621, and select at least one Hough intersection 621; step S750: select the target intersection 631 with the largest number of intersections from the Hough intersections 621; step S760: transform the coordinates of the target intersection 631 in the second dimensional space into a Hough line segment 640 in the first dimensional space; step S770: repeatedly obtain other selected line segments 610 and generate the corresponding Hough line segment 640; and step S780: draw a Hough antenna outline block 710 based on the Hough line segment 640.

The processor 120 selects any selected line segment 610 from the antenna outline block 530. Each pixel of the selected line segment 610 has a corresponding antenna boundary coordinate. The processor 120 sets the antenna conversion angle range in the first dimension. Generally speaking, the antenna conversion angle range can be equivalent to the chip conversion angle range. Or the range of the chip conversion angle range is different from the range of the antenna conversion angle range according to the computing power of the processor 120. The processor 120 executes the Hough transformation program 113 according to the antenna boundary coordinates and the antenna conversion angle range, and obtains multiple Hough antenna boundary curves in the second dimension. Different Hough antenna boundary curves will intersect with each other, and the position where different curves intersect is called the Hough intersection 621. The processor 120 counts the number of intersections of each Hough intersection 621, which is the number of curves passing through the Hough intersection 621. If the Hough antenna boundary curves cannot intersect with each other to generate the Hough intersection 621, it means that there may be an abnormal problem in the antenna outline block 530.

The processor 120 selects the target intersection 631 with the largest number of intersections from the Hough intersections 621 formed by multiple Hough antenna boundary curves according to the antenna conversion angle interval. In other words, the processor 120 will search for intersections in the antenna conversion angle interval and count the number of intersections. The processor 120 converts the coordinates of the target intersection 631 into a Hough line segment 640 in the first dimensional space, as shown in FIG7 . The antenna outline block 530 has two sets of left and right sides in the vertical direction and four sets of sides in the horizontal direction. Generally speaking, the vertical direction is the normal direction of the width of the input image 130. However, in practice, the vertical direction can also be based on the normal of the width, and an angle range is set on the normal, and the angle range of the normal can be regarded as the vertical direction. Similarly, the horizontal direction can also be the direction of the normal extension of the long side (height) of the input image 130, or the direction of the angle range with the normal. Therefore, the Hough antenna outline block 710 also includes two sets of vertical side edges and four sets of horizontal side edges of the target antenna 131. Hough line segments 640. In FIG. 7, the antenna outline block 530 is only used to illustrate the relative position of the Hough line segments 640. In fact, the antenna outline block 530 does not need to be displayed. In FIG. 7, the antenna outline block 530 is represented by a gray block.

After obtaining the Hoff chip outline block 650 or the Hoff antenna outline block 710, the processor 120 determines whether the Hoff chip outline block 650 and the Hoff antenna outline block 710 are complete, and please refer to FIG. 3B. The processor 120 sequentially selects the Hoff line segments 640 on any two sides of the Hoff chip outline block 650, and determines whether the angle of the selected two Hoff line segments 640 meets the preset angle. If the angle of the Hoff line segments 640 on the opposite sides does not meet the preset angle, it means that the Hoff chip outline block 650 may be abnormal, and the judgment result is "unqualified", such as chip damage or recognition error. Generally speaking, the processor 120 compares two Hough line segments 640 at least twice, such as the two Hough line segments 640 on the upper and lower sides or the left and right sides or the two adjacent sides. When any side has two Hough line segments 640 at the same time, it means that the Hough chip outline block 650 may have an abnormal problem and the judgment result is "unqualified". The processor 120 generates corresponding detection results based on the two Hough line segments 640.

In addition, the processor 120 will also perform a complete contour detection on the Hough antenna contour block 710. As mentioned above, the Hough antenna contour block 710 includes two sets of left and right sides in the vertical direction and four sets of Hough line segments 640 in the horizontal direction, please refer to the dotted line below Figure 7. The processor 120 determines whether the angle of the Hough line segments 640 on the left and right sides meets the preset angle. At the same time, the processor 120 also determines whether the four sets of horizontal Hough line segments 640 extend and intersect with the Hough line segments 640 on the two sides in the vertical direction. When the angle meets the preset angle and there is an intersection, the processor 120 generates a correct detection result.

After confirming that the Hough chip outline block 650 and the Hough antenna outline block 710 are normal, the processor 120 selects any Hough line segment 640 from the Hough antenna outline block 710 as the antenna boundary 811. The antenna boundary 811 can be the left and right sides of the Hough antenna outline block 710 in the vertical direction and the four sides in the horizontal direction. Taking Figures 7 and 8A as examples, the processor 120 can select any one of the Hough line segments 640 on the left and right sides of Figure 7 in the vertical direction as the antenna boundary 811. The processor 120 can select the corresponding vertical Hough line segment 640 from the Hough chip outline block 650 as the chip boundary 812.

Please refer to FIG. 8A , the processor 120 obtains the offset angle 813 according to the following processing. The processor 120 can obtain the connecting line segment 931 according to either the first positioning area 911 and the second positioning area 921, or the combination of the first positioning area 911 and the second positioning area 921. First, the first positioning area 911 is selected, and the connecting line segment 931 is generated according to the first positioning area 911 as an example.

FIG8A shows the Hough antenna outline block 710 using the input image 130. The processor 120 selects the Hough line segments 640 on opposite sides (i.e., the antenna boundary 811 mentioned above) from the Hough antenna outline block 710. The processor 120 generates a connecting line segment 931 with the first center point 912 of the first positioning area 911 as the origin. The connecting line segment 931 passes through two Hough line segments 640 in the vertical direction, and the connecting line segment 931 is perpendicular to one of the Hough line segments 640. The processor 120 calculates the angle formed by the connecting line segment 931 and the chip boundary 812 on the horizontal side, and the angle is the offset angle 813.

In addition to the aforementioned processing method of obtaining the connecting line segment 931 and the corresponding offset angle 813 using the first positioning area 911, corresponding processing can also be performed through multiple positioning areas. If the input image 130 has a first positioning area 911 and a second positioning area 921, the processor 120 can determine the connecting line segment 931 according to the first positioning area 911 and the second positioning area 921. The appearance or size of the first positioning area 911 or the second positioning area 921 is not limited to that shown in FIG. 8B. The first positioning area 911 and the second positioning area 921 may be, but are not limited to, triangles, circles, squares, rectangles, etc., or may be other polygons, and have the same material as the target antenna 131. They may be in the same shape as the target antenna 131. process, but is not electrically connected to the target antenna 131 . The processor 120 connects the first center point 912 of the first positioning area 911 and the second center point 922 of the second positioning area 921, and the connected line segment is the connecting line segment 931. The processor 120 The corresponding chip boundary 812 obtains an offset angle 813.

The processor 120 generates an antenna block center line 941 (see the black dashed line in FIG. 9 ) based on the Hough line segments 640 on both sides of the vertical direction in the Hough antenna outline block 710. The processor 120 can obtain the antenna block center line 941 based on the average of the two end points of the two Hough line segments 640. The intersection of the antenna block center line 941 and the connecting line segment 931 is the antenna block center point 942 of the Hough antenna outline block 710. The processor 120 calculates the center point of the target chip 133 based on the Hough chip outline block 650, and the center point is referred to as the chip block center point 660. The processor 120 can obtain four sets of intersection coordinates based on the intersection points of the four sets of Hough line segments 640 of the Hough chip outline block 650. The processor 120 sums up the four sets of intersection coordinates and takes the average, thereby obtaining the chip block center point 660 of the Hough chip outline block 650, please refer to Figure 6D. The processor 120 calculates the distance value between the antenna block center point 942 and the chip block center point 660, and the distance value is the antenna block center point 942 and the chip block center point 660 is the offset 814.

In addition, the processor 120 selects any Hough line segment 640 from the Hough antenna outline block 710 as the antenna boundary 811. The antenna boundary 811 can be the long side (i.e., the side in the vertical direction) or the wide side (i.e., the side in the horizontal direction) of the Hough antenna outline block 710. Taking Figures 7 and 9 as examples, the processor 120 can select any one of the left and right sides of Figure 7 as the antenna boundary 811. The Hough chip outline block 650 includes two long sides (i.e., the Hough line segments 640 on the left and right sides). The processor 120 selects the Hough line segments 640 at the corresponding positions from the Hough chip outline block 650 as the chip boundary 812 according to the selected antenna boundary 811.

In other words, if the processor 120 selects the long side from the Hough antenna outline block 710 as the antenna boundary 811, the processor 120 will also select the long side from the Hough chip outline block 650 as the chip boundary 812. The chip boundary 812 of FIG. 9 corresponds to the left Hough line segment 640 of FIG. 6D. Finally, the processor 120 calculates the offset angle 813 between the antenna boundary 811 and the chip boundary 812, as shown in FIG. 9. In other words, the processor 120 obtains the offset angle 813 of the target chip 133 based on the difference in the angle between the antenna boundary 811 and the chip boundary 812. In addition, the processor 120 can also determine the offset angle 813 of the target chip 133 based on other line segments.

Finally, the processor 120 generates the detection results of the target chip 133 and the target antenna 131 according to the offset angle 813 and the offset amount 814. The processor 120 can set different qualified conditions for the offset angle 813 and the offset amount 814 according to different types of RFID tags. For example, the processor 120 determines whether the offset amount 814 meets the preset distance threshold. If the offset amount 814 does not meet the preset distance and the offset angle 813 does not meet the preset angle threshold, the processor 120 will generate a judgment result of "failure". In fact, the processor 120 sets the corresponding judgment standard according to the type of RFID tag, and is not limited to the above example.

In one embodiment, after completing the chip outline block 420 and the antenna outline block 530, the processor 120 can further confirm whether the antenna outline block 530 includes the target chip 133.

Step S910: Determine whether the antenna outline block 530 includes the chip outline block 420; Step S920: If the antenna outline block 530 includes the chip outline block 420, the chip outline block 420 and the antenna outline block 530 perform a Hough transformation procedure; and Step S930: If the antenna outline block 530 does not include the chip outline block 420, the judgment result is "unqualified".

After the processor 120 completes the antenna outline block 530 and the chip outline block 420, the processor 120 checks whether the antenna outline block 530 includes the chip outline block 420. If the antenna outline block 530 includes the chip outline block 420, the processor 120 will continue to execute step S230. On the contrary, if the antenna outline block 530 does not include the chip outline block 420, the judgment result is "unqualified".

In one embodiment, the process of selecting the Hough intersection 621 by the processor 120 further includes the following steps: Step S1010: sequentially adjusting the floating point precision level of the chip conversion angle range, and counting the number of Hough intersections 621 of each floating point precision level; and Step S1020: selecting the Hough intersection 621 with the largest number of intersections as the target intersection 631.

Generally speaking, the larger the chip conversion angle range is, the more Hough chip boundary curves can be obtained. Although more Hough chip boundary curves can obtain more accurate target intersection points 631 and Hough line segments 640, for the processor 120, the larger the chip conversion angle range is, the greater the computational load of the processor 120 will be.

The processor 120 adjusts the chip conversion angle range by changing the floating point precision rank. The processor 120 sorts the number of intersections in each floating point precision rank, and obtains the one with the largest number of intersections from the sorting result as the new target intersection 631. In addition to corresponding to the decimal point system, the aforementioned floating point precision rank can also be applied to scientific notation. The floating point precision rank is explained below using the decimal point system as an example. The floating point precision rank corresponds to the length of the number after the decimal point.

(-10°~+10°)。例如，晶片轉換角度區間在θ={6°~7°}之間具有最多的霍夫交點621，處理器120選擇θ={6°~7°}為新的晶片轉換角度區間。處理器120根據目標交點631為基準且依序移動浮點精度位階。處理器120依次計算θ=6.9,θ=6.8...θ=6.0的霍夫交點621的數量。處理器120將霍夫交點621的數量進行排序，並獲取霍夫交點621數量最大者為目標交點631的坐標值。假設，處理器120在目標交點631的坐標值θ=6.8獲得該區間中最多的霍夫交點621；接著，處理器120根據目標交點631的坐標值θ=6.8並移動浮點精度位階，處理器120從θ=6.80~6.71進行前述的統計與排序。請參考下表1所示，其係為目標交點631的坐標值在各浮點精度位階的交點數量示意表。 Assume that the chip conversion angle range is θ, and θ

(-10°~+10°). For example, the chip conversion angle interval has the most Hough intersections 621 between θ={6°~7°}, and the processor 120 selects θ={6°~7°} as the new chip conversion angle interval. The processor 120 uses the target intersection 631 as a reference and moves the floating point precision level in sequence. The processor 120 calculates the number of Hough intersections 621 of θ=6.9, θ=6.8...θ=6.0 in sequence. The processor 120 sorts the number of Hough intersections 621 and obtains the coordinate value of the target intersection 631 with the largest number of Hough intersections 621. Assume that the processor 120 obtains the most Hough intersections 621 in the interval at the coordinate value θ=6.8 of the target intersection 631; then, the processor 120 performs the aforementioned statistics and sorting from θ=6.80 to 6.71 according to the coordinate value θ=6.8 of the target intersection 631 and moves the floating point precision level. Please refer to Table 1 below, which is a schematic table of the number of intersections at each floating point precision level for the coordinate value of the target intersection 631.

After the processor 120 completes all floating point precision levels, the processor 120 selects the coordinate value of the target intersection 631 at the last level of the floating point precision level as the new target intersection 631. The processor 120 generates a Hough line segment 640 based on the target intersection 631 obtained above. In practice, the processor 120 can determine the number of floating point precision levels based on computing power.

In addition to processing the chip conversion angle interval with floating point precision, in one embodiment, the processor 120 can also adjust the antenna conversion angle interval with floating point precision and select the corresponding target intersection point therefrom.

Step S1110: sequentially adjust the floating point precision level of the antenna conversion angle interval, and count the number of Hough intersections 621 of each floating point precision level; and Step S1120: select the Hough intersection 621 with the largest number of intersections as the target intersection 631.

(-10°~+10°)。經過θ

(-10°~+10°)的霍夫轉換程序113後，假設在θ={0°~2°}具有最多的霍夫交點621。因此處理器120再選出天線轉換角度區間為θ={0°~2°}。請參考下表2，其係為天線轉換角度區間的各浮點精度位階交點數量示意表：

The processor 120 adjusts the antenna conversion angle range by changing the floating point precision level. The processor 120 sorts the number of intersections in each floating point precision level, and obtains the one with the largest number of intersections from the sorting result as the new target intersection 631. Continuing from the previous example, the processor 120 first selects the antenna conversion angle range as θ, and θ

(-10°~+10°). After θ

After the Hough transformation process 113 of (-10°~+10°), it is assumed that the maximum number of Hough intersections 621 is in θ={0°~2°}. Therefore, the processor 120 selects the antenna transformation angle interval as θ={0°~2°}. Please refer to the following Table 2, which is a schematic table of the number of intersections of each floating point precision level in the antenna transformation angle interval:

The processor 120 obtains the corresponding Hough line segment 640 according to Table 1 and Table 2. The processor performs relevant comparison and processing of the antenna boundary 811 and the chip boundary 812 according to the Hough line segment 640.

In one embodiment, the antenna image program 112 may also execute the grayscale program 115 between executing the smoothing program 118 and the binarization program 116, see FIG3A. After the input image 130 is processed by the smoothing program 118, a smoothed image 510 is generated. The processor 120 executes the grayscale program 115 on the smoothed image 510 to generate a smoothed grayscale image (unlabeled). The processor 120 executes the binarization program 116 on the smoothed grayscale image and generates an antenna binarization image 520. The processor 120 performs corresponding processing according to the antenna binarization image 520.

The processing method and system for detecting the position accuracy of the antenna and chip of the RFID tag are applied to the antenna image of the target chip 133 to identify whether the position of the chip is offset. The processing method and system for detecting the position accuracy of the antenna and chip of the RFID tag also modify the calculation method of the Hough transform program 113 so that the computational load of the processing system can be reduced and the high-precision recognition result can be retained.

100:Processing system

110: Storage equipment

111: Chip imaging program

112: Antenna imaging program

113: Hough Transformation Procedure

114:Comparison results

115: Gray-level program

116: Binarization procedure

117: Wafer profile recognition process

118: Smoothing program

119: Antenna profile recognition procedure

120: Processor

130: Input image

131: Target antenna

133: Target chip

140: Camera unit

Claims (35)

A processing method for detecting the position accuracy of the antenna and chip of an RFID tag includes: obtaining an input image by a processor, the input image including a first positioning area; the processor executing a chip image program on the input image to generate a chip outline block; the processor executing an antenna image program on the input image to generate an antenna outline block; the processor executing a Hough transformation program on the chip outline block and the antenna outline block respectively to generate a Hough chip outline block and a Hough antenna outline block respectively; the processor selects the Hough antenna outline The processor obtains an antenna boundary of the block and a chip boundary of the Hough chip outline block; the processor obtains an offset angle according to the antenna boundary and the chip boundary; the processor obtains a connecting line segment passing through the first positioning area; the processor obtains an antenna block center point according to the Hough antenna outline block and the connecting line segment; the processor obtains a chip block center point according to the Hough chip outline block; the processor obtains an offset according to the antenna block center point and the chip block center point; and the processor generates a comparison result according to the offset angle and the offset. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 1, wherein the chip image process includes: executing a grayscale process on the input image to generate a grayscale image; executing a binarization process on the grayscale image to generate a chip binarization image; and executing a chip contour recognition process on the chip binarization image to generate the chip contour block. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 2, wherein the step of executing the chip contour recognition procedure includes: identifying multiple rectangular blocks in the chip binary image; judging whether there is a target chip in the rectangular blocks in a chip selection box; if the target chip exists in the chip binary image, removing the other rectangular blocks in the chip binary image that are not the target chip and generating the chip contour block; and if the target chip does not exist in the chip binary image, generating a judgment result. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 1, wherein the antenna image process includes: executing a smoothing process on the input image to generate a smoothed image; executing a binarization process on the smoothed image to generate an antenna binarization image; and executing an antenna outline recognition process on the antenna binarization image to generate the antenna outline block. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 1, wherein the antenna image process includes: executing a smoothing process on the input image to generate a smoothed image; executing a grayscale process on the smoothed image to generate a grayscale image; executing a binarization process on the grayscale image to generate an antenna binarization image; and executing an antenna outline recognition process on the antenna binarization image to generate the antenna outline block. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 4 or 5, wherein the step of executing the antenna outline recognition procedure includes: identifying multiple rectangular blocks in the antenna binary image; judging whether there is a target antenna in the rectangular blocks according to an antenna selection frame; if the target antenna exists in the antenna binary image, removing the other rectangular blocks in the antenna binary image and generating the antenna outline block; and if the target antenna does not exist in the antenna binary image, generating a judgment result. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 1, wherein before the step of executing the Hough transformation procedure on the chip outline block and the antenna outline block, further includes: the processor determines whether the antenna outline block includes the chip outline block; if the antenna outline block includes the chip outline block, the processor executes the Hough transformation procedure on the chip outline block and the antenna outline block; and if the antenna outline block does not include the chip outline block, the processor generates a judgment result. The processing method for detecting the antenna and chip position accuracy of the RFID tag as described in claim 1, wherein the step of executing the Hough transformation process on the chip outline block to generate the Hough chip outline block includes: obtaining a selected line segment of the chip outline block in a first dimensional space, wherein the selected line segment has a plurality of chip boundary coordinates; setting a chip transformation angle interval in a second dimensional space; executing the Hough transformation process according to the chip boundary coordinates and the chip transformation angle interval to generate A plurality of Hough chip boundary curves in the second dimensional space; a Hough intersection is obtained according to the Hough chip boundary curves, and the processor selects at least one of the Hough intersections; the processor selects the one with the largest number of intersections from the Hough intersections as a target intersection; the coordinates of the target intersection in the second dimensional space are converted into a Hough line segment in the first dimensional space; other selected line segments are repeatedly obtained and other Hough line segments are generated; and the Hough chip outline block is drawn according to the Hough line segments. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 8, wherein the step of selecting the target intersection point from the Hough intersection points with the largest number of intersection points includes: the processor sequentially adjusts a floating point precision level of the chip conversion angle range, and counts the number of the Hough intersection points of each floating point precision level; and selecting the target intersection point from the Hough intersection points with the largest number of intersection points. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 8 further includes the following steps after drawing the Hough chip outline block: The processor determines whether the Hough chip outline block is complete. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 1, wherein the step of executing the Hough transformation process on the antenna outline block to generate the Hough antenna outline block includes: obtaining a selected line segment of the antenna outline block in a first dimensional space, wherein the selected line segment has a plurality of antenna boundary coordinates; setting an antenna transformation angle interval in a second dimensional space; executing the Hough transformation process according to the antenna boundary coordinates and the antenna transformation angle interval to generate A plurality of Hough antenna boundary curves in the second dimensional space; a Hough intersection is obtained according to the Hough antenna boundary curves, and the processor selects at least one of the Hough intersections; the processor selects the one with the largest number of intersections from the Hough intersections as a target intersection; the coordinates of the target intersection in the second dimensional space are converted into a Hough line segment in the first dimensional space; other selected line segments are repeatedly obtained and other Hough line segments are generated; and the Hough antenna outline block is drawn according to the Hough line segments. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 11, wherein the step of selecting the target intersection point from the Hough intersection points with the largest number of intersection points includes: the processor sequentially adjusts a floating point precision level of the antenna conversion angle range, and counts the number of the Hough intersection points of each floating point precision level; and the processor selects the target intersection point from the Hough intersection points with the largest number of intersection points. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 11 further includes: after drawing the Hough antenna outline block, the processor determines whether the Hough antenna outline block is complete. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 1, wherein the step of selecting the antenna boundary of the Hough antenna outline block and the chip boundary of the Hough chip outline block includes: the antenna boundary is selected from a Hough line segment in a vertical direction or a Hough line segment in a horizontal direction of the Hough antenna outline block, and the chip boundary selects the Hough line segment in the selected direction from the Hough chip outline block according to the vertical direction or the horizontal direction. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 1, wherein the step of obtaining the connecting line segment passing through the first positioning area includes: the processor obtains a second positioning area of the input image; and the processor connects a first center point of the first positioning area and a second center point of the second positioning area to form the connecting line segment. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 1, wherein the step of obtaining the connecting line segment passing through the first positioning area includes: The connecting line segment vertically intersects a Hough line segment in a vertical direction of the Hough antenna outline block, and the connecting line segment passes through a first center point of the first positioning area. The processing method for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 1, wherein the step of obtaining the center point of the antenna block according to the Hough antenna outline block and the connecting line segment includes: the processor generates an antenna block center line according to two Hough line segments in a vertical direction of the Hough antenna outline block; and the intersection point of the antenna block center line and the connecting line segment is the center point of the antenna block. A processing system for detecting the position accuracy of the antenna and chip of an RFID tag includes: a storage device for storing an input image, a chip image program, an antenna image program, a Hough transformation program and a comparison result, wherein the input image at least includes a first positioning area; and a processor electrically connected to the storage device, wherein the processor executes the chip image program and the antenna image program respectively according to the input image, and generates a chip outline block and an antenna outline block respectively; the processor executes the Hough transformation program on the chip outline block and the antenna outline block respectively, and generates a Hough chip outline block and an antenna outline block respectively. The processor selects an antenna boundary of the Hough antenna outline block and a chip boundary of the Hough chip outline block; the processor obtains an offset angle according to the antenna boundary and the chip boundary; the processor obtains a connecting line segment passing through the first positioning area; the processor obtains an antenna block center point according to the Hough antenna outline block and the connecting line segment; the processor obtains a chip block center point according to the Hough chip outline block; the processor obtains an offset according to the antenna block center point and the chip block center point; the processor generates the comparison result according to the offset angle and the offset. A processing system for detecting the antenna and chip position accuracy of an RFID tag as described in claim 18, wherein the processor executes the chip imaging program, and the chip imaging program includes the following steps: the processor executes a grayscale program on the input image to generate a grayscale image; the processor executes a binarization program on the grayscale image to generate a chip binarization image; and the processor executes a chip contour recognition program on the chip binarization image to generate the chip contour block. A processing system for detecting the antenna and chip position accuracy of an RFID tag as described in claim 18, wherein the processor executes a chip outline recognition procedure including: the processor identifies multiple rectangular blocks in a chip binary image; the processor determines whether a target chip exists in the rectangular blocks according to a chip selection frame; if the target chip exists in the chip binary image, the processor removes the other rectangular blocks in the chip binary image and generates the chip outline block; and if the target chip does not exist in the chip binary image, the processor generates a judgment result. A processing system for detecting the position accuracy of the antenna and chip of an RFID tag as described in claim 18, wherein the processor executes the antenna image program, and the antenna image program includes the following steps: the processor executes a smoothing program on the input image to generate a smoothed image; the processor executes a binarization program on the smoothed image to generate an antenna binarization image; and the processor executes an antenna outline recognition program on the antenna binarization image to generate the antenna outline block. A processing system for detecting the position accuracy of the antenna and chip of an RFID tag as described in claim 18, wherein the processor executes the antenna image program, and the antenna image program includes the following steps: the processor executes a smoothing program on the input image to generate a smoothed image; the processor executes a grayscale program on the smoothed image to generate a grayscale image; the processor executes a binarization program on the grayscale image to generate an antenna binarization image; and the processor executes an antenna outline recognition program on the antenna binarization image to generate the antenna outline block. The processing system for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 18, wherein the processor executes an antenna outline recognition procedure including: the processor identifies multiple rectangular blocks in an antenna binary image; the processor determines whether there is a target antenna in the rectangular blocks according to an antenna selection frame; if the target antenna exists in the antenna binary image, the processor removes the other rectangular blocks in the antenna binary image and generates the antenna outline block; and if the target antenna does not exist in the antenna binary image, a judgment result is generated. The processing system for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 18, wherein the processor further includes before executing the step of executing the Hough transformation procedure on the chip outline block and the antenna outline block: the processor determines whether the antenna outline block contains the chip outline block; if the antenna outline block contains the chip outline block, the processor executes the Hough transformation procedure on the chip outline block and the antenna outline block; and if the antenna outline block does not contain the chip outline block, the processor generates a judgment result. A processing system for detecting the antenna and chip position accuracy of an RFID tag as described in claim 18, wherein the step of executing the Hough transform program on the chip outline block to generate the Hough chip outline block comprises: the processor obtains a selected line segment of the chip outline block in a first dimensional space, wherein the selected line segment has a plurality of chip boundary coordinates; the processor sets a chip transformation angle interval in a second dimensional space; the processor executes the Hough transform program according to the chip boundary coordinates and the chip transformation angle interval. , generating multiple Hough chip boundary curves in the second dimensional space; The processor obtains a Hough intersection according to the Hough chip boundary curves and selects at least one of the Hough intersections; the processor selects the one with the largest number of intersections from the Hough intersections as a target intersection; the processor converts the coordinates of the target intersection in the second dimensional space into a Hough line segment in the first dimensional space; repeatedly obtains other selected line segments and generates other Hough line segments; and the processor draws the Hough chip outline block according to the Hough line segments. A processing system for detecting the position accuracy of the antenna and chip of an RFID tag as described in claim 25, wherein the step of the processor selecting the target intersection point from the Hough intersections with the largest number of intersections includes: sequentially adjusting a floating point precision level of the chip conversion angle range, and counting the number of the Hough intersection points of each floating point precision level; and the processor selecting the target intersection point from the Hough intersections with the largest number of intersections. The processing system for detecting the antenna and chip position accuracy of the RFID tag as described in claim 25 further includes: determining whether the Hough chip outline block is complete after drawing the Hough chip outline block. The processing system for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 18, wherein the step of executing the Hough transform process on the processor to generate the Hough antenna outline block includes: the processor obtains a selected line segment of the antenna outline block in a first dimensional space, wherein the selected line segment has a plurality of antenna boundary coordinates; the processor sets an antenna transformation angle interval in a second dimensional space; the processor executes the Hough transform process according to the antenna boundary coordinates and the antenna transformation angle interval. The processor obtains a Hough intersection point according to the Hough antenna boundary curves and selects at least one of the Hough intersection points; the processor selects the one with the largest number of intersection points from the Hough intersection points as a target intersection point; the processor converts the coordinates of the target intersection point in the second dimensional space into a Hough line segment in the first dimensional space; repeatedly obtains other selected line segments and generates other Hough line segments; and the processor draws the Hough antenna outline block according to the Hough line segments. A processing system for detecting the position accuracy of the antenna and chip of an RFID tag as described in claim 28, wherein the step of the processor selecting the target intersection point from the Hough intersection points with the largest number of intersection points includes: sequentially adjusting a floating point precision level of the antenna conversion angle range, and counting the number of the Hough intersection points of each floating point precision level; and the processor selecting the target intersection point from the Hough intersection points with the largest number of intersection points. The processing system for detecting the position accuracy of the antenna and chip of the RFID tag as described in claim 28, wherein after the processor draws the Hough antenna outline block according to the Hough line segments, it further includes: Determining whether the Hough antenna outline block is complete. A processing system for detecting the position accuracy of the antenna and chip of an RFID tag as described in claim 18, wherein the processor obtains a second positioning area of the input image, and the processor connects a first center point of the first positioning area and a second center point of the second positioning area to form the connecting line segment. A processing system for detecting the position accuracy of the antenna and chip of an RFID tag as described in claim 18, wherein the processor intersects the connecting line segment perpendicularly with a Hough line segment in the vertical direction of the Hough antenna outline block, and the connecting line segment passes through a first center point of the first positioning area. A processing system for detecting the position accuracy of the antenna and chip of an RFID tag as described in claim 18, wherein the processor generates an antenna block centerline based on two Hough line segments in a vertical direction of the Hough antenna outline block; the processor uses the intersection point of the antenna block centerline and the connecting line segment as the center point of the antenna block. A processing system for detecting the position accuracy of the antenna and chip of an RFID tag as described in claim 18, wherein the processor selects the antenna boundary of the Hough antenna outline block and the chip boundary of the Hough chip outline block in the step of: the antenna boundary is selected from a Hough line segment in a vertical direction or a Hough line segment in a horizontal direction of the Hough antenna outline block, and the chip boundary selects the Hough line segment in the selected direction from the Hough chip outline block according to the vertical direction or the horizontal direction. The processing system for detecting the antenna and chip position accuracy of the RFID tag as described in claim 18 includes a camera unit electrically connected to the processor, and the camera unit captures the input image.

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