TWI852432B - Driver circuitry - Google Patents

Abstract

The present disclosure relates to circuitry comprising: digital circuitry configured to generate a digital output signal; and monitoring circuitry configured to monitor a supply voltage to the digital circuitry and to output a control signal for controlling operation of the digital circuitry, wherein the control signal is based on the supply voltage.

Description

Driver circuit

The following describes exemplary embodiments according to the present disclosure. Further exemplary embodiments and implementation methods will be apparent to those skilled in the art to which the present disclosure belongs. In addition, those skilled in the art to which the present disclosure belongs will recognize that they may use a variety of equivalent technologies to replace or combine the embodiments described below, and all such equivalent technologies should be deemed to be included in the present disclosure.

Example embodiments disclosed herein relate to analog and/or digital circuits for controlling or driving transducers and/or electronic circuits.

One way to control the speed of a transducer (e.g., a DC motor) is to adjust the supply voltage applied to the motor. Thus, when there is no load on the motor, if the supply voltage is higher, the motor speed is higher, and if the supply voltage is lower, the motor speed is lower. However, controlling the motor speed in this way limits the power and/or torque of the motor and causes the motor speed to be susceptible to the load on the motor. Also, since the motor speed varies depending on the supply voltage, any change in the supply voltage (e.g., a decrease in the amount of supply voltage rise, such as due to a discharge of a battery providing the supply voltage) will also affect the motor speed.

Another way to control the speed of a transducer (e.g., a DC motor) is to use a digital signal, such as a pulse width modulation (PWM) or pulse duration modulation (PDM) drive signal, to control the speed of the DC motor. The motor speed can be controlled by varying the duty cycle of the digital drive signal output by the motor's digital driver circuit, so that the motor speed is effectively controlled by the root mean square (RMS) value of the digital drive signal. In an open-loop motor control system with a varying supply voltage (e.g., where the supply voltage to a digital drive circuit is provided by a voltage source such as a battery), the motor speed is a function of both the duty cycle of the digital drive signal and the supply voltage, since the RMS value of the digital drive signal will vary as the supply voltage varies.

In another exemplary embodiment, a method of controlling the power efficiency and driver configuration of a transducer (e.g., an audio speaker system) is to adjust a supply voltage applied to an audio speaker driver. The audio speaker driver may drive the audio speaker using an analog drive signal and circuit, such as Class G amplifiers and/or Class H amplifiers, as known to those skilled in the art. In this analog configuration, larger input signals require larger supply voltages to avoid clipping of the output signal, but this configuration requires more energy. Smaller input signals require less supply voltage, saving energy and making the transducer and driver configuration more power efficient.

In addition, transducers such as motor drivers, audio drivers, and haptic drivers may require a sudden and potentially large amount of transient current from a battery (e.g., a lithium-ion battery). The individual and cumulative effects of such transient current demands may result in, for example, premature system brownouts due to the battery supply voltage level temporarily falling below a brownout threshold, and/or misleading the circuit and other components and/or systems in a host device including the circuit into believing that the battery has reached a brownout threshold when in fact it has not. In addition, a transient demand on one transducer may cause a transient voltage dip in the battery supply, affecting the output power supplied to other transducers. Furthermore, the cumulative power loss of such simultaneous current demands may cause undesirable overheating of the current and/or other components or systems in the host device containing the circuit.

In order to alleviate the problem of the motor speed being dependent on the supply voltage level and the duty cycle of the digital drive signal, a voltage regulator circuit, such as a DC-DC converter circuit, a low dropout (LDO) regulator circuit, etc., may be used to regulate the supply voltage of the digital drive circuit. However, the use of such an additional voltage regulator circuit increases the physical size, number of components, and cost of the system for controlling the DC motor, and may also reduce the power efficiency of the system due to the low efficiency of the additional voltage regulator circuit and the voltage headroom required by the voltage regulator circuit.

Digital drive signals can also be used to drive other transducers, such as light emitting diodes (LEDs), haptic transducers, resonant actuators, etc., and similar problems as described above will also occur when using digital and/or analog drive signals in these applications.

According to a first aspect, the present invention provides a circuit, comprising: a digital circuit configured to generate a digital output signal; and a monitoring circuit configured to monitor a supply voltage of the digital circuit and output a control signal for controlling the operation of the digital circuit, wherein the control signal is determined based on the supply voltage.

The digital circuit is operable to control a parameter of a digital output signal based on the control signal.

The digital circuit is operable to control a pulse width of a pulse of the digital output signal based on the control signal to maintain a given average voltage of the digital output signal in each time period to at least partially compensate for a change in the magnitude of the supply voltage.

The circuit may be configured to increase the pulse width of a pulse of the digital output signal to at least partially compensate for the reduction in magnitude of the supply voltage.

The circuit may be configured to reduce a pulse width of a pulse of the digital output signal to at least partially compensate for the increase in magnitude of the supply voltage.

The monitoring circuit may be configured to receive an input signal for the digital circuit and output a modified input signal to the digital circuit based on the control signal, and the digital circuit may be configured to generate the digital output signal based on the modified input signal.

The monitoring circuit may include: a waveform generator circuit configured to generate a voltage having an amplitude that varies with time based on a magnitude of the supply voltage; a comparator circuit configured to compare the voltage with a reference voltage and output a comparison signal when the voltage reaches the reference voltage; and a logic circuit configured to receive the input signal and the comparison signal and generate a modified input signal for the digital circuit based on the input signal and the comparison signal.

The waveform generator circuit can be configured so that the rate of increase of the voltage is inversely proportional to the magnitude of the supply voltage.

The waveform generator circuit can be configured to generate a ramp voltage.

The monitoring circuit may include: a capacitor; a voltage-to-current converter circuit configured to generate a first current based on the supply voltage; a current generator circuit configured to generate a constant current for charging the capacitor; and a current mirror circuit; and a current control transistor, wherein the current mirror circuit is configured to mirror the first current to a control terminal of the current control transistor so that the current control transistor controls a portion of the constant current separated from the capacitor.

The monitoring circuit may include: an analog-to-digital converter (ADC) circuit configured to generate a digital output signal based on the supply voltage; a timer circuit configured to: receive the input signal and the digital output signal; start timing a time period when a feature of the input signal is detected, wherein a length of the time period is determined based on the digital output signal; and output a timer output signal at the end of the time period; and a logic circuit configured to receive the input signal and the timer output signal, and generate a modified input signal for the PWM circuit based on the input signal and the timer output signal.

The timer circuit can be configured so that the length of the time period is inversely proportional to the magnitude of the supply voltage.

The characteristic of the input signal may be a rising edge of a pulse of the input signal.

The monitoring circuit may include: a voltage-controlled oscillator (VCO) circuit configured to generate an oscillating output signal having a frequency based on the supply voltage; a counter circuit configured to: receive the input signal and the oscillating output signal; start a count of the number of cycles of the oscillating signal when a feature of the input signal is detected; and output a counter output signal when the count reaches a count value representing a magnitude of the supply voltage; and a logic circuit configured to receive the input signal and the counter output signal, and generate a modified input signal for the PWM circuit based on the input signal and the counter output signal.

The VCO circuit may be configured such that the frequency of the oscillation output signal is inversely proportional to the magnitude of the supply voltage.

The characteristic of the input signal may be a rising edge of a pulse of the input signal.

The digital circuit may include a pulse width modulation (PWM) circuit configured to generate a PWM output signal.

According to a second aspect, the present invention provides an integrated circuit, comprising the circuit in the first aspect.

According to a third aspect, the present invention provides a system comprising the circuit in the first aspect and an output transducer configured to receive the digital output signal from the digital circuit.

The output transducer may include one or more of the following: a motor, a light emitting diode (LED) or LED array, a tactile actuator, a resonant actuator and/or a servo.

According to a fourth aspect, the present invention provides a device, comprising the circuit in the first aspect, wherein the device comprises a battery-powered device, a computer game controller, a virtual reality (VR) or augmented reality (AR) device, a pair of glasses, a mobile phone, a tablet or a laptop, an accessory device, an earmuff-type headset, an earphone, or a headset-microphone combination.

According to a fifth aspect, the present invention provides a monitoring circuit configured to receive a supply voltage applied to a digital circuit and an input signal for the digital circuit, and the monitoring circuit is configured to generate a modified input signal for the digital circuit based on the input signal and the supply voltage.

According to a sixth aspect, the present invention provides a digital driver circuit, comprising: a digital output circuit; and a monitoring circuit, wherein the monitoring circuit is configured to receive an input signal for the digital output circuit and a supply voltage applied to the digital output driver circuit, and based on the input signal and the supply voltage, generate a modified input signal for the digital output circuit.

According to a seventh aspect, the present invention provides a digital control circuit, comprising: a digital output driver circuit, configured to generate a digital signal based on an input signal; and a circuit, configured to apply a time shift to the digital signal, wherein the time shift is determined based on the magnitude of a supply voltage applied to the digital output driver circuit.

According to an eighth aspect, the present invention provides a circuit comprising: a digital signal modulator configured to output a modulated digital signal; and a circuit configured to monitor a supply voltage to the modulator and output a control signal for controlling the modulator, wherein the control signal is determined based on the supply voltage.

According to a ninth aspect, the present invention provides a digital signal modulator configured to output a modulated digital signal, comprising: A circuit configured to monitor a supply voltage to the modulator and output a control signal for controlling the modulator signal, wherein the control signal is determined based on the supply voltage.

According to a tenth aspect, the present invention provides a circuit for driving a load with a digital signal, wherein the circuit is configured to regulate, control or adjust the width of one or more digital pulses to compensate for changes in a supply voltage supplied to a digital modulator of the circuit to maintain a constant average voltage of the digital signal in each time period under a given load condition.

According to an eleventh aspect, the present invention provides a system comprising: a plurality of driver circuits, each driver circuit being configured to output a drive signal for driving a load, wherein the drive signal is determined based on an input signal; and a controller configured to control a parameter of one or more of the drive signals to at least partially compensate for a change in a component in the system.

The parameter of one or more of the driving signals may include a pulse width or a pulse amplitude of a digital driving signal output by one or more of the driver circuits.

The system may further include a power supply for providing a supply voltage to each of the driver circuits. The component variation in the system may include a variation of the supply voltage.

The power supply may include a battery, and the component change in the system may include a change in a parameter of the battery.

The parameter of the battery may include one or more of the following parameters: an output voltage of the battery; a charging state of the battery; a health state of the battery; and a temperature of the battery.

The system may further include a voltage regulator. The component variation in the system may include a variation in an output voltage of the voltage regulator.

The component variation in the system includes a variation of a parasitic element in the system.

The parasitic element may include a parasitic capacitor.

The component change in the system may include a temperature change of the component.

The system may include one or more temperature monitors for providing temperature information to the controller.

The component change in the system may include a parameter change of an input signal.

The system may include one or more voltage monitors for monitoring a battery output voltage and/or a regulator output voltage.

The system may include one or more impedance monitors for measuring or estimating the impedance of a battery.

The one or more impedance monitors may be configured to measure or estimate the impedance of the battery based on one or more characteristics of the battery.

The one or more characteristics of the battery may include one or more of the following characteristics: charge state, health state, temperature, parasitic elements, sense resistance and/or battery resistance.

The controller may be configured to estimate, calculate, or otherwise determine a predicted power requirement for each drive signal based on one or more parameters of the system.

The one or more parameters of the system may include: an amplitude level of the input signal on which the drive signal is based; a characteristic of a load driven by the drive signal; a transient gradient for estimating inrush current; a frequency; an average power; and/or a transducer efficiency.

The controller may be configured to control the parameter of the one or more of the drive signals based on the predicted power demand of the drive signals or a subset of the drive signals.

The controller may be configured to calculate, estimate or otherwise determine a total predicted power demand and output a signal indicating the total predicted power demand to a battery charger controller.

The battery charger controller may be configured to adjust a battery charging current based on the signal indicative of the total predicted power demand.

According to a twelfth aspect, the present invention provides a system comprising: a plurality of driver circuits, each driver circuit being configured to output a drive signal for driving a load; a power supply for providing a supply voltage to the driver circuits; and a controller configured to regulate, control or adjust a parameter of one or more of the drive signals based on a level of the supply voltage and an indication of an expected transient load in the system.

According to a thirteenth aspect, the present invention provides a system comprising: a power regulator or power controller associated with a transducer; one or more processors or controllers for controlling the power regulator or power controller; and a look-ahead controller configured to monitor control signals and/or data signals from the one or more processors or controllers in the system, the look-ahead controller being configured to adjust a transducer output power based on a supply voltage level and the monitored control signals and/or data signals.

The look-ahead controller may be configured to adjust the transducer output signal to: Reduce or avoid a temporary brownout condition; and/or Provide a constant output level; and/or Reduce cumulative output power requirements.

According to a fourteenth aspect, the present invention provides a circuit, comprising: one or more signal paths, each of which is configured to carry a signal for driving a load; a controller circuit, configured to receive a data from at least one of the signal paths, and output a control data to one or more of the signal paths to control one or more characteristics of the signal carried by one or more of the signal paths.

The data received by the controller circuit from at least one of the signal paths may include voltage data and/or thermal data and/or signal data.

The controller circuit may include a look-ahead controller circuit.

The one or more signal paths may include an analog signal path and/or a digital signal path.

Each of the signal paths may include a transducer driver circuit.

The controller circuit may be configured to output a control data to limit the signal power of the load associated with the one or more of the signal paths.

The control data may be configured to cause attenuation of a signal carried by one or more of the signal paths.

The controller circuit may be configured to output a control data to delay a signal in one or more of the signal paths.

According to a fifteenth aspect, the present invention provides a circuit comprising: A look-ahead controller configured to: Receive a signal data from a driver signal path; Estimate a power requirement of a load based on the signal data and/or a characteristic of a load coupled to the driver signal path; Predict a future supply voltage based at least in part on the estimated power requirement and a power supply parameter; and Adjust a parameter of a signal in one or more of the driver signal paths based on the predicted future supply voltage.

The power supply parameter may include one or more of the following parameters: A measurement of the current battery supply level; and A resistance-capacitance dynamic characteristic of the battery.

The resistance-capacitance dynamic characteristic of the battery can be determined based on a battery parameter, which includes one or more of the following parameters: a charging state; a health state; and a temperature.

According to a sixteenth aspect, the present invention provides a circuit that receives a voltage from a voltage supply for controlling one or more signal paths, the circuit comprising a controller configured to receive: At least a voltage data associated with the circuit; and/or At least a thermal data associated with the circuit; and/or A signal data from the one or more signal paths, wherein each of the signal paths comprises a separate transducer driver; The circuit is configured to output a control data to the one or more signal paths for controlling one or more characteristics of individual signals in the one or more individual signal paths, wherein the controller is a predictive controller, based on the one or more received data, before the individual signals of the one or more individual signal paths are output from their individual transducer drivers, to control one or more characteristics of the individual signals of the one or more individual signal paths to reduce or avoid at least an adverse voltage condition and/or an adverse thermal condition and/or an adverse signal condition associated with the circuit.

The adverse voltage condition may be a temporary brownout condition of the voltage supply.

The adverse thermal condition may be an undesirable heating condition of the circuit.

The adverse thermal condition may be an undesirable heating condition of other components in the host device that includes the circuit.

The voltage data may be obtained from a battery monitor and/or a voltage monitor.

The battery monitor may be configured to monitor a battery parameter.

The battery parameters may include one or more of the following parameters: the state of charge of the battery, the state of health of the battery, and/or parasitic elements of the battery (and/or associated with the battery).

The thermal data may be derived from one or more thermal monitors.

The signal data may be derived from one or more points distributed along the one or more signal paths.

The control data may control at least one signal parameter in a respective signal path. The at least one controlled signal parameter may be input to the controller.

The control data may control a gain of at least one signal in a respective signal path.

This circuit can provide a constant power output.

The controller may output a total predicted power demand signal.

The total predicted power demand signal may be input to a battery controller.

FIG. 1a is a simplified schematic diagram showing a circuit for driving a transducer with a digital signal (e.g., a PWM signal). The circuit (shown generally as 100a) includes a digital output driver circuit 110 coupled to a load 120. The load 120 may be, for example, a transducer such as a motor, an LED (or an LED array), a servo device, a tactile transducer, or a resonant actuator. Alternatively, the load 120 may be, for example, an electronic circuit such as an audio amplifier.

The digital output driver circuit 110 receives a supply voltage VBat from a power supply, which in this example is a battery 130, but it can also be equivalently a power supply, a power converter or a regulator, etc., wherein the output voltage of the power supply may vary due to a transient load generated by other components or systems in a host device including the circuit 100a.

The digital output driver circuit 110 in this example includes a first inverter and a second inverter connected in series, which are represented by 112 and 114 respectively. The first inverter 112 receives a digital input signal SIn at its input node 140 and outputs a digital inverted signal of SIn at its output node 145, that is, The second inverter 114 receives the digital inverted signal at its input node 145. , and outputs an inverted digital output signal DigitalOut at its output node 150. Therefore, the logical state or level of the digital output signal DigitalOut is the same as that of the digital input signal SIn.

FIG. 1b is a simplified schematic diagram showing a circuit for driving a transducer with an analog signal AnalogueOut, which in this exemplary embodiment is derived from a digital signal SIn. The circuit (generally shown as 100b) includes a mixed signal (i.e., analog and digital) output driver circuit 111 coupled to a load 120. The load 120 may be, for example, a transducer, such as an audio transducer, a speaker, a tactile transducer, or an ultrasonic transducer. Alternatively, the load 120 may be, for example, an electronic circuit, such as an audio amplifier.

The mixed signal output driver circuit 111 receives a supply voltage VBat from a power supply, which is the same as that described above with reference to FIG. 1a.

The mixed signal output driver circuit 111 in this example includes a digital-to-analog converter (DAC) 113, which receives a digital input signal SIn at its input node 140 and outputs an analog equivalent input signal AIn at its output node 146. The analog equivalent input signal AIn is input to a delay circuit 115 and a DC-DC converter 117 (e.g., a charge pump) on the signal path. In this example embodiment, the output of the delay circuit 115 is input to a pre-amplifier 119 on the signal path, and the output of the pre-amplifier 119 is input to an output driver or power amplifier 121 on the signal path. The output driver or power amplifier 121 receives a bipolar supply voltage from a DC-DC converter 117, which in turn receives its supply voltage from a battery 130. The bipolar voltages (V+ and V-) supplied to the output driver 121 are controlled based on a parameter (e.g., amplitude) of the analog equivalent input signal AIn, such that the voltage supplied to the output driver 121 is controlled as a function of a parameter of the analog equivalent input signal AIn. The output signal AnalogueOut output by the power amplifier 121 at an output node 151 is used to drive the load 120. The configuration and operation of such a mixed signal output driver circuit 111 are known to those skilled in the art to which the present disclosure pertains. Those skilled in the art will also recognize that, although the circuit shown in 100b includes a mixed signal (i.e., analog and digital) output driver circuit 111, DAC 113 may be part of some other circuit (not shown) such that output driver circuit 111 becomes an analog output driver circuit 111 that receives the analog equivalent input signal AIn as an input signal. In addition, delay circuit 115 may be located in the digital portion of the signal path rather than the analog portion of the signal path (as shown in FIG. 1b), upstream of DAC 113, and the DC-DC converter receives a digital preview signal rather than an analog preview signal.

In order to maintain a constant average voltage in each PWM period (and thereby maintain a constant output of the load 120, such as maintaining a constant motor speed when the load 120 is a DC motor, or maintaining a constant light intensity when the load 120 is an LED or an LED array), the PWM output driver circuit 110 generates a PWM output signal PWMOut having a constant duty cycle or mark-to-space ratio. This method is effective when the supply voltage VBay is maintained constant. However, if the supply voltage VBat changes, for example, due to the discharge of the battery 130 over time and/or due to other components, systems, transients or circuits in the host device drawing current from the battery 130, causing the supply voltage VBat to decrease, then the average voltage of the PWM output signal PWMOut in a PWM signal period will also decrease, as described below in FIG. 2 .

FIG. 2 shows example digital (e.g., PWM) pulses 210 to 250 output by the PWM output driver circuit 110 as the supply voltage VBat (shown as a dotted line in FIG. 2) decreases during a plurality of PWM periods P1 to P5. It should be noted that FIG. 2 is a highly simplified schematic diagram of the PWM pulses 210 to 250, which is drawn only for the convenience of explanation. A person skilled in the art of the present disclosure should be aware that in practical applications, the frequency of the PWM signal will be much higher than that shown in FIG. 2, such as on the order of several kilohertz (Hz) to several million Hz.

It is known to those skilled in the art that in the first PWM period P1, the average voltage (or equivalent average power) supplied by the PWM output driver circuit 110 to the load 120 is represented by the area of the pulse 210. Similarly, in each of the PWM periods P2 to P5, the average voltage supplied by the PWM output driver circuit 110 to the load 120 is represented by the areas of the pulses 220 to 250, respectively.

If the supply voltage VBat is constant, the average voltage supplied from the PWM output driver circuit 110 to the load 120 in each PWM period P1 to P5 will be the same, so the pulses 210 to 250 will all have the same area. However, in the example shown, the supply voltage VBat decreases over time, so although the width of each pulse 210 to 250 (i.e., the on-time in each PWM period) is the same, the voltage magnitudes of the pulses 210 to 250 are not all the same (i.e., the amplitude or height is not all the same), so the average voltage supplied to the load 120 in each PWM period is not constant. This situation causes instability in the output signal PWMOut of the drive load 120, which in turn causes, for example, instability in the motor speed when the load 120 is a DC motor, or instability in the light intensity when the load 120 is an LED or an LED array.

FIG. 3 is a schematic diagram showing a circuit for driving a load 120 with a digital (e.g., PWM) signal, wherein the digital signal is configured to regulate, control, or adjust a parameter of the digital signal, such as the width of one or more PWM pulses, to compensate for variations in the supply voltage input to the PWM modulator 310, so as to maintain a constant average voltage in each PWM period, and thereby maintain a constant output performance of the load.

This circuit (shown generally at 300 in FIG. 3 ) includes the same components as the circuit 100 in FIG. 1 a. These same components are denoted by the same reference numerals and will not be described again in detail.

The circuit 300 includes a PWM output driver circuit 310, whose structure and operation are the same as those of the PWM output driver circuit 110 in FIG. 1a, and thus will not be described in detail.

The circuit 300 further includes a monitoring circuit 320 configured to receive the supply voltage VBat and the input signal SIn, and output a modified input signal SIn' to the PWM output driver circuit 310. Therefore, the operation of the PWM output driver circuit 310 is controlled based on the modified input signal SIn', as described below.

The PWM output driver circuit 310 in the illustrated example is configured to receive the modified input signal SIn’ from the monitoring circuit 320, and output an output PWM signal PWMOut based on the modified input signal SIn’. Therefore, the modified input signal SIn’ can be regarded as a control signal, which is determined based on the supply voltage VBat and the input signal SIn, and is output by the monitoring circuit 320 for controlling the operation of the PWM output driver circuit 310. Therefore, the circuit 300 can control or adjust the pulse width of one or more pulses in the PWM output signal PWMOut in response to changes in the supply voltage VBat to maintain a desired average voltage (or equivalently average output power) in each PWM period to maintain a desired load condition (e.g., when the load 120 is a motor, maintain a desired motor speed).

Such an approach is illustrated in FIG. 4 , which shows example digital (eg, PWM) pulses 410 to 450 output by the PWM output driver circuit 310 as the supply voltage VBat (shown as a dashed line in FIG. 4 ) decreases during a plurality of PWM periods P1 to P5 .

Compared with the pulses 210 to 250 shown in the second figure, the widths (i.e., the durations) of the pulses 410 to 450 are different. On the contrary, the first pulse 410 of the first PWM period P1 is narrower (i.e., the duration is shorter) than the second pulse 420 of the second PWM period P2 and the third pulse 430 of the third PWM period P3. The fourth pulse 440 of the fourth PWM period P4 is slightly wider (i.e., the duration is slightly longer) than the second pulse 420 and the third pulse 430, and the fifth pulse 450 of the fifth PWM period P5 is also wider (i.e., the duration is longer) than the second pulse 420 and the third pulse 430. (It should be noted that the pulse widths in FIG. 4 are exaggerated for ease of illustration, so the illustrative pulses 410 to 450 shown in FIG. 4 do not necessarily have equal areas. However, as will be apparent below, each pulse 410 to 450 represents the same average voltage for each PWM period.)

Therefore, the PWM output driver circuit 310 controls or adjusts (relative to a preset pulse width) the width of the pulses 410 to 450 to compensate for variations in the supply voltage VBat so that the average voltage supplied to the load 120 in each PWM period P1 to P5 is the same to maintain the desired load condition (e.g., the desired motor speed when the load 120 is a motor). Therefore, for the first pulse 410, the pulse width is reduced compared to the second pulse 420 and the third pulse 430 to compensate for the increased amplitude (height) compared to the second pulse 420 and the third pulse 430, and the pulse width of the fifth pulse 450 is increased compared to the second pulse 420 and the third pulse 430 to compensate for the decreased amplitude (height) compared to the second pulse 420 and the third pulse 430. Therefore, the total area of each pulse 410 to 450 is the same.

FIG. 5 is a schematic diagram showing an example circuit for implementing the monitoring circuit 320. In the example shown in FIG. 5, the monitoring circuit (generally shown as 500) is configured to generate a modified input signal SIn' and output the modified input signal SIn' to a digital (e.g., PWM) output driver circuit 510 to control the operation of the digital output driver circuit 510.

The PWM digital output driver circuit 510 in FIG. 5 has the same structure and operation as the digital PWM output driver circuit 110 in FIG. 1a, so they will not be described in detail.

The monitoring circuit 500 includes a waveform (ramp) generator circuit 530 configured to receive a supply voltage VBat (e.g., from a battery 130) and an input signal SIn, and in this example, generate a rising ramp voltage VRamp, the rate of rise of which is determined based on the amplitude of the supply voltage VBat. The ramp voltage VRamp is output to a first non-inverting (+) input terminal of a comparator circuit 540. A second inverting (-) input terminal of the comparator circuit 540 receives a reference voltage or threshold voltage VRef from a suitable reference voltage source.

The output terminal of the comparator circuit 540 is coupled to the first input terminal of the logic circuit 550, and the logic circuit 550 may include one or more known flip-flops or logic gates. The second input terminal of the logic circuit 550 receives the input signal SIn. The output terminal of the logic circuit 550 is coupled to the input terminal of the PWM output driver circuit 510 to provide the modified input signal SIn' to the PWM output driver circuit 510 to control the operation of the PWM output driver circuit 510.

The operation of the monitoring circuit 500 will be described in detail below with reference to the timing diagrams of FIG. 6a and FIG. 6b.

In Figure 6a, the top trace 610a shows a single pulse of the input signal SIn, the second trace 620a shows the ramp voltage VRamp under the relatively low supply voltage VBat _low , the third trace 630a shows the corrected input signal SIn' under the relatively low supply voltage VBat _low , and the fourth trace 640a shows the PWM output signal PWMOut under the relatively low supply voltage VBat _low .

At time t0, when the rising edge of the pulse of the input signal SIn is detected, the ramp generator circuit 530 starts to generate a ramp voltage that rises from 0 volts (V). The rate of change ∆1 of the ramp voltage, i.e., the slope 622a, is determined based on the supply voltage, so that for a relatively high supply voltage VBat _high , the rising rate of the ramp voltage VRamp is slower than the rising rate of the relatively low supply voltage VBat _low , i.e., the rising rate of the ramp voltage VRamp is inversely proportional to the supply voltage VBat.

When the supply voltage is relatively low (i.e., VBat=VBat _low ), the ramp voltage VRamp reaches the reference voltage VRef at time t1. Between t0 and t1, the ramp voltage VRamp is less than the reference voltage VRef, so the output of the comparator circuit 540 is low. Therefore, the output of the logic circuit 550 is also low, so the corrected input signal SIn' is low. Therefore, the PWM output signal PWMOut is low. When the reference voltage VRef is reached (or shortly thereafter), the ramp voltage VRamp can be reset to 0V.

At time t1, the ramp voltage VRamp reaches the reference voltage VRef, so the output of the comparator circuit 540 becomes high, which in turn causes the output of the logic circuit 550 to become high, and the correction input signal SIn' also becomes high. Therefore, the PWM output signal PWMOut is equal to (or close to) VBat _low .

When the pulse of the input signal SIn ends (time t3), the output of the logic circuit 550 becomes low, SIn' becomes low, and PWMOut becomes low again.

In Figure 6b, the top trace 610b shows a single pulse of the input signal SIn, the second trace 620b shows the ramp voltage VRamp under the relatively high supply voltage VBat _high , the third trace 630b shows the corrected input signal SIn' under the relatively high supply voltage VBat _high , and the fourth trace 640b shows the PWM output signal PWMOut under the relatively high supply voltage VBat _high .

When the supply voltage is relatively high (i.e., VBat=VBat _high ), the ramp voltage VRamp reaches the reference voltage VRef at time t2 later than when the supply voltage is relatively low (i.e., VBat=VBat _low ), that is, the change rate ∆2 of the ramp voltage VRamp (i.e., the slope 622b) is less than the change rate when the supply voltage is relatively low. Between t0 and t2, the ramp voltage VRamp is less than the reference voltage VRef, so the output of the comparator circuit 540 is low. Therefore, the output of the logic circuit 550 is also low, so the corrected input signal SIn' is low. Therefore, the PWM output signal PWMOut is low.

At time t2, the ramp voltage VRamp reaches the reference voltage VRef, so the output of the comparator circuit 540 becomes high, which in turn causes the output of the logic circuit 550 to become high, and the correction input signal SIn' also becomes high. Therefore, the PWM output signal PWMOut is equal to (or close to) VBat _high . When reaching the reference voltage VRef (or soon after), the ramp voltage VRamp can be reset to 0V.

When the pulse of the input signal SIn ends (time t3), the output of the logic circuit 550 becomes a low level, SIn' also becomes a low level, and PWMOut becomes a low level again.

When the rising edge of the next pulse of the input signal SIn is detected, the ramp signal VRamp is 0V (or is reset to 0V if it has not been reset to 0V), and starts to rise again based on the size of the supply voltage VBat.

It is apparent from traces 630a, 630b, 640a and 640b that the monitoring circuit 500 compensates for the relatively low supply voltage VBat _low by increasing the pulse width (i.e., duration) in the PWM period of the output signal PWMOut so that the average voltage in each PWM period remains approximately constant even if the supply voltage decreases.

Similarly, the monitoring circuit 500 compensates for the relatively high supply voltage VBat _high by reducing the pulse width (ie, duration) of the output signal PWMOut in the PWM period so that the average voltage in each PWM period remains substantially constant even if the magnitude of the supply voltage increases.

Essentially, the monitoring circuit 500 implements a timer circuit that applies a time shift based on the magnitude of the supply voltage VBat to the PWM signal generated by the PWM output driver circuit 510. The time shift applied by the timer circuit compensates for changes in the magnitude of the supply voltage VBat by varying the length or duration of the PWM pulse.

Although the operation of the monitoring circuit 500 is described above as generating a ramp voltage VRamp, a person skilled in the art will appreciate that the waveform generator circuit 530 does not necessarily need to generate a linear ramp, but may generate some other waveform with an amplitude that varies with time based on the supply voltage VBat.

FIG7 is a schematic diagram showing an example circuit implementing a waveform generator 530 for use in the circuit 500 of FIG5. The circuit in this example includes a ramp generator circuit.

The ramp generator circuit (shown generally at 700 in FIG. 7 ) includes an amplifier circuit 710 having a first input terminal configured to receive a voltage Vin from a potential voltage divider comprised of a first resistor 712 and a second resistor 714 connected in series between a positive power supply voltage rail receiving a supply voltage VBat and a reference voltage supply rail GND coupled to ground or other suitable reference voltage. A second input terminal of the amplifier circuit receives a feedback signal from a feedback loop comprising a transistor 720 and a third resistor 722. Therefore, it is obvious to a person skilled in the art that the amplifier circuit 710 is configured to operate as a voltage-to-current converter to generate a current I1 flowing through the third resistor 722, where I1 is equal to Vin/R, where R is the resistance value of the third resistor 722.

The ramp generator circuit 700 further includes a current generator circuit 730 coupled in series with a second transistor 740 between the supply voltage rail and the reference voltage rail. A capacitor 750 is coupled in parallel with the transistor 740 between an output node 760 of the ramp generator circuit 700 and the reference voltage supply rail GND.

The current I1 is mirrored to a control terminal (eg, gate terminal) of the second transistor 740 through the current mirror transistors 770 , 780 , and 790 .

The second transistor 740 operates to control a portion of the constant current IConst to flow to the reference voltage supply rail GND. Therefore, based on the current I1, the second transistor 740 causes a portion of the current IConst that would originally flow to the capacitor 750 to flow out (or branch out), so that the portion of the current does not flow into the capacitor 750, wherein the current I1 is proportional to the supply voltage VBat. Therefore, when VBat rises, Vin rises, and the current I1 also rises. The rise of I1 is mirrored to the control terminal of the second transistor 740, causing the second transistor 740 to branch out a larger portion of the constant current IConst, so that the portion of the current does not flow into the capacitor 750, thereby reducing the rising rate (i.e., slope) of the ramp voltage VRamp at both ends of the capacitor 750. Conversely, when VBat decreases, Vin decreases, and the current I1 also decreases. The second transistor 740 divides a smaller portion of the constant current IConst so that the smaller portion of the current does not flow into the capacitor 750, thereby increasing the rising rate of the ramp voltage VRamp. Therefore, the rising rate of the ramp voltage VRamp is inversely proportional to the supply voltage VBat.

FIG8 is a schematic diagram showing another example circuit for implementing the monitoring circuit 320. In the example shown in FIG8, the monitoring circuit (generally represented by 800) is configured to generate a modified input signal SIn' and output the modified input signal SIn' to the PWM output driver circuit 810 to control the operation of the PWM output driver circuit 810.

The PWM output driver circuit 810 in FIG. 8 has the same structure and operation as the digital PWM output driver circuit 110 in FIG. 1a, so they will not be described in detail.

The monitoring circuit 800 includes a first resistor 822 and a second resistor 824, which are coupled in series between a positive power supply voltage rail receiving a supply voltage VBat and a reference supply voltage GND (or other suitable reference voltage source) to form a voltage divider. A node 826 is located between the first resistor 822 and the second resistor 824 and is coupled to an input terminal of an analog-to-digital converter (ADC) circuit 830. Therefore, the ADC circuit 830 receives an input voltage indicating the supply voltage VBat and outputs a digital signal VBat' representing the supply voltage VBat.

The output terminal of the ADC circuit 830 is coupled to the first input terminal of the timer circuit 840, so that the timer circuit receives the digital signal VBat'. The second input terminal of the timer circuit 840 receives the input signal SIn.

The output terminal of the timer circuit 840 is coupled to the first input terminal of the logic circuit 850. The second input terminal of the logic circuit receives the input signal SIn. The logic circuit 850 may include one or more known flip-flops or logic gates, etc., and is configured to receive the signal output by the timer circuit 840 and the input signal SIn, and generate a modified input signal SIn' to output to the PWM output driver circuit 810.

When the monitoring circuit 800 is in operation, the ADC circuit 830 outputs a digital signal VBat' indicating the magnitude of the supply voltage VBat to the timer circuit 840. When the rising edge of the pulse of the input signal SIn is detected, the timer circuit 840 starts to time a period of fixed time length. The fixed time length is determined based on the digital signal VBat' output by the ADC circuit 840, so that the fixed time length d of the period is inversely proportional to the magnitude of the supply voltage. At the end of the period (i.e., when the fixed time length ends), the timer circuit 840 outputs a signal to the logic circuit 850, so that an output pulse of the corrected input signal SIn' begins. The output pulse of the modified input signal SIn’ ends when the logic circuit 850 detects the falling edge of the pulse of the input signal SIn.

The operation of the monitoring circuit 800 will be described in detail below with reference to the timing diagrams of FIG. 9a and FIG. 9b.

In Figure 9a, the top trace 910a shows a single pulse of the input signal SIn, the second trace 920a shows the operation of the timer circuit 840 at a relatively low supply voltage VBat _low , the third trace 930a shows the modified input signal SIn' at a relatively low supply voltage VBat _low , and the fourth trace 940a shows the PWM output signal PWMOut at a relatively low supply voltage VBat _low .

At time t0, when the rising edge of the pulse of the input signal SIn is detected, the timer circuit 840 starts to count the time period. As mentioned above, the time period has a fixed time length d1, which is determined based on the value of the digital signal output by the ADC circuit 830, so that for a relatively low supply voltage VBat _low , the fixed time length d1 is shorter than the fixed time length d2 of a relatively high supply voltage VBat _high . Therefore, the fixed time length of the time period is inversely proportional to the magnitude of the supply voltage VBat.

When the supply voltage is relatively low (i.e., VBat=VBat _low ), the fixed time length d1 of the time period ends at time t1, at which time point the timer circuit 840 stops timing and provides a trigger signal to the logic circuit 850. Until the trigger signal is received by the logic circuit 850, the output of the logic circuit 850 is low, so the modified input signal SIn' is low. Therefore, the PWM output signal PWMOut is low.

At time t1, the fixed time length d1 of the time segment ends, and the timer circuit 840 outputs the trigger signal to the logic circuit 850, causing the output of the logic circuit 850 to become high, and the modified input signal SIn' also becomes high. Therefore, the PWM output signal PWMOut is equal to (or close to) VBat _low .

When the pulse of the input signal SIn ends (time t3), the output of the logic circuit 850 becomes a low level, SIn’ becomes a low level, and PWMOut becomes a low level again.

In Figure 9b, the top trace 910b shows a single pulse of the input signal SIn, the second trace 920b shows the operation of the timer circuit 840 under a relatively high supply voltage VBat _high , the third trace 930b shows the modified input signal SIn' under a relatively high supply voltage VBat _high , and the fourth trace 940b shows the PWM output signal PWMOut under a relatively high supply voltage VBat _high .

When the supply voltage is relatively high (i.e., VBat=VBat _high ), the fixed time length d2 of the time segment ends at time t2 later than when the supply voltage is relatively low (i.e., VBat=VBat _low ), at which time point the timer circuit 840 outputs a trigger signal to the logic circuit 850. Until this trigger signal is received, the output of the logic circuit 850 is low, so the modified input signal SIn' is low. Therefore, the PWM output signal PWMOut is low.

At time t2, the fixed time length d2 of the time segment ends, and the timer circuit 840 outputs the trigger signal to the logic circuit 850, causing the output of the logic circuit 850 to become high, and the modified input signal SIn' also becomes high. Therefore, the PWM output signal PWMOut is equal to (or close to) VBat _high .

When the pulse of the input signal SIn ends (time t3), the output of the logic circuit 850 becomes a low level, SIn' also becomes a low level, and PWMOut becomes a low level again.

When the rising edge of the next pulse of the input signal SIn is detected, the timer circuit 840 is reset and starts to count a new period of time, the fixed time length of which is determined based on the current supply voltage VBat.

It is apparent from traces 930a, 930b, 940a, and 940b that the monitoring circuit 800 compensates for the relatively low supply voltage VBat _low by increasing the pulse width (i.e., duration) in the PWM period of the output signal PWMOut so that the average voltage in each PWM period remains approximately constant even if the supply voltage decreases.

Similarly, the monitoring circuit 800 compensates for the relatively high supply voltage VBat _high by reducing the pulse width (ie, duration) of the output signal PWMOut in the PWM period so that the average voltage in each PWM period remains approximately constant even if the magnitude of the supply voltage increases.

Similarly, the monitoring circuit 800 essentially implements a timer circuit that applies a time shift based on the magnitude of the supply voltage VBat to the PWM signal generated by the PWM output driver circuit 810. The time shift applied by the timer circuit compensates for the magnitude changes of the supply voltage VBat by varying the length or duration of the PWM pulse.

FIG. 10 is a schematic diagram showing another exemplary circuit for implementing the monitoring circuit 320. In the example shown in FIG. 10, the monitoring circuit (generally represented by 1000) is configured to generate a modified input signal SIn' and output the modified input signal SIn' to the PWM output driver circuit 1010 to control the operation of the PWM output driver circuit 1010.

The PWM output driver circuit 1010 in FIG. 10 has the same structure and operation as the digital PWM output driver circuit 110 in FIG. 1a, so they will not be described in detail.

The monitoring circuit 1000 includes a voltage controlled oscillator (VCO) circuit 1030, which is configured to receive a supply voltage VBat and output an oscillation signal SOsc with a frequency fOsc, wherein fOsc varies with the magnitude of the supply voltage VBat. In this example, the frequency fOsc of the oscillation signal SOsc is inversely proportional to the magnitude of the supply voltage VBat, so that the fOsc when the supply voltage is relatively low (i.e., VBat=VBat _low ) is higher than the fOsc when the supply voltage is relatively high (i.e., VBat=VBat _high ).

The output terminal of the VCO circuit 1030 is coupled to the first input terminal of the counter circuit 1040. The second input terminal of the counter circuit 1040 receives the input signal SIn. The counter circuit 1040 is configured to start counting the cycles of the oscillation signal SOsc received at its first input terminal when the rising edge of the pulse of the input signal SIn is detected, and output a trigger signal to the logic circuit 1050 when the count value Cnt reaches the count value CntVBat representing the supply voltage VBat.

It should be noted that when fOsc is higher, the count value CntVBat representing the supply voltage VBat is reached faster than when fOsc is lower. Therefore, when the magnitude of the supply voltage VBat is smaller, the count value CntVBat representing the supply voltage VBat is reached faster.

The output terminal of the counter circuit 1040 is coupled to the first input terminal of the logic circuit 1050. The second input terminal of the logic circuit 1050 receives the input signal SIn. The logic circuit 1050 may include one or more known flip-flops or logic gates, etc., and is configured to receive the signal output by the counter circuit 1040 and the input signal SIn, and generate a modified input signal SIn' to output to the PWM output driver circuit 1010.

When the monitoring circuit 1000 operates, the VCO circuit 1030 outputs an oscillation signal SOsc, and the frequency fOsc of the oscillation signal SOsc is determined based on the size of the supply power VBat supplied to the counter circuit 1040, or indicates the size of the supply power VBat. When the rising edge of the pulse of the input signal SIn is detected, the counter circuit 1040 starts to count the number of oscillations of the oscillation signal SOsc until the count value CntVBat representing the supply voltage VBat is reached. At this time, the counter circuit 1040 outputs the trigger signal to the logic circuit 1050, so that an output pulse of the modified input signal SIn' starts. The output pulse of the modified input signal SIn’ ends when the logic circuit 1050 detects the falling edge of the pulse of the input signal SIn.

The operation of the monitoring circuit 1000 will be described in detail below with reference to the timing diagrams of FIG. 11a and FIG. 11b.

In Figure 11a, the top trace 1110a shows a single pulse of the input signal SIn, the second trace 1120a shows the count value Cnt at a relatively low supply voltage VBat _low , the third trace 1130a shows the corrected input signal SIn' at a relatively low supply voltage VBat _low , and the fourth trace 1140a shows the PWM output signal PWMOut at a relatively low supply voltage VBat _low .

At time t0, when the rising edge of the pulse of the input signal SIn is detected, the counter circuit 1040 starts counting the period of the oscillation signal SOsc output by the VCO circuit 1030. As mentioned above, the frequency fOsc of the oscillation signal SOsc is determined based on the magnitude of the supply voltage VBat, so that for a relatively low supply voltage VBat _low , the frequency fOsc is higher than the frequency under a relatively high supply voltage VBat _high .

When the supply voltage is relatively low (i.e., VBat=VBat _low ), the count value CntVBat representing the magnitude of the supply voltage VBat will be reached at time t1, at which time the counter circuit 1040 outputs a trigger signal to the logic circuit 1050. Until t1, the output of the logic circuit 1050 is low, so the corrected input signal SIn' is also low. Therefore, the PWM output signal PWMOut is low.

At time t1, the count value CntVBat representing the magnitude of the supply voltage VBat is reached, and the counter circuit 1040 outputs the trigger signal to the logic circuit 1050, causing the output of the logic circuit 1050 to become high, and the modified input signal SIn' also becomes high. Therefore, the PWM output signal PWMOut is equal to (or close to) VBat _low .

When the pulse of the input signal SIn ends (time t3), the output of the logic circuit 1050 becomes low, SIn' becomes low, and PWMOut becomes low again. When the pulse of the input signal SIn ends, the count value Cnt can be reset to 0 at an appropriate time point, such as when it reaches CntVBat (or soon thereafter).

In Figure 11b, the top trace 1110b shows a single pulse of the input signal SIn, the second trace 1120b shows the count value Cnt at a relatively high supply voltage VBat _high , the third trace 1130b shows the corrected input signal SIn' at a relatively high supply voltage VBat _high , and the fourth trace 1140b shows the PWM output signal PWMOut at a relatively high supply voltage VBat _high .

When the supply voltage is relatively high (i.e., VBat=VBat _high ), the count value CntVBat representing the magnitude of the supply voltage VBat will arrive at time t2 later than when the supply voltage is relatively low (i.e., VBat=VBat _low ), at which time the counter circuit 1040 outputs the trigger signal to the logic circuit 1050. Therefore, until t2, the output of the logic circuit 1050 is low, so the modified input signal SIn' is also low. Therefore, the PWM output signal PWMOut is low.

At time t2, the count value CntVBat representing the magnitude of the supply voltage VBat is reached, and the counter circuit 1040 outputs the trigger signal to the logic circuit 1050, causing the output of the logic circuit 1050 to become high, and the modified input signal SIn' also becomes high. Therefore, the PWM output signal PWMOut is equal to (or close to) VBat _high .

When the pulse of the input signal SIn ends (time t3), the output of the logic circuit 1050 becomes low, SIn' also becomes low, and PWMOut becomes low again. When the pulse of the input signal SIn ends, the count value Cnt can be reset to 0 at an appropriate time point, such as when it reaches CntVBat (or soon thereafter).

When the rising edge of the next pulse of the input signal SIn is detected, the counter circuit 1040 is reset (if it has not been reset yet) and starts counting the oscillation of the signal SOsc, the frequency fOsc of which is determined based on the magnitude of the supply voltage VBat at that time.

It is apparent from traces 1130a, 1130b, 1140a, and 1140b that the monitoring circuit 1000 compensates for the relatively low supply voltage VBat _low by increasing the pulse width (i.e., duration) in the PWM period of the output signal PWMOut so that the average voltage in each PWM period remains approximately constant even if the supply voltage decreases.

Similarly, the monitoring circuit 1000 compensates for the relatively high supply voltage VBat _high by reducing the pulse width (ie, duration) of the output signal PWMOut in the PWM period so that the average voltage in each PWM period remains approximately constant even if the magnitude of the supply voltage increases.

Similarly, the monitoring circuit 1000 essentially implements a timer circuit that applies a time shift based on the magnitude of the supply voltage VBat to the PWM signal generated by the PWM output driver circuit 1010. The time shift applied by the timer circuit compensates for the magnitude changes of the supply voltage VBat by varying the length or duration of the PWM pulse.

Circuit 300 may be incorporated into a host device, which may be a battery-powered device. For example, the host device may include a computer game controller, a virtual reality (VR) or augmented reality (AR) device, such as a head-mounted device or glasses, a mobile phone, a tablet or a laptop, or an auxiliary device, such as an over-ear headset, an earbud headset, or a headset-microphone combination.

FIG. 12 is a schematic diagram showing some of the components in such a host device. The host device (generally shown as 1200 in FIG. 12 ) includes a battery 1210 and a load 120, which may be, for example, an output transducer such as a motor, an LED or an LED array, a tactile transducer, a resonant actuator or a servo device, or may be an electronic circuit such as an amplifier circuit. The load 120 is controlled by the PWM output driver circuit 310 based on the modified input signal SIn′ output by the monitoring circuit 320, as described above with reference to FIGS. 3 to 11 .

The host device 1200 may further include one or more input transducers 1220 (and related driver circuits), and the input transducer 1220 may include, for example, a microphone, a joystick, one or more buttons, a switch, a force sensor, a touch sensor and/or a touch screen, and one or more output transducers 1230 (and related driver circuits), and the output transducer 1230 may include, for example, one or more tactile output transducers, one or more sound output transducers, such as speakers, and one or more image output transducers, such as a screen or display.

FIG. 13a is a variation of FIG. 1a and FIG. 1b, wherein there are multiple (N) digital and/or analog driver circuits 110-1 to 110-N, respectively coupled to individual loads 120-1 to 120-N. Each load 120-1 to 120-N may be, for example, a transducer, such as a motor, an LED (or an LED array), a servo device, a speaker, a tactile transducer, a resonant actuator, etc., or a combination of the above devices. Alternatively, one or more of the loads 120-1 to 120-N may also be, for example, an electronic circuit, such as an audio amplifier.

Each digital and/or analog output driver circuit 110-1 to 110-N receives a supply voltage VBat from a power supply, which in this example is a battery 130, but the power supply may also be equivalently a power supply or a power converter, a voltage regulator, etc., and its output voltage may vary due to temporary loads caused by other components or systems in the host device including the circuit 100-N. For simplicity, when referring to the digital output driver circuit 110-1 to 110-N, it also includes the analog output driver circuit 111-1 to 111-N (see Figure 1b), and any and all digital and/or analog PWM output driver circuits.

Each digital and/or analog output driver circuit 110-1 to 110-N includes the same or similar circuits as those shown in FIG. 1a and FIG. 1b, and each digital and/or analog output driver circuit 110-1 to 110-N receives a respective input signal SIn-1 to SIn-N to drive a respective load 120-1 to 120-N.

In order to maintain a constant average voltage in each PWM period of the individual PWM output signals PWMOut-1 to PWMOut-N, and thereby maintain a consistent output of each individual load 120-1 to 120-N (for example, when a load 120 is a DC motor, a consistent motor speed is maintained, or when a load 120 is an LED or an LED array, a consistent light intensity is maintained), each individual PWM output driver circuit 110-1 to 110-N generates an individual PWM output signal PWMOut-1 to PWMOut-N (or an analog output signal AnalogueOut-1 to AnalogueOut-N, such as AnalogueOut-2 in FIG. 13a, if the individual output driver circuit is an analog output driver circuit), each having an individual constant duty cycle (duty cycle) or mark-to-space ratio. This approach is effective when the supply voltage VBat is kept constant. However, if the supply voltage VBat changes, for example, due to the discharge of the battery 130 over time and/or due to other components, systems, transients or circuits in the host device drawing current from the battery 130, causing the supply voltage VBat to drop, then the average voltage of the individual PWM output signals PWMOut-1 to PWMOut-N in the individual PWM signal periods will also drop, as described below with reference to FIG. 14.

FIG. 13b is a variation of FIG. 13a, wherein a plurality (N) of digital output driver circuits 110-1 to 110-N are coupled to respective loads 120-1 to 120-N. Each load 120-1 to 120-N may be, for example, as described above with reference to FIG. 13a. Other related aspects between FIG. 13a and FIG. 13b are as described above with reference to FIG. 13a, and are known to those skilled in the art to which the present disclosure belongs.

FIG. 14 shows example digital pulses 210′ to 250′ when the supply voltage VBat decreases during a plurality of PWM periods P1′ to P5′, which are typically output by only one of the digital output driver circuits 110-1 to 110-N.

With respect to FIG. 14 , for the sake of clarity of explanation, only the PWM output driver circuit 110 - 1 will be described below, and a person skilled in the art to which the present disclosure pertains will recognize that the same principles also apply to any and all other output driver circuits 110 - 2 to 110 -N.

It should be noted that FIG. 14 is a highly simplified schematic diagram of PWM pulses 210' to 250' for illustrative purposes only. A person skilled in the art of the present disclosure will know that in practical applications, the frequency of the PWM signal will be much higher than that shown in FIG. 14, for example, on the order of several kilohertz (Hz) to several million Hz.

It is known to those skilled in the art that in the first PWM period P1', the average voltage (or equivalent average power) supplied by the PWM output driver circuit 110-1 to its load 120-1 is represented by the area of the pulse 210'. Similarly, in each of the PWM periods P2' to P5', the average voltage supplied by the PWM output driver circuit 110-1 to its load 120-1 is represented by the area of the pulses 220' to 250'.

If the supply voltage VBat is constant, the average voltage supplied by the PWM output driver circuit 110-1 to the load 120-1 will be the same in each of the PWM periods P1' to P5', so the pulses 210' to 250' will have the same area. However, in the illustrated example, the supply voltage VBat decreases over time, so although the width of each pulse 210' to 250' (i.e., the activation time in each PWM period) is the same, the pulses 210' to 250' do not all have the same voltage magnitude (i.e., the amplitude or height is not all the same), so the average voltage and power supplied to the load 120-1 in each PWM period are not constant. This situation causes the output signal PWMOut-1 driving the load 120-1 to be unstable, which in turn causes, for example, unstable motor speed when the load 120-1 is a DC motor, or unstable light intensity when the load 120-1 is an LED or an LED array.

As shown in FIG14 , there are two example transient events T1 and T2 that occur. These transients may occur due to over-current demands of any combination of loads 120-2 to 120-N and/or other components or systems in the host device in combination with the load demands of the PWM output driver circuit 110-1 and its load 120-1. The gray segments in the PWM "start" pulses 230' and 240' represent PWM "start" pulses from any combination of loads 120-2 to 120-N and/or other components or systems in the host device that coincide with the PWM "start" time periods 230' and 240' of the PWM output driver circuit 110-1 and its load 120-1, 230' _T and 240' _T , respectively. This coincidence of PWM "start" time periods illustrates how transients T1 and T2 occur when two or more PWM "start" pulses from any combination of loads 120-1 to 120-N and/or any combination of other components or systems in the host device completely or partially coincide, and exceed the current delivery capability of the supply voltage VBat. A person skilled in the art of the present disclosure will be aware that the situation caused in practical application will be far more complicated than that shown in FIG. 14.

As shown in Figure 14, due to the overlap of multiple PWM "start" pulses that exceed the current delivery capacity of the supply voltage VBat, an over-current demand is caused in the P3' PWM period, resulting in a transient T1, causing the supply voltage VBat to drop. However, this over-current demand is not enough to make the supply voltage VBat lower than the temporary low voltage (brownout) threshold V _BOT , and when the over-current demand ends, that is, when the multiple PWM "start" pulses end, the supply voltage VBat returns to its nominal level.

Similarly, due to the overlap of multiple PWM "start" pulses that exceed the current delivery capacity of the supply voltage VBat, an over-current demand is caused in the P4' PWM period, resulting in a transient state T2, causing the supply voltage VBat to drop. However, in this T2 state, the over-current demand is sufficient to cause the supply voltage VBat to drop below the temporary low-voltage threshold V _BOT before the over-current demand ends (i.e., when the multiple PWM "start" pulses end) and returns to its nominal level. However, when the supply voltage VBat is lower than the temporary low voltage threshold _VBOT , the PWM output driver circuits 110-1 to 110-N and/or other components or systems in the host device including the PWM output driver circuits 110-1 to 110-N may be triggered to power down and reset or shut down completely.

This overlap of the PWM "start" period, whether or not it causes a temporary low voltage condition to be triggered, may also cause device overheating problems, causing the PWM output driver circuit and/or other components or systems in the host device including the PWM output driver circuits 110-1 to 110-N to experience power outages, reset or complete shutdown.

Figure 15a is a block diagram representing hardware and/or firmware and/or software components used to monitor and control various features in the digital and/or analog output driver circuits 110-1 to 110-N (and/or 111-1 to 111-N), including their individual signal paths and/or related blocks, and/or other components or systems in a host device including the digital and/or analog output driver circuits 110-1 to 110-N (and/or 111-1 to 111-N) (not all of which are shown for clarity of explanation). For the sake of brevity and clarity, the following description will only focus on the digital output driver circuits 110 - 1 to 110 -N. However, a person skilled in the art will appreciate that the same or similar principles are also applicable to the analog output driver circuits 111 - 1 to 111 -N.

Each PWM output driver circuit 110 - 1 to 110 -N drives a respective load 120 - 1 to 120 -N (not shown) with a respective PWM output signal PWMOut- 1 to PWMOut-N. One or more parameters of one or more of the individual digital pulses of the PWM output signals, such as pulse width or pulse amplitude, can be regulated, controlled or adjusted, for example, by the predictive controller 1100, to compensate for "variations" in, for example, the supply voltage VBat and/or regulator supply and/or battery parameters, including but not limited to their charge state, health state, temperature, and/or parasitic elements (such as trace resistance R _trace , sense resistance R _sense , system resistance R _system ), and/or the temperature of hardware, firmware and/or other components or systems in a host device including at least the hardware and/or firmware and/or software shown in the block diagram of FIG. 15a.

The high level concept shown in FIG. 15a is to use information about when and where the transient load and/or its associated effects occur to compensate for the aforementioned "variation" and predictively adjust, control or adjust one or more parameters of one or more of the PWM pulses.

The predictive controller 1100 may be, for example, a state machine that predictively regulates, controls or adjusts one or more parameters of one or more of the PWM pulses PWMOut-1 to PWMOut-N to compensate for, for example, battery/regulator status, thermal information from one or more thermal monitors, and/or "changes" in any combination of signals SIn-1 to SIn-N and/or their individual signal parameters at any point in the signal path. In addition, the predictive controller 1100 may, for example, output a "total predicted power demand" or a similar signal based on one or more of its various inputs, which may be sent to a battery charger controller (not shown), or a portion of the battery charger controller, such as a battery charger state machine, so that the battery charger controller can dynamically stop or reduce the battery charging current to avoid over-temperature or over-current events.

Therefore, in terms of a high-level concept, the method shown in Figure 15a uses information about the system and/or transient load (and/or related information thereof), and the current supply voltage level, to control one or more parameters of the digital signal, such as the width of the PWM signal, to at least alleviate (or preferably prevent) a temporary brownout condition such as that which typically occurs at T2, and/or reduce peak thermal problems that may occur in the system, and/or provide a stable drive strength or provide a stable output power, i.e., a drive pulse area.

Typically, the host device includes one or more processors that control, for example, the transducer and associated power regulators and controllers, including battery charger controllers. Control signals and/or data signals from the one or more processors and/or controllers may also be detected by the controller 1100 before such signals are applied to the transducer output. Such a signal lookahead may also provide an opportunity to compensate for any reduction in the supply voltage VBat caused by the transducer or regulator to mitigate or avoid a temporary low voltage condition by reducing the transducer output power, or to provide a stable output level by adjusting the output level to the supply level. Additionally, this configuration reduces cumulative power requirements to reduce heating, especially power dissipation caused by on-chip current-resistors (I ² R), such as in transducer drivers or regulators.

The power prediction value of each transducer input signal PWMOut-X and/or Analogue-X (where X represents a number between 1 and N) can be determined based on one or more parameters, such as: the amplitude level of the individual input signals SIn-1 to SIn-N of the transducer input signal; known and optionally programmable load characteristics; complex properties, such as but not limited to transient gradients, such as for estimating inrush current; frequency; average power; and/or transducer efficiency.

The voltage supply information may include, for example, a voltage monitor to measure current battery and (if necessary) regulator supply levels; and/or an impedance monitor to measure or estimate the impedance of the battery based on some or all of the battery characteristics, such as charge state, health state, current temperature, parasitic elements (such as trace impedance of the battery printed circuit board (PCB) and/or connectors, current sense resistors, and/or battery resistance).

The predicted signal controller 1100 may consider the cumulative effect of the power prediction value (or a selectable subset of such power prediction values) at each transducer input, together with the current voltage supply level and the battery impedance prediction value, and predictively adjust, control or adjust the transducer signal (or adjust, control or adjust the transducer driver or regulator if necessary) before the transducer signal is applied to its transducer output to avoid premature battery short circuits and/or reduce peak heating problems and/or provide a stable transducer power output level (i.e., drive strength) in the event of supply voltage changes. One may choose to adjust all transducers, or only a subset of such transducers.

In addition, the prediction signal controller 1100 can also provide individual signal adjustment states to each individual power predictor so that the power predictors can dynamically compensate their estimates. The prediction controller 1100 can also consider the characteristics of the pre-adjusted but delayed individual transducer input signals S _{In-1_DEL} to S _{In-N_DEL} to ensure that a large amount of power demand has been delivered, or can match the delay of the individual power prediction value to its signal path delay.

Any signal conditioning applied may be applied directly to the signal, and/or to the transducer's DAC/driver (e.g., when used to modulate a PWM drive signal, similar to that described in U.S. Patent Application No. 63/059,504).

The long term measurement of the supply voltage VBat may be a short term estimate, or may be optionally filtered, delayed or averaged to account for effects such as decoupling capacitance. Transducer signal monitoring may include programmability of transducer characteristics such as peak output power, aging effects, etc. The estimate of VBat may include programmability such as incorporating decoupling capacitors that may provide short term charging needs before a battery charge is required, such a configuration being optimized without excessively attenuating the signal if not necessary. The predictive controller 1100 may also receive temperature information from one or more thermal monitors, which may be used in conjunction with the cumulative effect of the power predictions at each transducer input and the battery status to reduce the power consumption of the transducer driver or regulator. The temperature measurement(s) may be instantaneous measurements or average measurements over a programmable time period and may be considered in conjunction with a programmable hysteretic threshold.

Figure 15b is a simplified block diagram showing hardware and/or firmware and/or software components used to monitor and control characteristics of digital and/or analog output signals used to drive individual loads (not shown), including individual signal paths and/or related blocks of such components and/or other components or systems in a host device that includes digital and/or analog output driver circuits (not all of which are shown for clarity of explanation). FIG. 15b shows a circuit that receives voltage from a voltage supply (e.g., a battery) for controlling one or more signal paths, the circuit comprising a controller configured to receive voltage data and/or thermal data and/or signal data from the one or more signal paths, wherein each signal path comprises a respective transducer driver. The controller is also configured to output control data to one or more of the signal paths to control one or more characteristics of the respective signals in the one or more signal paths. The controller is preferably a predictive controller, i.e., a lookahead controller, which controls one or more characteristics of the received voltage data and/or thermal data and/or signal data before the individual signals in the one or more individual signal paths are output from their individual transducer drivers to reduce or avoid at least adverse voltage conditions and/or thermal conditions and/or signal conditions associated with the circuit.

FIG. 16 shows an example transducer event (e.g., haptic output) that requires high dynamic power and may cause the battery power supply to drop or dip. Based on one or more anticipated signal and/or load characteristics, estimating the signal power of any and each transducer, and measuring the current battery supply level and supply decoupling capacitor, and/or using the battery's resistor-capacitor (RC) dynamic characteristics (based on some or all of the battery parameters, such as state of charge, health, and temperature, etc.), the future supply voltage VBat _F may be predicted. Information about a predicted value of a future supply voltage VBat _F may be used to limit the signal power at the output transducer by, for example, attenuating the signal level before the signal is applied to its respective load, adjusting one or more parameters of the signal, for example to avoid temporary low voltage conditions and/or compensate for temporary conditions of the power supply, thereby providing a stable output power level, and/or reducing heating on the chip or in the system.

Referring to FIG. 17 , if the transducer output signals PWMOut-X and/or AnalogueOut-X have sufficient look-ahead, transient events may be avoided altogether by skew- ing individual transducer output signals PWMOut-X and/or AnalogueOut-X. In the case where the transducer output signal may be additionally conditioned (i.e., by adding an additional delay to the signal so that the signal is further delayed for a short period of time) without any (or any perceptible) impact to the user, if the additional delayed signal coincides with one or more other transducer outputs that are in a preferred low power state, there is a chance that the additional delayed signal may be output without the need for signal conditioning, control or adjustment. This signal delay or skewing is preferably done before the signal is applied to the transducer, rather than while the signal is being applied to the transducer. If the signal is skewed or delayed, then the skew/delay characterization must be used in the ongoing power prediction. In the example shown in FIG. 17 , since the transducer associated with the input signal A _IN is in a preferred low power state, the additional delayed signal S _{IN_DEL+} is used instead of the transducer input signal S _{IN_DEL} .

As is apparent from the foregoing description, the circuit disclosed herein provides a mechanism for dynamically compensating for changes in the supply voltage applied to the digital output driver circuit, so that the average voltage (or equivalent average power) supplied to the load (e.g., a transducer or an electronic circuit) driven by the digital output driver circuit in each time period is maintained approximately constant for use in the operating state required by the load, thereby maintaining a stable load output. The circuits of the present disclosure are capable of compensating for both temporary variations in available supply voltage (which may be caused by current being drawn from the power supply by other components or subsystems in the host device that includes the digital output driver circuit) and long-term variations in available supply voltage (which may be caused by discharge of the battery over time).

Each embodiment may be implemented as an integrated circuit (e.g., an integrated circuit (e.g., a monolithic integrated circuit) or multiple integrated circuits (e.g., multiple monolithic integrated circuits), each of which implements a portion of the aforementioned circuit or system), which may be a codec or an audio digital signal processor (audio DSP) in some examples. Each embodiment may be incorporated into an electronic device, which may be, for example, a portable device and/or a device that can operate on battery power. The device may be a communication device, such as a mobile phone or a smartphone. The device may be a computing device, such as a laptop or a tablet computing device. The device may be a wearable device, such as a smartwatch. The device may be a device with voice control or activation functions, such as a smart speaker. In some examples, the device may be an accessory device used in conjunction with other products, such as a headset, headphones, earphones, earbuds, etc.

It will be appreciated by those skilled in the art to which the present disclosure pertains that some aspects of the apparatus and methods described above, such as the discovery and configuration methods, may be implemented by processor control code, such as that stored on a non-volatile carrier medium such as a magnetic disk, an optical disk (CD-ROM or DVD-ROM), a programmable memory (such as a read-only memory (firmware)), or stored on a data carrier (such as an optical or electrical signal carrier). In various applications, each embodiment may be implemented on a digital signal processor (DSP), an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). Thus, the processor control code may include known program code or microcode, or, for example, code for setting or controlling an ASIC or FPGA. The processor control code may also include code for dynamically configuring reconfigurable devices (e.g., reprogrammable logic gate arrays). Similarly, the processor control code may include code for a hardware description language (e.g., Verilog ^TM or Very High Speed Integrated Circuit Hardware Description Language (VHDL)). A person skilled in the art to which the present disclosure pertains will appreciate that the processor control code may be distributed over a plurality of coupled and mutually communicating components. Where appropriate, embodiments may also operate as code implementations on field (re)programmable analog arrays or similar devices to configure analog hardware.

It should be noted that the foregoing embodiments are illustrative rather than restrictive descriptions of the embodiments, and that a person skilled in the art to which the present disclosure pertains may design a variety of alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude components or steps not listed in the claims, "one" or "an" does not exclude plural forms, and a single feature or other unit may implement the functions of several units described in the claims; and the word "circuit" is intended to include the use of hardware, firmware and/or software, including combinations of hardware, firmware and/or software. Any reference number or mark in the claims should not be construed as limiting the scope of the claims.

100a: Circuit 110: Digital output driver circuit 112: First inverter 114: Second inverter 120: Load 130: Battery 140: Input node 145: Node 150: Output node VBat: Supply voltage SIn: Digital input signal : Digital inverted signal DigitalOut: Digital output signal 100b: Circuit 111: Mixed signal output driver circuit 113: Digital-to-analog converter (DAC) 115: Delay circuit 117: DC-to-DC converter 119: Preamplifier 121: Output driver (power amplifier) 146: Output node 151: Output node AIn: Analog equivalent input signal AnalogueOut: Analog signal 210, 220, 230, 240, 250: Digital pulse P1, P2, P3, P4, P5: PWM time segment 300: Circuit 310: PWM modulator 320: Monitoring circuit SIn': Corrected input signal PWMOut: PWM output signal 410, 420, 430, 440, 450: Digital pulse 500: Monitoring circuit 510: Digital output driver circuit 530: Waveform (ramp) generator circuit 540: Comparator circuit 550: Logic circuit VRamp: Ramp voltage VRef: Reference voltage GND: Reference voltage supply track 610a, 620a, 630a, 640a: Track 622a: Slope ∆1: Rate of change VBat _low : Supply voltage t0, t1, t2, t3: Time 610b, 620b, 630b, 640b: Track 622b: Slope ∆2: Rate of change VBat _high : Supply voltage 700: Ramp generator circuit 710: Amplifier circuit 712: First resistor 714: Second resistor 720: Transistor 722: Third resistor 730: Current generator circuit 740: Second transistor 750: Capacitor 760: Output node 770, 780, 790: Current mirror transistor Vin: Voltage I1: Current IConst: Constant current 800: Monitoring circuit 810: PWM output driver circuit 822: First resistor 824: Second resistor 826: Node 830: Analog-to-digital converter (ADC) circuit 840: Timer circuit 850: Logic circuit VBat': digital signal 910a, 920a, 930a, 940a: trace d1: fixed time length 910b, 920b, 930b, 940b: trace d2: fixed time length 1000: monitoring circuit 1010: PWM output driver circuit 1030: voltage-controlled oscillator (VCO) circuit 1040: counter circuit 1050: logic circuit SOsc: oscillation signal Cnt: count value 1110a, 1120a, 1130a, 1140a: trace CntVBat: count value 1110b, 1120b, 1130b, 1140b: Track 1200: Host device 1210: Battery 1220: Input transducer 1230: Output transducer 100-N: Circuit 110-1, 110-N: Digital and/or analog driver circuit (PWM output driver circuit) 111-2: Analog output driver circuit 120-1, 120-2, 120-N: Load SIn-1, SIn-2, SIn-N: Input signal PWMOut-1, PWMOut-N: PWM output signal AnalogueOut-2: Analogue output signal 210', 220', 230', 240', 250': Digital pulse P1', P2', P3', P4', P5': PWM period 230' _T , 240' _T : PWM "start" pulse V _BOT : temporary low voltage threshold T1, T2: transient event 1100: predictive controller S _{In-1_DEL} , S _{In-N_DEL} : transducer input signal PWMOut-X, AnalogueOut-X: transducer input signal transducer input signal S _{IN_DEL+} : additional delay signal

The following description of the various embodiments of the present invention is for illustrative purposes only and refers to the accompanying drawings, wherein: Figure 1a is a schematic diagram showing a circuit for driving a transducer with a digital signal; Figure 1b is a schematic diagram showing a circuit for driving a transducer with an analog signal; Figure 2 is a graph showing the digital signal output by the circuit in Figure 1a as it changes over time; Figure 3 is a schematic diagram showing an example circuit for driving a transducer with a digital signal according to the present disclosure; Figure 4 is a graph showing the digital signal output by the circuit in Figure 3 as it changes over time; Figure 5 is a schematic diagram showing an example monitoring circuit for use in the circuit in Figure 3; Figures 6a and 6b are timing diagrams showing the operation of the circuit in Figure 5; Figure 7 is a schematic diagram showing an example ramp voltage generator circuit; Figure 8 is a schematic diagram showing another example monitoring circuit; Figures 9a and 9b are timing diagrams showing the operation of the circuit in Figure 8; Figure 10 is a schematic diagram showing another example monitoring circuit; Figures 11a and 11b are timing diagrams showing the operation of the circuit in Figure 10; Figure 12 is a schematic diagram showing a host device including the circuit in Figure 3; Figure 13a is a schematic diagram showing a circuit for driving multiple transducers with multiple individual digital signals; FIG. 13b is a schematic diagram showing a circuit for driving multiple transducers with multiple individual digital signals; FIG. 14 is a graph showing the digital signal output of the circuit in FIG. 13a or FIG. 13b as a function of time; FIG. 15a is a schematic block diagram showing monitoring elements and control elements; FIG. 15b is a simplified schematic block diagram showing monitoring elements and control elements; FIG. 16 shows illustrative waveforms showing transducer events under high dynamic load; and FIG. 17 shows the delay of the transducer signal.

120: Load

130:Battery

300: Circuit

310:PWM modulator

320: Monitoring circuit

VBat: supply voltage

SIn: digital input signal

SIn’: Corrected input signal

PWMOut: PWM output signal

Claims (20)

A driver circuit is used to output a drive signal to a load, the driver circuit comprising: a digital circuit configured to generate a digital output signal for driving the load; and a monitoring circuit configured to monitor a supply voltage of the digital circuit and output a control signal for controlling the operation of the digital circuit, wherein the control signal is determined based on the supply voltage, wherein the monitoring circuit is configured to receive an input signal for the digital circuit and output a modified input signal to the digital circuit based on the control signal, and wherein the digital circuit is configured to generate the digital output signal based on the modified input signal. A driver circuit as claimed in claim 1, wherein the digital circuit operates to control a parameter of a digital output signal based on the control signal. A driver circuit as claimed in claim 2, wherein the digital circuit operates to control a pulse width of a pulse of the digital output signal based on the control signal to maintain a given average voltage of the digital output signal in each time period to at least partially compensate for a change in the magnitude of the supply voltage. A driver circuit as claimed in claim 3, wherein the circuit is configured to increase the pulse width of the pulse of the digital output signal to at least partially compensate for the reduction in the magnitude of the supply voltage. A driver circuit as claimed in claim 3, wherein the circuit is configured to reduce the pulse width of the pulse of the digital output signal to at least partially compensate for the increase in the magnitude of the supply voltage. A driver circuit as claimed in claim 1, wherein the monitoring circuit comprises: a waveform generator circuit configured to generate a voltage having an amplitude that varies with time based on a magnitude of the supply voltage; a comparator circuit configured to compare the voltage with a reference voltage and output a comparison signal when the voltage reaches the reference voltage; and a logic circuit configured to receive the input signal and the comparison signal and generate a modified input signal for the digital circuit based on the input signal and the comparison signal. A driver circuit as claimed in claim 6, wherein the waveform generator circuit is configured to cause a rate of increase of the voltage to be inversely proportional to the magnitude of the supply voltage. A driver circuit as claimed in claim 6, wherein the waveform generator circuit is configured to generate a ramp voltage. A driver circuit as claimed in claim 6, wherein the monitoring circuit comprises: a capacitor; a voltage-current converter circuit configured to generate a first current based on the supply voltage; a current generator circuit configured to generate a constant current for charging the capacitor; and a current mirror circuit; and a current control transistor, wherein the current mirror circuit is configured to mirror the first current to a control terminal of the current control transistor so that the current control transistor controls a portion of the constant current separated from the capacitor. A driver circuit as claimed in claim 1, wherein the monitoring circuit comprises: an analog-to-digital converter (ADC) circuit configured to generate a digital output signal based on the supply voltage; a timer circuit configured to: receive the input signal and the digital output signal; start timing a time period when a feature of the input signal is detected, wherein a length of the time period is determined based on the digital output signal; and output a timer output signal at the end of the time period; and a logic circuit configured to receive the input signal and the timer output signal, and generate a modified input signal for the PWM circuit based on the input signal and the timer output signal. A driver circuit as claimed in claim 10, wherein the timer circuit is configured so that the length of the time period is inversely proportional to the magnitude of the supply voltage. A driver circuit as claimed in claim 10, wherein the characteristic of the input signal is a rising edge of a pulse of the input signal. A driver circuit as claimed in claim 6, wherein the monitoring circuit comprises: a voltage-controlled oscillator (VCO) circuit configured to generate an oscillation output signal having a frequency based on the supply voltage; a counter circuit configured to: receive the input signal and the oscillation output signal; start a count of the number of cycles of the oscillation signal when a feature of the input signal is detected; and output a counter output signal when the count reaches a count value representing a magnitude of the supply voltage; and a logic circuit configured to receive the input signal and the counter output signal, and generate a modified input signal for the PWM circuit based on the input signal and the counter output signal. A driver circuit as claimed in claim 13, wherein the VCO circuit is configured to make the frequency of the oscillating output signal inversely proportional to the magnitude of the supply voltage. A driver circuit as claimed in claim 13, wherein the characteristic of the input signal is a rising edge of a pulse of the input signal. A driver circuit as claimed in claim 1, wherein the digital circuit includes a pulse width modulation (PWM) circuit configured to generate a PWM output signal. An integrated circuit, including the driver circuit of claim 1 above. A driver system includes the driver circuit of claim 1 and an output transducer configured to receive the digital output signal from the digital circuit. A drive system as claimed in claim 18, wherein the output transducer comprises one or more of the following: a motor, a light emitting diode (LED) or an LED array, a tactile actuator, a resonant actuator and/or a servo device. An electronic device, comprising the driver circuit of claim 1, wherein the electronic device comprises a battery-powered device, a computer game controller, a virtual reality (VR) or augmented reality (AR) device, a pair of glasses, a mobile phone, a tablet or laptop computer, an auxiliary device, an earmuff headset, an earbud headset, or an earphone-microphone combination.

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