TWI856632B - Semiconductor stack, semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present disclosure provides a semiconductor stack, a semiconductor device and a method for manufacturing the same. The semiconductor device includes a first semiconductor layer and a light-emitting structure. The first semiconductor layer includes a first III-V semiconductor material, a first dopant and a second dopant. The light-emitting structure is on the first semiconductor layer and includes an active structure. In the first semiconductor layer, a concentration of the second dopant is higher than a concentration of the first dopant. The first dopant is carbon, and the second dopant is hydrogen.

Description

Semiconductor stack, semiconductor element and manufacturing method thereof

The present disclosure relates to a semiconductor device, and more particularly to a light-emitting device comprising a semiconductor stack.

With the rapid development of technology, semiconductor components play a very important role in the fields of information transmission and energy conversion, and the research and development of related materials is also ongoing. For example, III-V semiconductor materials containing group III and group V elements can be applied to various optoelectronic components such as light emitting diodes (LEDs), laser diodes (LDs), solar cells, etc., and can also be applied to lighting, medical, display, communication, sensing, power supply systems and other fields. LED components are suitable for solid-state lighting sources and have the advantages of low power consumption and long life. Therefore, they have gradually replaced traditional light sources and are widely used in traffic signs, backlight modules, various lighting and medical equipment, etc.

The present invention provides a semiconductor element, which includes a first semiconductor layer, a light-emitting structure, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer includes a first III-V semiconductor material. The light-emitting structure is located on the first semiconductor layer and includes an active structure. The second semiconductor layer is located below the first semiconductor layer and includes a second III-V semiconductor material. The third semiconductor layer is located between the first semiconductor layer and the light-emitting structure and includes a third III-V semiconductor material.

The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer include a first dopant and a second dopant. The concentration of the first dopant in the first semiconductor layer is greater than the concentration of the first dopant in the second semiconductor layer. The concentration of the first dopant in the first semiconductor layer is greater than the concentration of the first dopant in the third semiconductor layer. The concentration of the second dopant in the first semiconductor layer is lower than the concentration of the second dopant in the second semiconductor layer. The concentration of the second dopant in the first semiconductor layer is lower than the concentration of the second dopant in the third semiconductor layer.

The present invention also provides a semiconductor component packaging structure, which includes a carrier, a semiconductor component and a packaging material. The semiconductor component is located on the carrier. The packaging material covers the semiconductor component.

10: Semiconductor stacking

20, 20’, 30, 40, 60: semiconductor components

61:Packaging substrate

62:Through hole

63: Carrier

63a: Part 1

63b: Part 2

65:Joining line

66: Contact structure

66a, 66b: Contact pads

68: Packaging materials

100, 300, 400, 500: first semiconductor layer

102, 402, 502: Second semiconductor layer

204, 304, 404, 504: third semiconductor layer

206, 306, 406: Luminous structure

208, 308, 408: Fourth semiconductor layer

210, 310, 410: Active structures

212, 312, 412: Fifth semiconductor layer

414: Window layer

416: Contact layer

600:Packaging structure

318, 418: first electrode

320, 420: Second electrode

S510, S520, S530, S540: Steps

C ₁ : First concentration

C ₂ : Second concentration

C ₃ : Second concentration

C _L1 , C _L2 , C _Li , C _M1 , C _M2 , C _Mi : concentration

Figure 1 is a schematic diagram of the structure of a semiconductor stack according to an embodiment of the present disclosure.

Figure 2A is a schematic diagram of a partial structure of a semiconductor device in an embodiment of the present disclosure.

Figure 2B is a schematic diagram of a partial structure of a semiconductor device in an embodiment of the present disclosure.

Figure 3 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present disclosure.

Figure 4 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present disclosure.

Figures 5A to 5D are schematic diagrams of a method for manufacturing a semiconductor stack according to an embodiment of the present disclosure.

Figure 5E is a graph showing the relationship between the concentration and depth of an element in a partial range of a semiconductor device of an embodiment of the present disclosure.

Figure 5F is a partial enlarged schematic diagram of the concentration curve of carbon (C) in Figure 5E.

Figure 6 is a schematic diagram of the packaging structure of a semiconductor device in an embodiment of the present disclosure.

The following embodiments will be accompanied by drawings to illustrate the concept of the present invention. In the drawings or descriptions, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shapes or sizes of the components in the drawings are only examples and are not limited thereto. It should be noted that the components not shown or described in the drawings may be in a form known to those skilled in the art.

The general formula InGaAsP represents In _x7 Ga _1-x7 As _1-y2 P _y2 , where 0<x1<1, 0<y1<1; AlGaInAs represents (Al _y2 Ga _(1-y2) ) _1-x2 In _x2 As, where 0<x2<1, 0<y2<1; the general formula AlGaInP represents (Al _y3 Ga _(1-y3) ) _1-x3 In _x3 P, where 0<x3<1, 0<y3<1; the general formula InGaAs represents In _x4 Ga _1-x4 As, where 0<x4<1; the composition of each layer and the additives and dopants included in the semiconductor device disclosed in the present invention can be analyzed by any suitable method, such as secondary ion mass spectrometry (secondary ion mass spectrometer). The thickness of each layer can be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM). In addition, each dopant mentioned in the present disclosure can be intentionally added or unintentionally added. Intentional addition is, for example, by in-situ doping during epitaxial growth and/or by implanting P-type or N-type dopants after epitaxial growth. Unintentional addition is, for example, caused by process design.

Those with ordinary knowledge in the art should understand that other components may be added on the basis of the embodiments described below. For example, unless otherwise specified, the description of "forming a second layer on a first layer" may include an embodiment in which the first layer and the second layer are in direct contact, and may also include an embodiment in which the first layer and the second layer have other layers between them and are not in direct contact with each other. In addition, the upper and lower relationships of the layers may change as the structure or element is operated or used in different directions. In addition, in the present disclosure, the description of a layer "substantially composed of material X" means that the main component of the layer is material X, but does not exclude the inclusion of dopants or unavoidable impurities.

FIG. 1 is a schematic diagram of the structure of a semiconductor stack 10 of an embodiment of the present disclosure. The semiconductor stack 10 includes a first semiconductor layer 100 and a second semiconductor layer 102. The second semiconductor layer 102 is adjacent to the first semiconductor layer 100. In this embodiment, a surface 100a of the first semiconductor layer 100 is in direct contact with a surface 102a of the second semiconductor layer 102. There is no other structure (such as a buffer layer, etc.) between the first semiconductor layer 100 and the second semiconductor layer 102.

In this embodiment, the first semiconductor layer 100 includes a first III-V semiconductor material. The first III-V semiconductor material is a material composed of group III and group V elements in the periodic table of chemical elements. The group III element may be gallium (Ga) or indium (In). The group V element may be arsenic (As) or phosphorus (P), and preferably does not include nitrogen (N). In one embodiment, the first semiconductor layer 100 is substantially composed of the first III-V semiconductor material, for example, substantially composed of a binary III-V semiconductor material. In one embodiment, the first semiconductor layer 100 is substantially composed of InP. The first semiconductor layer 100 may include a dopant. In one embodiment, the first semiconductor layer 100 includes a first dopant and a second dopant. In this embodiment, the concentration of the second dopant in the first semiconductor layer 100 is greater than the concentration of the first dopant. The first dopant is, for example, carbon (C), and the second dopant is, for example, hydrogen (H). Thus, the first semiconductor layer 100 can have a surface with stable properties and fewer epitaxial defects, and can be used as a surface for epitaxial layer growth, for example. In one embodiment, the first semiconductor layer 100 can include a third dopant. The third dopant is, for example, silicon (Si). In one embodiment, the dopants in the first semiconductor layer 100 may each independently have a doping concentration of about 1×10 ¹⁶ cm ^-3 to about 1×10 ¹⁹ cm ^-3 , such as about 5×10 ¹⁶ cm ^-3 to about 5×10 ¹⁷ cm ^-3 , or 6×10 ¹⁷ cm ^-3 to 5×10 ¹⁸ cm ^-3 . In one embodiment, the concentration of the third dopant in the first semiconductor layer 100 is less than 1×10 ¹⁹ cm ^-3 , such as in the range of about 6×10 ¹⁶ cm ^-3 to about 1×10 ¹⁷ cm ^-3 . When the dopant in the first semiconductor layer 100 has an appropriate doping concentration, the first semiconductor layer 100 may have better conductive properties. In one embodiment, the conductive type of the first semiconductor layer 100 is N-type.

In this embodiment, the second semiconductor layer 102 includes a second III-V semiconductor material. The second III-V semiconductor material is a material composed of group III and group V elements in the periodic table of chemical elements. The group III element can be gallium (Ga) or indium (In). The group V element can be arsenic (As) or phosphorus (P), preferably without nitrogen (N). The second III-V semiconductor material is different from the first III-V semiconductor material. In one embodiment, each component element of the second III-V semiconductor material is different from each component element of the first III-V semiconductor material. In one embodiment, the second semiconductor layer 102 is substantially composed of the second III-V semiconductor material, for example, substantially composed of a binary III-V semiconductor material. In one embodiment, the second semiconductor layer 102 is substantially composed of GaAs. The second semiconductor layer 102 may include a plurality of dopants. The plurality of dopants in the second semiconductor layer 102 may each independently have a doping concentration of 5×10 ¹⁵ cm ^-3 to 1×10 ²⁰ cm ^-3 , for example, a doping concentration of 1×10 ¹⁷ cm ^-3 to 1×10 ¹⁸ cm ^-3 , a doping concentration of 1×10 ¹⁸ cm ^-3 to 1×10 ¹⁹ cm ^-3 , or a doping concentration of 1×10 ¹⁹ cm ^-3 to 1×10 ²⁰ cm ^-3 . When the dopants in the second semiconductor layer 102 have an appropriate doping concentration, the second semiconductor layer 102 may have better conductive properties. The dopant in the second semiconductor layer 102 may include silicon (Si), zinc (Zn), carbon (C), or hydrogen (H). In one embodiment, the conductivity type of the second semiconductor layer 102 is N-type. In some embodiments, the first semiconductor layer 100 and the second semiconductor layer 102 have the same conductivity type, for example, both are P-type or N-type. In one embodiment, the resistivity of the second semiconductor layer 102 is in the range of 10 ⁷ Ω. cm or more and 10 ⁹ Ω. cm or less, for example, 10 ⁸ Ω. cm or more.

In some embodiments, the first semiconductor layer 100 and the second semiconductor layer 102 both contain a first dopant, a second dopant, and a third dopant. In some embodiments, the concentration of the third dopant in the second semiconductor layer 102 is higher than the concentration of the third dopant in the first semiconductor layer 100. In some embodiments, the concentration of the second dopant in the second semiconductor layer 102 is higher than the concentration of the second dopant in the first semiconductor layer 100. In some embodiments, the concentration of the first dopant in the second semiconductor layer 102 is lower than the concentration of the first dopant in the first semiconductor layer 100. The first dopant mentioned above is, for example, carbon (C), the second dopant is, for example, hydrogen (H), and the third dopant is, for example, silicon (Si). By containing specific dopants, the first semiconductor layer 100 and the second semiconductor layer 102 can obtain appropriate conductive properties and epitaxial quality.

On the other hand, the first semiconductor layer 100 has a first lattice constant L1, and the second semiconductor layer 102 has a second lattice constant L2. In this embodiment, the first lattice constant L1 is greater than the second lattice constant L2, and the difference ΔL% between the first lattice constant L1 and the second lattice constant L2 is greater than 2%, preferably greater than 2.5% or greater than 3%, and less than 10%, preferably less than 5%. In detail, the difference between the first lattice constant L1 and the second lattice constant L2 can be calculated by the following formula: ΔL%=L1-L2/L2*100%. The above lattice constant refers to the one obtained by measuring the X-ray diffraction spectrum of the semiconductor material at a temperature of 300K. Here we only list the lattice constants of several semiconductor compounds for reference, as shown in Table 1 below.

The first semiconductor layer 100 and the second semiconductor layer 102 can be formed by liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), metal organic chemical vapor deposition (MOCVD), or hydride vapor phase epitaxy (HVPE). In this embodiment, the first semiconductor layer 100 is directly formed on the second semiconductor layer 102 as a substrate. The thickness of the first semiconductor layer can be less than 20 μm, preferably less than 10 μm, more preferably less than 5 μm, and can be more than 1 μm. In one embodiment, the thickness of the first semiconductor layer is 2 μm. When the thickness of the first semiconductor layer 100 is within the above range, it can have better structural stability and can further reduce the impact caused by lattice mismatch. The thickness of the second semiconductor layer 102 can be in the range of about 50μm to about 1000μm, for example, about 100μm to about 400μm or about 150μm to about 350μm. Setting the thickness within the above range can make the semiconductor structure subsequently grown thereon have a more stable structure. When observing the semiconductor stack 10 including the first semiconductor layer 100 and the second semiconductor layer 102 with an electron microscope, it can be observed that there are few epitaxial defects on the surface of the first semiconductor layer 100. In some embodiments, under X-ray diffraction analysis (XRD), the XRD full width at half maximum (FWHM) of the first semiconductor layer 100 can be less than 500 arcsec, preferably less than 350 arcsec, and more preferably less than 300 arcsec, such as within the range of more than 100 arcsec to less than 200 arcsec. Thus, the surface of the first semiconductor layer 100 is more suitable for the growth of other epitaxial layers. Specifically, the first semiconductor layer 100 or the semiconductor stack 10 including the first semiconductor layer 100 and the second semiconductor layer 102 can be used as a growth substrate for semiconductor devices.

FIG. 2A is a partial structural diagram of a semiconductor device 20 according to an embodiment of the present disclosure. In this embodiment, the semiconductor device 20 includes a first semiconductor layer 100, a third semiconductor layer 204, and a light-emitting structure 206. The composition of the first semiconductor layer 100 can be referred to the aforementioned description of the first semiconductor layer 100, which will not be repeated here. In addition, the third semiconductor layer 204 and the light-emitting structure 206 can be sequentially formed on the first semiconductor layer 100 by liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), metal organic chemical vapor deposition (MOCVD), or hydride vapor phase epitaxial (HVPE). In some embodiments, the first semiconductor layer 100, the third semiconductor layer 204, and the light-emitting structure 206 are sequentially formed on the second semiconductor layer 102 as described in the previous embodiment, and then the second semiconductor layer 102 is removed to form the structure shown in FIG. 2A.

As shown in FIG. 2A , the third semiconductor layer 204 is located on the first semiconductor layer 100 and is adjacent to the first semiconductor layer 100. In the present embodiment, no other structure (such as a buffer layer, etc.) exists between the first semiconductor layer 100 and the third semiconductor layer 204. The third semiconductor layer 204 may include a third III-V semiconductor material. The third III-V semiconductor material is a material composed of elements of Group III and Group V in the periodic table of chemical elements. The Group III element may be gallium (Ga) or indium (In). The Group V element may be arsenic (As) or phosphorus (P), preferably excluding nitrogen (N). In some embodiments, the third III-V semiconductor material is the same as the aforementioned first III-V semiconductor material. Specifically, in some embodiments, the third semiconductor layer 204 is substantially composed of a third III-V semiconductor material, such as a binary III-V semiconductor material. In one embodiment, the third semiconductor layer 204 is substantially composed of InP. In addition, the third semiconductor layer 204 may also include a plurality of dopants. In some embodiments, the plurality of dopants in the third semiconductor layer 204 may each independently have a doping concentration of 5×10 ¹⁶ cm ^-3 to 5×10 ¹⁸ cm ^-3 , for example, a doping concentration of 5×10 ¹⁷ cm ^-3 to 2×10 ¹⁸ cm ^-3 , or a doping concentration of 5×10 ¹⁶ cm ^-3 to 5×10 ¹⁷ cm ^-3 . In some embodiments, the first semiconductor layer 100 and the third semiconductor layer 204 both contain a first dopant, a second dopant, and a third dopant. The first dopant is, for example, carbon (C), the second dopant is, for example, hydrogen (H), and the third dopant is, for example, silicon (Si). In some embodiments, forming the third semiconductor layer 204 on the first semiconductor layer 100 helps to further stabilize the epitaxial surface quality. In some embodiments, the third semiconductor layer 204 can be used as a window layer to improve the light-emitting efficiency of the semiconductor device 20, and the third semiconductor layer 204 is transparent to the light emitted by the light-emitting structure 206. In addition, in one embodiment, the conductivity type of the third semiconductor layer 204 is N-type.

The light-emitting structure 206 includes an active structure 210, a fourth semiconductor layer 208, and a fifth semiconductor layer 212. The active structure 210 may include a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantum wells (MQW) structure. When the semiconductor device 20 is in operation, the active structure 210 emits radiation. The radiation is preferably infrared light, such as near infrared light (NIR). In detail, when the radiation is near infrared light, it may have a peak wavelength between 800nm and 1700nm, such as 810nm, 840nm, 910nm, 940nm, 1050nm, 1070nm, 1100nm, 1200nm, 1300nm, 1400nm, 1450nm, 1550nm, 1600nm, 1650nm, 1700nm, etc. The active structure 110 may include a fourth group III-V semiconductor material. The fourth group III-V semiconductor material is a material composed of group III and group V elements in the periodic table of chemical elements. The group III element may be gallium (Ga) or indium (In). The group V element may be arsenic (As) or phosphorus (P), preferably without nitrogen (N). The fourth III-V semiconductor material may be a quaternary III-V semiconductor material. In some embodiments, the active structure 110 is substantially composed of the fourth III-V semiconductor material. For example, the active structure 110 may be substantially composed of a quaternary III-V semiconductor material (such as InGaAsP or AlGaInAs).

The fourth semiconductor layer 208 and the fifth semiconductor layer 212 are respectively located on both sides of the active structure 210, and the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may have opposite conductivity types. For example, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may be n-type semiconductor and p-type semiconductor, respectively, to provide electrons and holes, respectively. Alternatively, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may be p-type semiconductor and n-type semiconductor, respectively, to provide holes and electrons, respectively. The fourth semiconductor layer 208 and the third semiconductor layer 204 may have the same conductivity type, such as both being n-type semiconductor layers. In addition, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 include a fifth group III-V semiconductor material and a sixth group III-V semiconductor material, respectively. The fifth group III-V semiconductor material and the sixth group III-V semiconductor material may be binary, ternary or quaternary group III-V semiconductor materials, respectively. Group III-V semiconductor materials refer to materials composed of group III and group V elements in the periodic table of chemical elements. Group III elements may be gallium (Ga) or indium (In). Group V elements may be arsenic (As) or phosphorus (P), preferably without nitrogen (N). In one embodiment, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 are substantially composed of quaternary semiconductor materials (such as InGaAsP, AlGaInP or AlGaInAs).

The fourth semiconductor layer 208 and the fifth semiconductor layer 212 have different conductivity types by adding different dopants. Specifically, the dopants include magnesium (Mg), zinc (Zn), silicon (Si), tellurium (Te), etc., but are not limited thereto. In some embodiments, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 can be doped by in-situ doping during epitaxial growth and/or by implanting P-type or N-type dopants after epitaxial growth. In one embodiment, the dopant in the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may each independently have a dopant concentration of 2×10 ¹⁷ cm ⁻³ to 1×10 ²⁰ cm ⁻³ , for example, a dopant concentration of 5×10 ¹⁷ cm ⁻³ to 5×10 ¹⁹ cm ⁻³ .

In some embodiments, an etching stop layer may be further disposed between the first semiconductor layer 100 and the light emitting structure 206. Referring to FIG. 2A, for example, the etching stop layer (not shown) may be disposed between the first semiconductor layer 100 and the third semiconductor layer 204. Then, the first semiconductor layer 100 may be removed according to the requirements of the device structure, thereby forming a semiconductor device 20' as shown in FIG. 2B. By disposing the etching stop layer, the third semiconductor layer 204 and the light emitting structure 206 may be prevented from being damaged when the first semiconductor layer 100 is removed. Next, the semiconductor device 20' may include a bonding layer (not shown), and is bonded to a supporting substrate through the bonding layer, and subsequent processes are performed. In one embodiment, the semiconductor device 20' only includes the structure shown in FIG. 2B without a supporting substrate. In some embodiments, the etch stop layer includes a seventh group III-V semiconductor material. The seventh group III-V semiconductor material may be a ternary or quaternary group III-V semiconductor material. The group III-V semiconductor material is a material composed of group III and group V elements in the periodic table of chemical elements. The group III element may be aluminum (Al), gallium (Ga) or indium (In). The group V element may be arsenic (As) or phosphorus (P), preferably without nitrogen (N). The etch stop layer preferably includes a Group V element different from the Group V element in the composition of the first semiconductor layer 100. In one embodiment, the etch stop layer includes a ternary III-V semiconductor material of InGaAs. In one embodiment, the etch stop layer is substantially composed of a ternary semiconductor material, such as InGaAs.

Based on the above, since the first semiconductor layer 100 can have a surface with a lower defect density, it is more suitable as a base layer for the growth of semiconductor epitaxial layers. Specifically, when the third semiconductor layer 204 and other semiconductor layers are further formed on the first semiconductor layer 100, each semiconductor layer can still have good epitaxial quality.

FIG. 3 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present disclosure. In this embodiment, the semiconductor device 30 includes a first semiconductor layer 300, a third semiconductor layer 304, a light-emitting structure 306, a window layer 314, a first electrode 318, and a second electrode 320. The composition of the first semiconductor layer 300, the third semiconductor layer 304, and the light-emitting structure 306 can be referred to the above description of the first semiconductor layer 100, the third semiconductor layer 204, and the light-emitting structure 206, and will not be repeated here. In detail, the composition of the fourth semiconductor layer 308, the active structure 310 and the fifth semiconductor layer 312 in the light-emitting structure 306 can refer to the aforementioned description of the fourth semiconductor layer 208, the active structure 210 and the fifth semiconductor layer 212, respectively.

In this embodiment, the window layer 314 is located on the light-emitting structure 306 and is adjacent to the fifth semiconductor layer 312 in the light-emitting structure 306. In addition, the conductivity type of the window layer 314 is opposite to the conductivity type of the third semiconductor layer 304. For example, when the window layer 314 is a P-type semiconductor layer, the third semiconductor layer 304 is an N-type semiconductor layer. The window layer 314 can be used as a light extraction layer to further improve the light-emitting efficiency of the semiconductor element 30. In addition, the window layer 314 is transparent to the light emitted by the light-emitting structure 306.

The first electrode 318 and the second electrode 320 can be used to be electrically connected to an external power source, and the first electrode 318 and the second electrode 320 are electrically connected to the light emitting structure 306. In this embodiment, the first electrode 320 is adjacent to the window layer 314, and the second electrode 318 is adjacent to the first semiconductor layer 300, but it is not limited thereto. In addition, the materials of the first electrode 318 and the second electrode 320 can be the same or different, and for example include transparent conductive materials, metals or alloys. The transparent conductive material includes metal oxides, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO). Metals can be listed as gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), copper (Cu) or nickel (Ni). The alloy can include at least two selected from the group consisting of the above metal elements, such as germanium gold nickel (GeAuNi), benzene gold (BeAu), germanium gold (GeAu), zinc gold (ZnAu), etc.

FIG. 4 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure. In this embodiment, the semiconductor device 40 includes a first semiconductor layer 400, a second semiconductor layer 402, a third semiconductor layer 404, a light-emitting structure 406, a window layer 414, a contact layer 416, a first electrode 420, and a second electrode 418. The main difference between the semiconductor device 40 and the aforementioned semiconductor device 30 is that the semiconductor device 40 further includes a second semiconductor layer 402 and a contact layer 416. The composition of the first semiconductor layer 400, the second semiconductor layer 402, the third semiconductor layer 404, the light-emitting structure 406, the window layer 414, the first electrode 420 and the second electrode 418 can refer to the description of the aforementioned embodiment, and will not be repeated here. In detail, the composition of the fourth semiconductor layer 408, the active structure 410 and the fifth semiconductor layer 412 in the light-emitting structure 406 can refer to the aforementioned description of the fourth semiconductor layer 208, the active structure 210 and the fifth semiconductor layer 212, respectively.

The contact layer 416 is located between the first electrode 420 and the window layer 414 for conducting current. The contact layer 416 may have the same conductivity type as the window layer 314, for example, a P-type semiconductor layer. In the present embodiment, the contact layer 416 is adjacent to the first electrode 420. In detail, the contact layer 416 is, for example, a doped or undoped semiconductor material layer, and may include an eighth group III-V semiconductor material. The eighth group III-V semiconductor material may be a binary or ternary group III-V semiconductor material, for example, GaAs or InGaAs. When the first electrode 420 includes a metal or an alloy, an ohmic contact can be formed between the first electrode 420 and the contact layer 416, so that a good electrical contact is formed between the first electrode 420 and the light-emitting structure 406.

Figures 5A to 5B are schematic cross-sectional views of a method for manufacturing a semiconductor stack according to an embodiment of the present disclosure. Figure 5C is a flow chart of a semiconductor stack according to an embodiment. The semiconductor stack is, for example, a partial structure of a semiconductor element. As shown in Figures 5A and 5B, a second semiconductor layer 502 is first provided, and a first semiconductor layer 500 is formed on the second semiconductor layer 502. The description of the first semiconductor layer 500 and the second semiconductor layer 502 can refer to the description of the first semiconductor layer 100 and the second semiconductor layer 102 in the aforementioned embodiment, and will not be repeated here.

Referring to FIGS. 5A to 5C , step S510 is performed to grow a portion of the first semiconductor layer 500 at a first temperature. The growth of the first semiconductor layer 500 is achieved, for example, by liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), metal organic chemical vapor deposition (MOCVD), or hydride vapor phase epitaxial (HVPE). The first temperature is, for example, below 650° C. and above 400° C., preferably not more than 520° C., and more preferably in the range of 450° C. to 510° C. or 420° C. to 500° C. By growing the first semiconductor layer 500 within the above temperature range, good epitaxial quality can be further obtained.

Next, step S520 is performed to provide a second temperature greater than the first temperature. The second temperature is, for example, above 700°C and below 850°C, preferably greater than 750°C, and more preferably in the range of 760°C to 810°C or 780°C to 800°C. In step S520, for example, the epitaxial environment temperature is adjusted from the first temperature to the second temperature. In some embodiments, the difference between the first temperature and the second temperature is not less than 300°C, thereby achieving a better epitaxial effect. In addition, at the second temperature, the growth of the first semiconductor layer 500 may not be performed. In this step, high-temperature annealing is performed by adjusting the ambient temperature to the higher second temperature. Not continuing to grow the first semiconductor layer 500 at the second temperature can adjust the stress in a portion of the first semiconductor layer 500 previously grown at the first temperature, thereby reducing epitaxial defects.

Then, the process proceeds to step S530 to confirm the thickness of the first semiconductor. When the first semiconductor layer 500 has reached the predetermined thickness, the preparation of the first semiconductor layer 500 and the second semiconductor layer 502 is completed. In some embodiments, the predetermined thickness may be less than 20 μm, preferably less than 10 μm, more preferably less than 5 μm, and may be greater than 1 μm. When the first semiconductor layer 500 has not yet reached the predetermined thickness, the process proceeds to step S540 to repeat step S510 and step S520, for example, repeat step S510 and step S520 at least twice. In some embodiments, step S510 and step S520 may be repeated more than ten times to obtain a semiconductor stack of appropriate thickness and more stable epitaxial quality. In addition, the number of times step S510 and step S520 may be repeated less than thirty times.

Based on the above, by heating and cooling the first semiconductor layer 500 during the preparation process, it is not necessary to use other buffer structures or processes to adjust the stress caused by lattice mismatch between the first semiconductor layer 500 and the second semiconductor layer 502, and a structure with good epitaxial quality can be obtained.

In some embodiments, the stack of the first semiconductor layer 500 and the second semiconductor layer 502 can be used as a base layer, and subsequent epitaxial structure growth can be performed as required, for example, a light-emitting structure can be further directly formed on the stack of the first semiconductor layer 500 and the second semiconductor layer 502.

As shown in FIG. 5D , a third semiconductor layer 504 can be further formed on the first semiconductor layer 500 and the second semiconductor layer 502. The description of the third semiconductor layer 504 can refer to the description of the third semiconductor layer 204 in the aforementioned embodiment, and will not be repeated here. As mentioned above, the light-emitting structure can be formed on the third semiconductor layer 504. One side of the first semiconductor layer 500 is adjacent to the second semiconductor layer 502, and the other side is adjacent to the third semiconductor layer 504. The surface 500a of the first semiconductor layer 500 directly contacts the surface 502a of the second semiconductor layer 502, and the other surface 500b directly contacts the surface 504a of the third semiconductor layer 504.

FIG. 5E is a graph showing the relationship between the concentration and thickness of an element in a partial range of a semiconductor device according to an embodiment of the present disclosure. Specifically, FIG. 5E is the result of a secondary ion mass spectrometry (SIMS) analysis of a partial region of a light-emitting device including the structure shown in FIG. 5D. As shown in FIG. 5E, according to the thickness and sequence of each layer in the semiconductor device, it can be roughly divided into a first zone Z1, a second zone Z2, and a third zone Z3. Specifically, the first zone Z1 corresponds to the second semiconductor layer 502, the second zone Z2 corresponds to the first semiconductor layer 500, and the third zone Z3 corresponds to the third semiconductor layer 504. In this embodiment, the first semiconductor layer 500 and the third semiconductor layer 504 both contain a plurality of dopants and are substantially composed of InP, and the second semiconductor layer 502 contains a plurality of dopants and is substantially composed of GaAs. The above-mentioned dopants include at least a first dopant, a second dopant, and a third dopant. The first dopant is carbon (C) and is represented by C1, the second dopant is hydrogen (H) and is represented by C2, and the third dopant is silicon (Si) and is represented by C3. Please refer to the vertical axis on the left of Figure 5E for the concentrations of the first, second and third dopants C1, C2 and C3. In this embodiment, the first dopant and the second dopant are unintentional dopants, and the third dopant is an intentional dopant.

By growing the first semiconductor layer 500 of the single-layer structure in the above-mentioned manner, the first dopant and the second dopant that are not intentionally doped have a doping concentration greater than 10 ¹⁶ cm ^-3 in the first semiconductor layer 500, and the concentration curve of carbon (C) has a pattern similar to a periodic change. As shown in FIG. 5E , in the second zone Z2, the concentration of the second dopant is higher than the concentration of the first dopant, that is, the concentration of hydrogen (H) is greater than the concentration of carbon (C) in the first semiconductor layer 500. In addition, the concentration of the third dopant in the second zone Z2 is lower than the concentration of the third dopant in the first zone Z1, and is also lower than the concentration of the third dopant in the third zone Z3. That is, the silicon (Si) concentration in the first semiconductor layer 500 is lower than the silicon (Si) concentration in the second semiconductor layer 502 or the third semiconductor layer 504. On the other hand, in the second zone Z2, the concentration of the second dopant is higher than the concentration of the third dopant, that is, the hydrogen (H) concentration in the first semiconductor layer 500 is greater than the silicon (Si) concentration.

FIG. 5F is a partially enlarged schematic diagram of the concentration curve of the first dopant (carbon (C)) in the dotted box area in the second zone Z2 of FIG. 5E. As shown in FIG. 5F, in this embodiment, the concentration distribution of the first dopant (carbon (C)) includes at least i local maxima (such as the concentrations C _L1 , C _L2 , ..., C _Li indicated in the figure) and i local minima (such as the concentrations C _M1 , C _M2 , ..., C _Mi indicated in the figure), i is, for example, a positive integer greater than or equal to 5, and i=8 in the local area shown in FIG. 5F. The local maximum and the local minimum appear alternately, and any of the local maxima is greater than any of the local minimums. As shown in FIG. 5E , in the first block of the second zone Z2 , the concentration of the third dopant is less than some local maximum values; and in the second block of the second zone Z2 , the concentration of the third dopant is greater than some local minimum values.

As shown in FIG. 5E , in this embodiment, the doping concentration of silicon (Si) in the first semiconductor layer 500 is below 1×10 ¹⁷ cm ^-3 and is in the range of about 5×10 ¹⁶ cm ^-3 to about 9×10 ¹⁶ cm ^-3 ; the concentration of carbon (C) is in the range of about 4×10 ¹⁶ cm ^-3 to about 9×10 ¹⁶ cm ^-3 ; and the concentration of hydrogen (H) is in the range of about 1×10 ¹⁷ cm ^-3 to about 5×10 ¹⁷ cm ^-3 . On the other hand, in some embodiments, the first zone Z1, the second zone Z2, and the third zone Z3 further include inevitable impurities, such as oxygen (O), etc., which are not shown here for simplicity. In one embodiment, the oxygen (O) concentrations in the first zone Z1, the second zone Z2, and the third zone Z3 are distributed in the range of 3×10 ¹⁵ cm ^-3 to 2×10 ¹⁶ cm ^-3 , which is close to the detection limit of secondary ion mass spectrometry (SIMS) analysis.

FIG. 6 is a schematic diagram of a semiconductor device package structure of an embodiment of the present disclosure. Referring to FIG. 6 , the package structure 600 includes a semiconductor device 60, a package substrate 61, a carrier 63, a bonding wire 65, a contact structure 66, and a package material 68. The package substrate 61 may include a ceramic or glass material. The package substrate 61 has a plurality of through holes 62. The through holes 62 may be filled with a conductive material such as metal to facilitate electrical conduction and/or heat dissipation. The carrier 63 is located on the surface of one side of the package substrate 61 and also includes a conductive material such as metal. The contact structure 66 is located on the surface of the other side of the package substrate 61. In the present embodiment, the contact structure 66 includes a contact pad 66a and a contact pad 66b, and the contact pad 66a and the contact pad 66b can be electrically connected to the carrier 63 through the through hole 62. In one embodiment, the contact structure 66 can further include a thermal pad (not shown), for example, located between the contact pad 66a and the contact pad 66b. The semiconductor element 60 is located on the carrier 63 and can be the semiconductor element described in any embodiment of the present disclosure. In the present embodiment, the carrier 63 includes a first portion 63a and a second portion 63b, and the semiconductor element 60 is electrically connected to the second portion 63b of the carrier 63 through a bonding wire 65. The material of the bonding wire 65 may include metal, such as gold, silver, copper, aluminum, or an alloy containing at least one of the above elements. The packaging material 68 covers the semiconductor element 60 and has the effect of protecting the semiconductor element 60. Specifically, the packaging material 68 may include a resin material such as epoxy, silicone, etc. The packaging material 68 may further include a plurality of wavelength conversion particles (not shown) to convert the first light emitted by the semiconductor element 60 into a second light. The wavelength of the second light is greater than the wavelength of the first light.

The light-emitting element disclosed herein can be applied to products in the fields of lighting, medical treatment, display, communication, sensing, power supply system, etc., such as lamps, monitors, mobile phones, tablet computers, car dashboards, TVs, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signs, outdoor displays, medical equipment, etc.

Based on the above, according to some embodiments of the present disclosure, a semiconductor structure can be provided, which has good surface epitaxial quality, for example, it can be used as a substrate of a semiconductor element, and it is beneficial to further reduce the production cost of the semiconductor element. According to some embodiments of the present disclosure, a semiconductor element and its manufacturing method can be provided, which achieves excellent technical effects in adjusting the stress generated by lattice mismatch between heterogeneous epitaxy, and can avoid defects in the epitaxial layer at the interface.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the relevant technical field should understand that some modifications or changes can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application. In addition, the contents of the above embodiments can be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described. For example, the relevant parameters of a specific component disclosed in an embodiment or the connection relationship between a specific component and other components can also be applied to other embodiments, and all fall within the scope of protection of the present invention.

10: Semiconductor stacking

100: First semiconductor layer

102: Second semiconductor layer

100a, 102a: surface

Claims (10)

A semiconductor element comprises: a first semiconductor layer comprising a first III-V semiconductor material; a light-emitting structure located on the first semiconductor layer and comprising an active structure; and a second semiconductor layer located below the first semiconductor layer and comprising a second III-V semiconductor material; a third semiconductor layer located between the first semiconductor layer and the light-emitting structure and comprising a third III-V semiconductor material; The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer include a first dopant and a second dopant, the concentration of the first dopant in the first semiconductor layer is greater than the concentration of the first dopant in the second semiconductor layer, and the concentration of the first dopant in the first semiconductor layer is is greater than the concentration of the first dopant in the third semiconductor layer, the concentration of the second dopant in the first semiconductor layer is lower than the concentration of the second dopant in the second semiconductor layer, and the concentration of the second dopant in the first semiconductor layer is lower than the concentration of the second dopant in the third semiconductor layer. A semiconductor device as described in claim 1, wherein the light-emitting structure emits near-infrared light having a peak wavelength between 800 nm and 1700 nm. A semiconductor device as described in claim 1, wherein the second III-V semiconductor material is different from the first III-V semiconductor material. The semiconductor device as described in claim 1 further comprises a fourth semiconductor layer located between the third semiconductor layer and the light-emitting structure and comprising a binary, ternary or quaternary III-V semiconductor material. The semiconductor device as described in claim 1, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer further include a third dopant. A semiconductor element as described in claim 1, wherein in the first semiconductor layer, the concentration distribution of the first dopant includes at least a plurality of local maxima and a plurality of local minima, the local maxima and the local minima appear alternately, and any one of the local maxima is greater than any one of the local minima. A semiconductor device as described in claim 1, wherein the concentration distribution of the first dopant includes at least 5 local maxima and 5 local minima. A semiconductor device as described in claim 1, wherein the first dopant and the second dopant include silicon (Si), zinc (Zn), carbon (C) or hydrogen (H). A semiconductor device as described in claim 1, wherein in the third semiconductor layer, the concentration of the first dopant is lower than the concentration of the second dopant. A semiconductor component packaging structure, comprising: a carrier; a semiconductor component, located on the carrier and being a semiconductor component as described in any one of claim 1 to claim 9; and a packaging material, covering the semiconductor component.