TWI858366B - Vertical transfer structures - Google Patents

Abstract

Pixels, such as for image sensors and electronic devices, include a photodiode formed in a semiconductor substrate, a floating diffusion, and a transfer structure selectively coupling the photodiode to the floating diffusion. The transfer structure includes a transfer gate formed on the semiconductor substrate, and a vertical channel structure including spaced apart first doped regions formed in the semiconductor substrate between the transfer gate and the photodiode. Each spaced apart first doped region is doped at a first dopant concentration with a first-type dopant. The spaced apart first doped regions are formed in a second doped region doped at a second dopant concentration with a second-type dopant of a different conductive type.

Description

Vertical transmission structure

The present invention relates generally to image sensors and, particularly but not exclusively, to vertical transmission structures for image sensors.

Image sensors are everywhere. They are widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. The technology used to make image sensors continues to advance at a rapid pace. For example, the demand for higher resolution and lower power consumption is driving further miniaturization and integration of these devices. These trends are also contributing to increasing pixel counts.

In a pixel architecture, forming a photodiode deep within the pixel can improve full well capacity, reduce white pixels (WP), and enable a smaller layout. In such embodiments, a vertical transfer gate is typically utilized to transfer charge carriers from the photodiode to other pixel elements (e.g., a floating diffusion region). The vertical transfer gate is typically formed by etching a columnar or monolithic recess in a semiconductor substrate, depositing an oxide layer in the recess, and then depositing a conductive gate material in the recess over the oxide layer. However, such vertical transfer gates have a greater number of surfaces than planar transfer gates, and producing the surfaces by etching, such as plasma etching, can introduce surface defects into the semiconductor substrate, which in turn can cause white pixels and other deleterious effects. Furthermore, selecting the gate control voltage of the vertical transfer gate during an integration period usually requires a trade-off between bloom and white pixels.

The present invention provides a structure to solve these disadvantages.

The above information is presented as background information only to assist in understanding the present invention. No determination has been made, and no assertion is made, as to whether any of the above may be applicable as prior art with respect to the present invention.

The present invention relates to image sensors, and in particular, to vertical transfer structures for image sensors. To facilitate understanding, the present invention describes the vertical transfer structure in the context of a complementary metal oxide semiconductor ("CMOS") image sensor. However, it should be understood that the present invention should not be limited to vertical transfer structures for CMOS image sensors, but can be applied to non-CMOS image sensors. In the following description, many specific details are explained to provide a thorough understanding of one of the examples. However, those skilled in the art will recognize that the techniques described herein may be practiced without one or more of the specific details, or using other methods, components, materials, etc. In other examples, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring specific aspects.

References throughout this specification to "one embodiment" or "some embodiments" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. Therefore, the phrases "in some embodiments" or "in an embodiment" appearing throughout this specification do not necessarily all refer to the same embodiment. In addition, the particular features, structures, or characteristics of any embodiment may be combined with any features of any other embodiment to achieve yet other embodiments within the scope of the present invention.

The present invention refers to several terms with respect to different embodiments, including apparatus and methods. Terms with similar names have similar meanings with respect to different embodiments, unless expressly noted. Similarly, the present invention utilizes several technical terms. Such terms have their ordinary meanings in the fields from which they are derived, unless specifically defined herein or the context of their use would clearly suggest otherwise. It should be noted that element names and symbols (e.g., Si and silicon) may be used interchangeably throughout this document; however, both have the same meaning. Terms with similar names have similar meanings with respect to different embodiments, unless expressly noted.

For ease of description, spatially relative terms such as "below," "beneath," "under," "under," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature, as depicted in the figures. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is turned over, an element described as "below," "beneath," or "under" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may cover both orientations of "above" and "below." The device may be oriented in other ways (rotated ninety degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the present invention, the term "semiconductor substrate" or "substrate" refers to any type of substrate used to form semiconductor devices thereon, including single crystal substrates, semiconductor-on-insulator (SOI) substrates, doped silicon substrates, and epitaxial-on-semiconductor (EPI) substrates, and the like. The term semiconductor substrate may also refer to a substrate formed of one or more semiconductors that undergo pre-processing steps to form regions and/or junctions in the substrate, including etching, material deposition, and ion implantation. In addition, although various embodiments will be described primarily with respect to materials and processes compatible with silicon-based semiconductor materials (e.g., silicon and alloys of silicon with germanium and/or carbon), the present technology is not limited in this regard. Instead, the various embodiments may be implemented using any type of semiconductor material, such as gallium arsenide, indium gallium arsenide, and other semiconductor materials known to those skilled in the art.

It should be understood that the term "photodiode doped region" may correspond to a region within a semiconductor substrate that has been doped, for example by ion implantation, to have a charge carrier type (i.e., conductivity type) that is opposite to the majority charge carrier type of the semiconductor substrate, such that a periphery of the doped region (e.g., referred to herein as the photodiode doped region) forms a PN junction or PIN junction of a photodiode. For example, an N-doped region formed in a P-type semiconductor substrate forms a corresponding photodiode region. In some embodiments, a photodiode may further include a pinning region (e.g., a doped region disposed between one side of the semiconductor substrate and a photodiode doped region having a conductivity type opposite to the conductivity type of the photodiode region) to form a pinned photodiode. For example, when the photodiode doped region is an N-type conductivity and the semiconductor substrate is also a P-type conductivity, the pinning region may have a P-type conductivity.

The present application may also cite quantities and numbers. Unless specifically stated, such quantities and numbers should not be considered restrictive, but rather represent possible quantities or numbers associated with the present application. Furthermore, in this regard, the present application may use the term "plurality" to refer to a quantity or number. In this regard, the term "plurality" means any number more than one, such as two, three, four, five, etc. The terms "about," "approximately," "close to," etc. mean plus or minus 5% of the stated value. For the purposes of the present invention, the phrase "at least one of A, B, and C" means, for example, (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all further possible arrangements when more than three elements are listed. The phrase "at least one of A, B, or C" has the same meaning.

1 is a diagram showing an example of a representative image sensor 100 having a pixel array 102 of pixels 120. As shown, pixel array 102 is coupled to a readout circuitry 104 (which is coupled to a functional logic 106) and a control circuit 108.

Pixel array 102 is a two-dimensional ("2D") array of pixels 120 (e.g., pixels P1, P2, . . . , Pn). In one embodiment, each pixel 120 is a complementary metal oxide semiconductor ("CMOS") imaging pixel. Pixel array 102 may be implemented as a back-illuminated image sensor array. In some embodiments, one or more of pixels 120 include one or more pixel elements as described below, including a transfer structure having one or more of the vertical transfer structures described herein, a floating diffusion region, a source follower transistor, a row select transistor, and a reset transistor. As shown, pixels 120 are arranged in rows (eg, rows R1 to Ry) and columns (eg, rows C1 to Cx) to obtain image data of a person, place, or object, which can then be used to reconstruct a 2D image of the person, place, or object.

After the pixel 120 has acquired its image data or image charge, the image data is read out by the readout circuitry 104 and transmitted to the function logic 106. The readout circuitry 104 may include amplification circuitry, such as a differential amplifier circuitry, analog-to-digital ("ADC") conversion circuitry, or other circuitry. In some embodiments, the readout circuitry 104 may read out the image data one row at a time along the readout row (as shown) or may use a variety of other techniques (not shown) to read out the image data, such as serial readout or fully parallel readout of all pixels at the same time.

Function logic 106 includes logic and memory for storing image data or even manipulating image data by applying image post-effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or otherwise).

The control circuit 108 is coupled to the pixels 120 and includes logic and memory for controlling the operating characteristics of the pixels 120. For example, the control circuit 108 may generate voltage control signals (e.g., transmit signals and cutoff signals) that control the operation of the transmission structures associated with each pixel 120. For example, the control circuit 108 may generate a shutter signal for controlling image acquisition. In some embodiments, the shutter signal is a global shutter signal that simultaneously enables all pixels 120 to simultaneously capture their respective image data during a single acquisition window. In some embodiments, the shutter signal is a rolling shutter signal, whereby each column, row, or group of pixels 120 is sequentially enabled during consecutive acquisition windows.

FIG2 shows a layout of a representative pixel 220, which forms part of an image sensor such as image sensor 100 of FIG1, which itself may be integrated into an electronic device such as a smart phone, a digital camera, an endoscope, or the like. The pixel layout shown in FIG2 is representative, and the teachings of the present invention—particularly the transmission structure described below—may be embodied in many other pixel layouts.

The pixel 220 is at least partially formed by a semiconductor substrate 222 having an active pixel region and a device transistor region. The active pixel region includes at least one photodiode 224, a floating diffusion region 226, and a transmission structure 250 configured to selectively form a charge carrier channel between the photodiode 224 and the floating diffusion region 226. The transmission structure 250 includes a vertical channel structure 252 and a transmission gate 254 as described in detail below. The photodiode 224 is formed in the semiconductor substrate 222 below the floating diffusion region 226 and the transmission structure 250. In any embodiment, in order to increase the full well capacity of the photodiode 224, a portion of the photodiode 224 may extend and be formed below the transistor elements in the device transistor region, for example, to the extent of the boundary 227a, wherein the device transistor region includes at least a reset transistor 228, a source follower transistor 230, and a row of select transistors 232. In some embodiments, the photodiode 224 may not extend below the device transistor region, for example, the photodiode 224 may reach the extent of the boundary 227b. In an embodiment, a portion of the photodiode 224 may be configured and extended to a position between the boundary 227a and the boundary 227b.

Photodiode 224 is configured to photogenerate and accumulate charge carriers (e.g., electrons, holes) in response to incident light received during an integration cycle of the image sensor. For example, during an integration cycle of the image sensor, photogenerated charge carriers accumulate in a charge accumulation region of photodiode 224 (e.g., the source of transfer gate 254) and can be selectively transferred to floating diffusion region 226 (e.g., the drain of transfer gate 254) depending on a voltage applied to transfer structure 250 (e.g., vertical channel structure 252 and transfer gate 254 of transfer structure 250).

The photodiode 224 can be in various configurations, including but not limited to, a pinned photodiode configuration and a partially pinned photodiode configuration. In some embodiments, a pinning layer having a conductivity opposite to that of the photodiode 224 (e.g., the pinning layer is a P-type doped layer when the photodiode 224 is N-type) is disposed between a front surface of the semiconductor substrate 222 and an N-type photodiode region of the photodiode 224, wherein the pinning layer is coupled to ground.

The floating diffusion region 226 is coupled to the transmission structure 250 and a gate SF of the source follower transistor 230. The floating diffusion region 226 collects the electric carriers from the photodiode 224 and optionally additional photodiodes and outputs a corresponding voltage to the gate SF of the source follower transistor 230 for signal reading.

The transmission structure 250 includes a vertical channel structure 252 and a transmission gate 254. The transmission gate 254 is electrically coupled to the vertical channel structure 252. In an embodiment, the transmission gate 254 is a planar gate electrode formed on a surface (e.g., a front surface or a non-illuminated surface) of the semiconductor substrate 222, and the vertical channel structure 252 is formed in the semiconductor substrate 222 below the transmission gate 254. The transmission gate 254 is disposed between the vertical channel structure 252 and the floating diffusion region 226, and couples the vertical channel structure 252 to the floating diffusion region 226. The transfer gate 254 and the vertical channel structure 252 cooperate to form a conduction channel that selectively transfers charge from the photodiode 224 to the floating diffusion region 226 (under the operation of a control circuit such as the control circuit 108 of FIG. 1 ). The floating diffusion region 226 then outputs a voltage to the gate SF of the source follower transistor 230 based on the amount of charge accumulated in the floating diffusion region 226. The source follower transistor 230 outputs an amplified image signal in response to the voltage received at its gate SF. The transmission structure 250 (specifically, its vertical channel structure 252) extends to a depth in the semiconductor substrate 222 near the photodiode 224, and thus enables the photodiode 224 to be buried in the semiconductor substrate 222 away from the front surface of the semiconductor substrate 222, which can reduce or eliminate dark current caused by surface defects. In any embodiment, the photodiode 224 can be further formed below a portion of the device transistor area and below a portion of the active pixel area. At the same time, the transmission structure 250 avoids the disadvantages of traditional vertical transmission gates, namely, surface defects caused by dry etching of vertical pillars into the semiconductor substrate 222. A representative transmission structure similar to the transmission structure 250 is described in detail below.

The reset transistor 228 is coupled between a power line and the floating diffusion region 226 to reset (e.g., discharge) the residual charge in the floating diffusion region 226 and charge the floating diffusion region 226 to a preset voltage, such as a supply voltage, under the control of a reset signal, such as from a control circuit (e.g., control circuit 108) at a gate RST of the reset transistor 228 during a reset cycle of the image sensor. Under the control of the reset signal received at the gate RST of the reset transistor 228 during the reset cycle, the reset transistor 228 can further couple the photodiode 224 to a preset voltage, such as the supply voltage, via the transmission structure 250. .

Source follower transistor 230 is coupled between a power line and a column select transistor 232 and modulates an image signal output based on a voltage at a floating diffusion region 226 at its gate SF, wherein the image signal corresponds to the amount of photoelectrons accumulated in the photodiode 224 of the pixel 220 in response to the amount of incident light absorbed during an integration cycle of the image sensor.

Column select transistor 232 selectively couples the output of source follower transistor 230 (eg, image signal) to the readout row line under control of a column select signal received from a control circuit (eg, control circuit 108) at a gate RS of column select transistor 232 during a readout operation of the image sensor.

The channel isolation structures 234, 236 electrically isolate the transistor elements in the device transistor region from the photodiode 224, the transmission structure 250, and the floating diffusion region 226 in the active pixel region. In some embodiments, the channel isolation structures 234, 236 can be dielectric-filled trench isolation structures, such as shallow trench isolation structures or deep trench isolation structures. In some embodiments, the channel isolation structures 234, 236 can be doped well isolation structures having a conductivity type opposite to that of the photodiode 224. In some embodiments, the channel isolation structures 234, 236 may be a combination of a dielectric-filled trench isolation structure and a doped well isolation structure. In one example, a dielectric-filled trench isolation structure may be formed in a respective doped well isolation region.

In some embodiments, the pixel 220 may include additional elements not described in detail herein, such as one or more additional isolation structures, transistors, capacitors, floating diffusion regions, or the like. In the illustrated example, the pixel 220 includes a single photodiode 224; however, some embodiments include a plurality of photodiodes sharing a common floating diffusion region, a common source follower transistor, a common reset transistor, and a common column select transistor, for example, through respective coupled transmission structures 250.

In operation, during the integration cycle of the image sensor (also referred to as the exposure or accumulation cycle), the photodiode 224 absorbs incident light directed toward the pixel 220 and photogenerates one or more charges in its charge accumulation region. The photogenerated charges accumulated in the charge accumulation region of the photodiode 224 indicate the amount of incident light incident on the photodiode 224. During the integration cycle, the transmission structure 250 is biased off. In some embodiments, the transmission structure 250 is controlled (e.g., via a bias voltage) to implement a halo path from the photodiode 224 to the floating diffusion region 226, thereby allowing excess photogenerated charge to flow from the photodiode 224 to the floating diffusion region 226, thereby preventing excess photogenerated charge in the photodiode 224 from flowing to neighboring photodiodes during the integration period. After the integration period, one or more transfer signals are applied to the transfer structure 250 (e.g., a separate control signal may be applied to the vertical channel structure 252 and the transfer gate 254), such as from the control circuit 108 of FIG. 1 , which forms a charge carrier channel in the semiconductor substrate 222 near the transfer gate 254 and the vertical channel structure 252 and transfers (some) of the photogenerated charges from the photodiode 224 to the floating diffusion region 226 through the charge carrier channel during the charge transfer cycle of the image sensor. The source follower transistor 230 is operable to generate an image signal based on the voltage output by the coupled floating diffusion region 226. The column select transistor 232 coupled to the source follower transistor 230 then selectively couples the image signal to a respective readout row line or a row of bit lines for subsequent image processing when a column select signal is received during a readout cycle.

3A to 3C show cross-sectional views of a representative transmission structure 350 formed in a pixel 320 having a photodiode 324 and a floating diffusion region 326. The transmission structure 350 is configured to form a carrier channel between the photodiode 324 and the floating diffusion region 326, and has the same structure as the transmission structure 250 of FIG. 2 . Specifically, FIG. 3A shows a cross-sectional view of the pixel 320 and the transmission structure 350 taken along a cross-sectional line equivalent to the line AA' shown in FIG. 2 . FIG. 3B shows a second cross-sectional view of the pixel 320 and the transmission structure 350 taken along a cross-sectional line equivalent to the line BB' shown in FIG. 2 . FIG. 3C shows a cross-sectional view of the pixel 320 and the transmission structure 350 taken along a cross-sectional line equivalent to the line CC' shown in FIG. 2 .

3A , pixel 320 includes a semiconductor substrate 322 having a photodiode 324 formed therein, the photodiode including a photodiode doped region having a conductivity type (e.g., N-type) opposite to the conductivity type (e.g., P-type) of the surrounding semiconductor substrate 322. In one embodiment, the photodiode doped region may extend deeper into the semiconductor substrate 322 adjacent to a back side 340 of the semiconductor substrate 322. It should be understood that the photodiode may include an interface between the photodiode doped region and (several) differently doped regions of the semiconductor substrate 322. The photodiode doping region and the doping region(s) of the semiconductor substrate 322 may form a charge accumulation region for accumulating photogenerated charge of the photodiode 324. It should be understood that the polarity of the photodiode 324 may be reversed; for example, in some embodiments, the photodiode doping region may be P-type doped in an N-type semiconductor substrate 322. The photodiode doping region of the photodiode 324 has a PD dopant concentration that is typically less than the dopant concentration of the vertical channel structure of the transmission structure 350, as described below. This application relates to "dopant concentration" (charge carriers per unit volume) and "dopant dosage" (charge carriers per unit area). The relationships described herein for dopant concentrations between different elements of a pixel also apply to the relationships between dopant dosages used to dope those elements. Although the PD dopant concentration/dosage may vary between embodiments, in some embodiments, the photodiode doping region is doped with a dopant at a PD dopant dosage of about E11/ ^cm2 to about E12/ ^cm2 .

In some embodiments, the PD dopant concentration of the photodiode doping region is greater than the dopant concentration of the semiconductor substrate 322. In some embodiments, the dopant concentration of the photodiode doping region varies along the depth of the semiconductor substrate 322. For example, in some embodiments, the concentration of the photodiode doping region decreases as its depth into the semiconductor substrate 322 increases (i.e., toward the back side 340).

Optional isolation structures 334, 336 delimit at least a portion of the photodiode 324 and the transmission structure 350 to electrically/optically isolate those elements from other pixel elements (e.g., adjacent photodiodes). In some embodiments, the isolation structures 334, 336 are formed by isolation wells having a conductivity type opposite to that of the photodiode 324 and the same as that of the semiconductor substrate 322. In some embodiments, the isolation structures 334, 336 are formed as part of a common doping well in the semiconductor substrate 322, which is coupled to a ground reference voltage and has a dopant concentration/dosage at least as high as the semiconductor substrate 322, for example, doped with a dopant having a dose on the order of about E12/ ^cm2 .

In some embodiments, the isolation structures 334, 336 are formed in a grid-like interconnect trench structure. In some embodiments, the isolation structures 334, 336 are formed by a backside deep trench isolation structure extending from a backside 340 of the semiconductor substrate 322 toward a front side 338 opposite the backside 340, thereby providing electrical and optical isolation between the photodiode 324 and neighboring photodiodes. In the illustrated embodiment, the isolation structures 334, 336 extend completely from the backside 340 of the semiconductor substrate 322 toward the front side 338, thereby providing complete electrical isolation between the photodiode 324 and neighboring photodiodes within the semiconductor substrate 322. However, it should be understood that in some embodiments, each of the isolation structures 334, 336 partially extends from the back side 340 of the semiconductor substrate 322 toward the front side 338, such that a substrate region remains between each of the isolation structures 334, 336 and the front side 338 of the semiconductor substrate 322. In some embodiments, each of the isolation structures 334, 336 includes a backside deep trench isolation structure at least partially formed in the implant-doped well region.

The transmission structure 350 includes a vertical channel structure 352 and a transmission gate 354. In some embodiments, the transmission gate 354 is similar to the transmission gate 254 in that it is a planar gate electrode formed on the semiconductor substrate 322. The transmission gate 354 may also be referred to as a planar transmission gate 354 and may be used interchangeably. In some embodiments, the transmission structure 350 includes the vertical channel structure 352 but does not include the transmission gate 354. The vertical channel structure 352 is a series of PN junctions extending vertically into the semiconductor substrate 322, which can be biased to selectively form a channel that carries charge carriers from the photodiode 324 to the floating diffusion region 326. A planar transfer gate 354 is formed on the front side 338 of the semiconductor substrate 322 (see FIG. 3B ), is operably coupled to the vertical channel structure 352, and can be biased (alone or in combination with the vertical channel structure 352) to selectively transfer charge carriers from the photodiode 324 to the floating diffusion region 326 (see FIG. 3B ). The features are described below.

Still referring to FIG3A, the vertical channel structure 352 includes a plurality of spaced apart P-type doped regions 356, 358 formed in the semiconductor substrate 322 and within an N-type doped region 360, which is itself formed in the semiconductor substrate 322. As shown in FIG3B and FIG3C, the P-type doped regions 356, 358 are disposed between the photodiode 324 and the transfer gate 354 and between the photodiode 324 and the floating diffusion region 326. In some embodiments, the plurality of spaced apart P-type doped regions 356, 358 include or consist of two such regions to completely deplete the N-type doped region 360 during an integration period; however, other embodiments include a greater number of spaced apart regions, such as three, four, or five. In some embodiments, the P-type doped regions 356, 358 are parallel to each other, for example, at least in a horizontal direction parallel to the front side 338 of the semiconductor substrate 322 and in a vertical direction, for example, in a vertical plane normal to the front side 338 of the semiconductor substrate 322.

Unlike a known vertical transfer gate that includes a pillar or monolithic gate having conductive gate material extending vertically into the semiconductor substrate (e.g., into an etched trench, pillar, or other void), the vertical channel structure 352 does not include any conductive gate material extending into the semiconductor substrate 322 (although there are contacts 368, 370, which may only extend slightly into the semiconductor substrate 322). This also applies to the planar transfer gate 354 (see FIG. 3B) operably coupled between the vertical channel structure 352 and the floating diffusion region 326.

Instead of vertical conductive gate material extending into the semiconductor substrate 322, the vertical channel structure 352 of the present invention utilizes implanted and doped PN junctions to regulate the movement of charge carriers between the photodiode 324 and the floating diffusion region 326. That is, the vertical channel structure 352 includes a plurality of spaced apart P-type doped regions 356, 358 extending vertically into the semiconductor substrate 322 and formed within an N-type doped region 360. To reiterate, the vertical channel structure 352 includes a plurality of PN junctions formed by the N-type doped region 360 between the P-type doped regions 356, 358 and the semiconductor substrate 322. These junctions form a selective carrier channel and eliminate the need for a conventional vertical transfer gate. Advantageously, it is not necessary to etch any pillars, columns or monolithic trenches in the semiconductor substrate 322 that would cause etching damage to the lattice structure of the semiconductor substrate 322, thereby creating defects and trap sites that form dark current sources. Thus, etching damage typically associated with vertical transfer gates can be avoided and white pixel effects caused by such structures can be reduced, while allowing the photodiode 324 to be formed deep in the semiconductor substrate 322 away from the front surface 338, thereby suppressing white pixel problems caused by surface defects and maximizing the full well capacity of the photodiode 324 within the available area of the pixel 320.

Each P-type doped region 356, 358 may be formed by implanting a P-type implant (e.g., boron) into the semiconductor substrate 322 at two or more locations within the N-type doped region 360. The P-type doped regions 356, 358 may be spaced apart laterally by about 0.1 um to about 0.5 um, such as about 0.2 um, about 0.3 um, or about 0.4 um. It should be understood that in any embodiment, the spacing between the P-type doped regions 356, 358 may be less than or equal to 0.5 um, such as to completely deplete the portion of the N-type doped region 360 disposed between the P-type doped regions. In addition, each P-type doping region 356, 358 has a P-type doping concentration that is higher than the PD doping concentration of the photodiode doping region of the photodiode 324 and higher than the doping concentration of the N-type doping region 360, so that the N-type doping region 360 can be completely depleted, for example, during the integration cycle of the image sensor. The P-type doping concentration of each P-type doping region 356, 358 is lower than the concentration of the floating diffusion region 326. Although the P-type dopant concentration/dosage may vary between embodiments, in some embodiments, the P-type dopant has a dopant having a dosage of about E13/ ^cm2 to about E14/ ^cm2 .

Each P-type doped region 356, 358 extends from the front side 338 of the semiconductor substrate 322 to a junction depth _Djl of about 250 nm to about 800 nm in the semiconductor substrate 322 and has a width of about 0.1 um to about 0.5 um. Accordingly, the P-type doped regions 356, 358 are formed between the photodiode 324 and the floating diffusion region 326 and extend vertically into the semiconductor substrate 322 toward the photodiode 324. However, the P-type doped regions 356, 358 terminate above the photodiode 324 so that there is no direct contact between the photodiode 324 and the P-type doped regions 356, 358. To reiterate, in some embodiments, a distal end 357 of each of the spaced apart P-type doped regions 356, 358 is spaced apart from the photodiode 324. The plurality of P-type doped regions 356, 358 are spaced apart from each other by about 0.1 um to about 0.5 um.

The N-type doped region 360 surrounds each of the P-type doped regions 356, 358 and is between the P-type doped regions 356, 358 to create a PN junction between the P-type semiconductor substrate 322 and the P-type doped regions 356, 358. To reiterate, the N-type doped region 360 has the P-type doped regions 356, 358 formed completely inside, which prevents contact between the P-type doped regions 356, 358 and the semiconductor substrate 322, thereby avoiding a short circuit. Accordingly, the N-type doped region 360 is implanted and formed below the surface of the front side 338 of the semiconductor substrate 322 and between the photodiode 324 and the floating diffusion region 326. An N-type doped region 360 is further formed between the photodiode 324 and the transfer gate 354. The N-type doped region 360 vertically extends from the front side 338 of the semiconductor substrate 322 to a junction depth D _j2 that is greater than the junction depth D _j1 to which the P-type doped regions 356 and 358 extend relative to the front side 338. In some embodiments, the _N -type doped region 360 spans the distance between the photodiode 324 and the transfer gate 354. In some embodiments, the junction depth D _j2 of the N-type doped region 360 relative to the front side surface 338 is in the range of about 300 nm to about 1000 nm. In some embodiments, a distance from a junction edge of the N-type doped region 360 to each of the P-type doped regions 356, 358 (i.e., the difference between _Dj1 and _Dj2 ) is about 0.1 um to about 0.5 um. The N-type doped region 360 may be aligned with an edge of the pass gate 354 near the N-type doped region 360. In one embodiment, the pass gate 354 overlaps a portion of the N-type doped region 360.

The N-type dopant region 360 may be formed by implanting an N-type implant (eg, phosphorus or arsenic) at an N-type dopant concentration that is lower than the P-type dopant concentration of the P-type dopant regions 356 , 358 but higher than the PD dopant concentration of the photodiode 324 . Thus, the N-type doped region 360 can be completely depleted when the P-type doped regions 356, 358 are negatively biased during the integration period, and has a potential lower than the potential of the photodiode 324 but higher than the potential of the floating diffusion region 326, thereby forming a charge carrier channel. During the charge transfer period, when the transfer gate 354 is biased to be turned on and the P-type doped regions 356, 358 are biased with a zero bias voltage or a certain voltage, the charge carrier channel allows the flow of photogenerated charges. Although the N-type dopant concentration/dosage may vary between embodiments, in some embodiments, the N-type dopant dosage used to dope the P-type doping regions 356, 358 is about E12/ ^cm2 to about E13/ ^cm2 . It should be understood that the bias voltage, the dopant concentration of the P-type doping regions 356, 358 and the N-type doping region 360, and the width of the N-type doping region 360 can be configured based on the desired halo performance and transmission efficiency.

3B and 3C , unlike the P-type doped regions 356, 358 (which do not extend too deep to make contact with the photodiode 324), the N-type doped region 360 extends vertically from the front side 338 of the semiconductor substrate 322 to a depth sufficient to make contact with the photodiode 324. This enables charge carriers to be transferred from the photodiode 324 to the N-type doped region 360 in a particular mode of operation described below.

3A , a charge carrier channel region or channel region 362 of the N-type doped region 360 is disposed between the P-type doped regions 356, 358. During a particular operating state (e.g., an integration cycle), when the transfer gate 354 is turned off (e.g., by a cutoff signal), the P-type doped regions 356, 358 are biased (e.g., with a negative voltage) to deplete free charge carriers from the channel region 362 of the N-type doped region 360, thereby preventing charge carrier transfer from the photodiode 324. In some embodiments, the P-type doped regions 356, 358 are biased simultaneously after the transfer gate 354 is turned off. However, when the transfer gate 354 is turned on (e.g., during a charge transfer cycle), the P-type doped regions 356, 358 are zero biased or grounded so that the channel region 362 is no longer depleted of free charge carriers, and the charge carriers can pass from the photodiode 324, for example, along a transfer path 363 through the channel region 362 of the N-type doped region 360, a channel region of the transfer gate 354, and to the floating diffusion region 326, wherein the channel region of the transfer gate 354 is coupled to the channel region 362 and is close to the transfer gate 354 in the semiconductor substrate 322. In some embodiments, the channel region of the transfer gate 354 is connected in series with the channel region 362 between the photodiode 324 and the floating diffusion region 326. In some embodiments, the channel region 362 of the N-type doped region 360 extends laterally from one of the P-type doped regions 356 to the other P-type doped region 358. In some embodiments, the channel region 362 has a width between the P-type doped regions 356, 358 of about 0.1 um to about 1.0 um, such as about 0.2 um, about 0.3 um, about 0.4 um, about 0.5 um, about 0.6 um, about 0.7 um, about 0.8 um, or about 0.9 um.

Contact regions 364, 366 are formed within each of the P-type doped regions 356, 358. The contact regions 364, 366 of the P-type doped regions 356, 358 are connected to conductive traces (or contacts) 368, 370 (respectively), which are adjacent to the front side 338, which in turn are electrically connected to a common metal interconnect 372. The metal interconnect 372 can be part of a first metal layer and is operably coupled to a control circuit (e.g., control circuit 108) of the image sensor through one or more metal interconnects. Conductive traces 368, 370 and metal interconnect 372 may be embedded in a dielectric material layer so that metal interconnect 372 is electrically isolated from contacts and metal interconnect structures that connect transfer gate 354 to the control circuitry of the image sensor. Contact regions 364, 366 are P-type doped regions having a P-type dopant concentration\dosage higher than the remainder of P-type doped regions 356, 358. For example, in some embodiments in which the P-type doping regions 356, 358 may be doped with a P-type dopant amount of about E13 to about E14/ ^cm2 , the contact regions 364, 366 may be doped with a larger P-type dopant amount, such as a dopant amount greater than about E14/ ^cm2 .

Metal interconnect 372 may be electrically biased by the control circuitry of the image sensor or pixel to deplete the free charge carriers of N-type doping region 360. The bias voltage may vary depending on the P-type dopant concentration, the N-type dopant concentration, and other sensor operating parameters such as the desired halo level. However, representative bias voltages of the P-type doped regions 356, 358 may be in a range from about -2.0 V to about -0.5 V, about -1.9 V to about -0.6 V, about -1.8 V to about -0.7 V, about -1.7 V to about -0.8 V, about -1.6 V to about -0.9 V, about -1.5 V to about -1.0 V, about -2.0 V to about -1.0 V, about -2.0 V to about -1.5 V, about -1.5 V to about -0.5 V, or about -1.5 V to about -1.0 V.

Turning to Figure 3B, a planar transmission gate 354 formed on the front side 338 of the semiconductor substrate 322 can be biased to form a channel between the channel region 362 and the floating diffusion region 326 in the semiconductor substrate 322 near the surface of the front side 338, so that the channel of the planar transmission gate 354 is coupled in series to the channel region 362 and the electric carriers are transferred from the channel region 362 of the vertical channel structure 352 to the floating diffusion region 326 through the channel of the planar transmission gate 354.

The transfer gate 354 includes a metal or polysilicon gate portion formed on an isolation layer 374 deposited on the front side 338 of the semiconductor substrate 322. The isolation layer 374 _is formed of a dielectric material, such as silicon oxide or a high-k material, such as a material having a dielectric constant greater than about 3.9 (e.g., _Al2O3 or _HfO2 ). In some embodiments, the isolation layer 374 has a thickness of about 30 Å to about 100 Å.

In some embodiments, the transfer gate 354 includes an optional spacer 376 disposed around the gate portion. In some embodiments, the spacer 376 substantially surrounds the gate portion. In some embodiments, the spacer 376 is formed of a dielectric material similar to the isolation layer 374. The spacer 376 can be a single layer or a multi-layer stacked structure formed of oxide, nitride, or a combination thereof.

In some embodiments, the photodiode doping region of the photodiode 324 has the same conductivity type as the N-type doping region 360, and when viewed in a cross-section perpendicular to the front surface 338 of the semiconductor substrate and perpendicular to a plane bisecting the plurality of spaced first doping regions 356, 358 (such as the plane of FIG. 3B), the photodiode doping region includes an upper portion 325a and a lower portion 325b adjacent to and extending from the upper portion. The lower portion 325b has a first implantation depth relative to the front side 338 that is deeper than the upper portion 325a. In some embodiments, an upper portion 325a of the photodiode doping region of the photodiode 324 adjacent to the transmission structure 350 has a dopant concentration that is higher than a lower portion 325b of the photodiode doping region of the photodiode 324 adjacent to the back side 340 of the semiconductor substrate 322. In some embodiments, the photodiode doping region of the photodiode 324 has a gradient doping profile that varies along the depth in the semiconductor substrate 322. The upper portion 325a is adjacent to and in contact with the N-type doping region 360. The lower portion 325b is formed below the vertical channel structure 352 and is vertically separated from the N-type doped region 360. In some embodiments, the upper portion 325a of the photodiode doped region overlaps a portion of the N-type doped region 360 in a vertical direction so that during a charge transfer cycle, charge can enter the charge carrier channel 362 of the transfer structure 350 from the upper portion 325a of the photodiode doped region to the floating diffusion region 326. In some embodiments, no portion of the photodiode 324 contacts the P-type doped region 356 or 358. In some embodiments, the lower portion of the photodiode 324 extends under the transfer gate 354.

Turning briefly to FIG. 3C , the transmission gate 354 is electrically connected to a metal interconnect 380 via a contact 378. The metal interconnect 380 may be part of the first metal layer and electrically isolated from the metal interconnect 372. The metal interconnect 380 and the metal interconnect 372 may be located in the same or different metal layers depending on the wiring layout. The metal interconnect 380 is operably coupled to the control circuitry of the image sensor through one or more metal interconnect structures to selectively bias the transmission gate 354 to be turned on or off depending on the received transmission signal or the disconnect signal. Accordingly, the transmission gate 354 can be biased separately from the transmission structure 350.

Returning to FIG. 3B , floating diffusion region 326 is formed as an N-type dopant region adjacent to pass gate 354. Floating diffusion region 326 is doped with an N-type dopant having a FD dopant concentration/dosage greater than the N-type dopant concentration/dosage of N-type dopant region 360. Although the FD dopant concentration/dosage may vary between embodiments, in some embodiments, the FD dopant dosage is about E15/cm ² . Floating diffusion region 326 is in electrical communication with a metal interconnect 344 (via a contact 342 ). Metal interconnect 344 may be part of the first metal layer and electrically isolated from metal interconnect 372 and metal interconnect 380. Metal interconnect 344 is coupled to a gate of a source follower transistor (e.g., gate SF of source follower transistor 230) that modulates image signal readout based on the voltage received from floating diffusion region 326.

As noted above, the relative dopant concentrations/dopings of the photodiode doping region of the photodiode 324, the P-type doping regions 356, 358, and the N-type doping region 360 enable successful operation of the transmission structure 350. In some embodiments, the PD dopant concentration/dosage of the photodiode doping region of the photodiode 324 is less than both the N-type dopant concentration/dosage of the N-type dopant region 360 and the P-type dopant concentration/dosage of the P-type dopant regions 356 and 358, and the N-type dopant concentration/dosage of the N-type dopant region 360 is less than the P-type dopant concentration/dosage of the P-type dopant regions 356 and 358 and less than the FD dopant concentration/dosage of the floating diffusion region 326. In one such representative embodiment, the PD dopant amount is about E11/ ^cm2 -E12/ ^cm2 (e.g., E12/ ^cm2 ), the N-type dopant amount of the N-type dopant region 360 is about E12/ ^cm2 to about E13/ ^cm2 (e.g., about E13/ ^cm2 ), the P-type dopant amount of the P-type dopant regions 356 and 358 is about E13/ ^cm2 to about E14/ ^cm2 (e.g., about E14/ ^cm2 ), and the FD dopant amount of the floating diffusion region 326 is at least about E14/ ^cm2 (e.g., about E15/ ^cm2 ).

3B and 3C together, the operation of the transmission structure 350 will now be described.

During an integration cycle of pixel 320, photodiode 324 accumulates charge carriers in its charge accumulation region in response to the amount of incident light absorbed, and vertical channel structure 352 and transfer gate 354 are biased by a control circuit (e.g., control circuit 108 of FIG. 1 ) so that approximately all charge carriers cannot move from photodiode 324 through the channel region of transfer structure 350. In an embodiment, the control circuit biases the P-type doped regions 356, 358 to a bias voltage sufficient to completely deplete free charge carriers in the channel region 362 of the N-type doped region 360 (i.e., a region disposed between the P-type doped regions 356, 358) via the metal interconnect 372 and the contacts 368, 370. For example, in some embodiments, the control circuit (e.g., the control circuit 108 of FIG. 1) outputs a bias voltage of about -2.0 V to about -1 V to the P-type doped regions 356, 358. The depleted N-type dopant region 360 is promoted by a higher P-type dopant concentration/dosage of the P-type dopant regions 356, 358 relative to the N-type dopant region 360. Due to the higher N-type dopant concentration/dosage of the N-type dopant region 360 relative to the photodiode 324, the potential of the N-type dopant region 360 will be reduced to a level lower than a potential of the photodiode 324 and prevent charge carriers from passing through the vertical channel structure 352 from the photodiode 324. Also during the integration period, the control circuit can also negatively bias (e.g., about -0.5 V to about -2 V) the transfer gate 354 via the metal interconnect 380 and the contact 378 to reduce the potential of the channel region associated with the transfer gate 354 to a level lower than the potential of the N-type doped region 360, thereby preventing the transfer of charge carriers from the vertical channel structure 352 to the floating diffusion region 326, and further induce a hole-rich region to passivate the surface region under the transfer gate 354, thereby reducing dark current. In some embodiments, during an integration period, the control circuit may further adjust the bias voltage applied to the P-type doped regions 356, 358 to tune the potential of the channel region 362 associated with the N-type doped region 360 to achieve a halo path between the photodiode 324 and the floating diffusion region 326, so that: (i) one or more excess photogenerated electrons can leak through the N-type doped region 360 to the floating diffusion region 326 to prevent the photodiode 324 from being saturated; and (ii) excessive photogenerated electrons are prevented from leaking to a neighboring photodiode 324 to cause crosstalk. It should be understood that the bias voltage applied to the P-type doped regions 356 and 358 can be configured to balance the halo efficiency and the full well capacity of the photodiode 324. This is because if the bias voltage applied to the P-type doped regions 356 and 358 is not negative enough, more accumulated photogenerated charge will leak from the photodiode 324 to the floating diffusion region 326, thereby affecting the full well capacity of the photodiode 324.

During a transmission cycle of the pixel 320, the control circuit turns on both the transmission structure 350 and the transmission gate 354, that is, the control circuit controls the transmission structure 350 to form a charge carrier channel between the P-type doped regions 356 and 358. Specifically, the control circuit outputs a zero bias voltage to the metal interconnect 372 to the P-type doped regions 356 and 358 so that the N-type doped region 360 allows charges to flow through the channel region 362. The zero bias doped regions 356 and 358 then increase the potential of the N-type doped region 360 to a level higher than the potential of the photodiode 324. Subsequently or substantially simultaneously, the control circuit forward biases the transfer gate 354 to generate a charge carrier channel having a potential equal to or higher than the potential of the N-type doped region 360 in the semiconductor substrate 322 below the transfer gate 354, and the transfer gate 354 is electrically coupled to the N-type doped region 360. This enables charge carriers to pass from the photodiode 324 through the charge carrier channel region 362 formed by the vertical channel structure 352 (the charge carrier channel region is formed below the transfer gate 354), and to the floating diffusion region 326.

In different embodiments, different dopant concentrations and bias voltages may be adjusted to modulate halo and charge transfer efficiency depending on the application. However, the relative dopant concentrations between different elements of a pixel are constant between the embodiments discussed above. Accordingly, the dopant concentrations and bias voltages provided herein are representative and non-limiting.

Thus, the transfer structure 350 enables selective transfer of charge carriers from the photodiode 324 to the floating diffusion region 326. Advantageously, because the transfer structure 350 lacks any etched trench structures in the semiconductor substrate 322, it does not create surface defects on the semiconductor substrate 322. This avoids white pixels and other deleterious effects associated with known vertical transfer gates. For clarity, in any of the embodiments described herein, the transfer gate and vertical channel structure do not include any conductive gate material extending into the semiconductor substrate 322, despite traces and/or contacts.

The above description of the illustrated examples of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the present invention to the precise forms disclosed. Although specific examples of the present invention are described herein for illustrative purposes, those skilled in the art will recognize that various modifications are possible within the scope of the present invention.

Such modifications may be made to the present invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the present invention to the specific examples disclosed in this specification. Instead, the scope of the present invention shall be determined entirely by the following claims, which shall be interpreted in accordance with established principles of claim interpretation.

100: Image sensor 102: Pixel array 104: Readout circuit system 106: Functional logic 108: Control circuit 120: Pixel 220: Pixel 222: Semiconductor substrate 224: Photodiode 226: Floating diffusion region 227a: Boundary 227b: Boundary 228: Reset transistor 230: Source follower transistor 232: Column select transistor 234: Channel isolation structure 236: Channel isolation structure 250: Transmission structure 252: Vertical channel structure 254: Transmission gate 320: Pixel 322: Semiconductor substrate 324: Photodiode 325a: Upper portion 325b: Lower portion 326: Floating diffusion region 334: Isolation Structure 336: Isolation structure 338: Front side/front surface/front surface 340: Back side 342: Contact 344: Metal interconnect 350: Transmission structure 352: Vertical channel structure 354: Transmission gate 356: P-type doped region/first doped region 357: Far end 358: P-type doped region/first doped region 360: N Type doped region 362: carrier channel region or channel region/carrier channel 363: transmission path 364: contact region 366: contact region 368: contact/conductive trace 370: contact/conductive trace 372: metal interconnect 374: isolation layer 376: spacer 378: contact 380: metal interconnect D _j1 : junction depth D _j2 : junction depth

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

FIG. 1 is a block diagram illustrating an embodiment of an image sensor according to the teachings of the present invention.

FIG. 2 is a diagrammatic layout of a representative pixel embodying a transmission structure according to the teachings of the present invention.

3A is a first cross-sectional view of a portion of a pixel taken along a cross-sectional line equivalent to line AA′ shown in FIG. 2 embodying a transmission structure according to the teachings of the present invention.

3B is a second cross-sectional view of the pixel of FIG. 3A taken along a cross-sectional line equivalent to line BB′ shown in FIG. 2 .

3C is a third cross-sectional view of the pixel of FIG. 3A taken along a cross-sectional line equivalent to line CC′ shown in FIG. 2 .

Throughout the several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the drawings are depicted for simplicity and clarity and are not necessarily drawn to scale. For example, the size of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the various embodiments of the invention. In addition, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are generally not depicted in order to facilitate a clearer viewing of one of the various embodiments of the invention.

320: pixels

322:Semiconductor substrate

324: Photodiode

334: Isolation structure

336: Isolation structure

338: front side/front side surface/front surface

340: Dorsal side

350: Transmission structure

352: Vertical channel structure

356: P-type doping region/first doping region

357: Remote

358: P-type doping region/first doping region

360: N-type doping area

362: Charge carrier channel region or channel region/charge carrier channel

364:Contact area

366:Contact area

368: Contacts/conductive traces

370: Contacts/conductive traces

372:Metal interconnects

D _j1 : junction depth

D _j2 : junction depth

Claims (16)

A pixel includes: a photodiode formed in a semiconductor substrate and having a photodiode doping region with a PD dopant concentration, wherein the photodiode has a first conductivity type, wherein the semiconductor substrate has a second conductivity type opposite to the first conductivity type; a floating diffusion region formed in the semiconductor substrate and having an FD dopant concentration of the first conductivity type, wherein the FD dopant concentration is higher than the PD dopant concentration; and a transmission structure that selectively couples the photodiode to the floating diffusion region, wherein the transmission structure includes: a transmission a transmission gate formed on the semiconductor substrate; and a vertical channel structure including spaced first doped regions formed in the semiconductor substrate between the transmission gate and the photodiode, wherein each of the spaced first doped regions is doped with a first type dopant of the second conductivity type at a first dopant concentration. Dopant, wherein the spaced-apart first doping regions are formed in a second doping region doped with a second type dopant of the first conductivity type at a second dopant concentration, wherein the second dopant concentration is greater than the PD dopant concentration, less than the first dopant concentration, and less than the FD dopant concentration. A pixel as in claim 1, wherein the second doped region surrounds the spaced first doped regions. A pixel as claimed in claim 1, wherein each of the spaced-apart first doped regions extends vertically from a front surface of the semiconductor substrate into the semiconductor substrate, wherein a distal end of each spaced-apart first doped region is spaced apart from the photodiode. A pixel as claimed in claim 3, wherein the second doped region extends vertically from the front surface of the semiconductor substrate into the semiconductor substrate and overlaps with the photodiode. A pixel as claimed in claim 1, wherein in a cross-section perpendicular to a front surface of the semiconductor substrate and perpendicular to a plane bisecting the spaced first doped regions, the photodiode doped region of the photodiode comprises: an upper portion adjacent to a distal end of the second doped region; and a lower portion adjacent to and extending from the upper portion; wherein the upper portion contacts the second doped region. A pixel as in claim 1, wherein the first doped regions spaced apart are parallel to each other. A pixel as claimed in claim 6, wherein the first doped regions spaced apart are spaced apart by about 0.1um to about 0.5um. A pixel as claimed in claim 1, wherein the transmission structure further comprises a conductive contact electrically connected to each of the spaced-apart first doped regions at a surface of the semiconductor substrate. A pixel as in claim 8, wherein each of the spaced-apart first doping regions has a contact region disposed adjacent to the surface of the semiconductor substrate and having a contact dopant concentration, wherein the contact dopant concentration is greater than the first dopant concentration of the spaced-apart first doping regions. A pixel as claimed in claim 8, wherein the contact is electrically connected to each of the first doped regions separated from each other via a plurality of conductive contacts. A pixel as claimed in claim 8, wherein the transmission structure further includes a second contact electrically connected to the transmission gate. A pixel as claimed in claim 1, wherein the transmission gate is a planar transmission gate disposed on a surface of the semiconductor substrate, wherein the transmission gate is selectively coupled to the photodiode and to the floating diffusion region through the second doped region. A pixel as claimed in claim 1, wherein the transfer gate and the vertical channel structure do not include any conductive gate material extending into the semiconductor substrate. An image sensor comprising: a plurality of pixels as claimed in claim 1, wherein each pixel is separated from neighboring pixels of the plurality of pixels by an isolation structure formed in the semiconductor substrate; and a control circuit operably coupled to each pixel of the plurality of pixels, the control circuit being configured to control the plurality of pixels. An image sensor as claimed in claim 14, wherein the control circuit includes logic configured to perform the following operations for each pixel: Applying a cutoff signal to turn off the transmission gate during an integration cycle; and negatively biasing the spaced first doped regions when the transmission gate is turned off, thereby completely depleting free charge carriers in a channel region of the second doped region disposed between the spaced first doped regions during the integration cycle. An image sensor as claimed in claim 15, wherein the control circuit further includes logic configured to perform the following operations for each pixel: applying a transfer signal to turn on the transfer gate during an exposure period; and grounding the plurality of spaced-apart first doped regions when the transfer gate is turned on, thereby transferring electric carriers from the photodiode to the floating diffusion region through the transfer gate during the exposure period.