TWI859909B - Computer system based on wafer-on-wafer architecture and memory test method - Google Patents

Abstract

A memory test method for computer systems based on wafer-on-wafer architecture. The computer system is a three-dimensional wafer product formed by a memory wafer layer, a logic circuit layer and a substrate. When a memory test is performed, a memory device in the memory wafer layer is divided into a plurality of memory sub blocks with the same size. First, a same data table is created in at least two memory sub blocks. Then, a plurality of different initial values prepared in advance are provided for a workload proof operation that executed at the at least two memory sub blocks at same time, and the data tables of the at least two memory sub blocks are repetitively read and written for plural times to produce multiple operation results corresponding to each initial value. When the verification module obtains operation results from the arithmetic module, the operation results are compares with corresponding known answers, and the error rate of each of the at least two memory sub blocks under test is therefore estimated.

Description

Computer system and memory test method based on wafer stacking architecture

The present application relates to a method for testing a memory device, and more particularly to a method for testing a memory in a computer system implemented using wafer stacking technology.

In this era, the application of artificial intelligence and blockchain has become a new business opportunity. Blockchain can be widely used in applications such as smart contracts, digital identities, and shared economy.

However, some blockchain platforms often change the blockchain algorithm for various security considerations or vulnerability repairs. In addition to increasing the difficulty of calculations, they often deliberately make special designs to reduce the computing efficiency of specific application chips, such as increasing the requirements for memory throughput or the capacity of storage devices.

Therefore, for blockchain server developers, they must also change the hardware architecture to adapt to the high standard requirements for memory throughput. Therefore, a completely new hardware architecture for blockchain servers needs to be developed. In addition, the memory control method and memory testing method applicable to the new hardware architecture need to have corresponding improvement mechanisms.

Traditional memory testing methods require a dedicated test module to be configured inside the chip in order to test the memory. In a computer system based on a wafer stacking architecture, testing all memory units may take a huge amount of time. Therefore, the present application embodiment proposes a computer system based on a wafer stacking architecture and a memory testing method thereof, which utilizes the native algorithm in the computer system with different initial values and known solutions, and quickly judges the availability of the memory device based on the calculation results of the initial values and the known solutions, thereby achieving the purpose of improving testing efficiency.

In order to achieve the above-mentioned purpose, the present application proposes a memory testing method, which is applicable to a computer system based on a wafer stacking architecture. The so-called wafer stacking architecture is a wafer stack formed by a memory crystal layer, a logic circuit layer and a substrate using WoW (Wafer on Wafer) technology. The memory crystal layer includes at least one memory device. The logic circuit layer is connected to the at least one memory device through a plurality of connection pads, and includes a firmware, a computing module connecting the firmware and the at least one memory device, and a judgment module connecting the computing module.

When performing a memory test, the at least one memory device is basically divided into a plurality of memory sub-blocks for testing. First, the same data table is established in at least two of the plurality of memory sub-blocks. Then, a plurality of different pre-prepared initial values and a known solution corresponding to each initial value are provided. Each initial value is a value required by the operation module for performing a proof-of-work operation. The proof-of-work operation can read and write the data table of the at least two memory sub-blocks multiple times to generate a plurality of operation results corresponding to each initial value. After the judgment module obtains the operation results from the operation module and compares them with the corresponding known solutions, the error rate of the tested memory sub-block can be statistically calculated.

In a further embodiment, the determination module compares the error rate of the memory sub-block with a critical value to determine whether the availability of the memory sub-block is available or unavailable. Afterwards, the determination module records the number of the tested memory sub-block in the firmware according to the determination result of the availability.

In a specific embodiment, the proof-of-work operation can be an Ethereum hashing algorithm (Ethash). The data table is a directed acyclic graph (DAG).

In order to fully test the memory units in each memory sub-block, a directed acyclic graph with a size consistent with the memory sub-block can be generated in the memory sub-block through program-controlled configuration of the computing module.

In a further embodiment, the pre-prepared initial value and the corresponding known solution can be pre-stored in the firmware when leaving the factory, or can be a value input from the outside in real time. When testing, the judgment module obtains the known solution from the firmware or the outside and compares it with the test result.

In order to achieve the above objectives, the present application also proposes an embodiment of the computer system based on the wafer stacking architecture.

In summary, the computer system and memory testing method proposed in the embodiment of the present application are applicable to computer systems with wafer stacking architecture. The native algorithm in the computing module is used in combination with different initial values and known solutions to execute the test program on more than two memory sub-blocks at the same time, so as to judge the availability of the memory sub-blocks according to the computing results of the computing module. This method does not require the design of additional test logic in the computer system, which effectively simplifies the complexity of the computer system, and by testing multiple memory sub-blocks at the same time, the test efficiency of the memory device is also improved exponentially.

FIG1 is a schematic diagram of a wafer stacking structure of a three-dimensional wafer product 100 according to an embodiment of the present application. The three-dimensional wafer product 100 is stacked layer by layer with at least one memory crystal layer 110, a logic circuit layer 120, and a substrate 130. A plurality of memory devices 112 are arranged in the memory crystal layer 110. The memory device 112 can be a memory module composed of memory particles, such as a dynamic random access memory (DRAM). The logic circuit layer 120 is a wafer layer in which a plurality of logic circuits 122 are arranged. The logic circuits 122 are a generic term for various chip modules, such as, but not limited to, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), memory controllers, or processors. The bottommost substrate 130 not only provides basic support, but also provides additional wiring space. Multiple connection pads 102 or 104 are configured between each layer to provide signal channels. The three-dimensional wafer product 100 of this embodiment is a semi-finished product of a computer system 200, and after cutting, multiple independently operating computer systems 200 can be produced. Although only one substrate 130 is shown in Figure 1, it is not limited to this in the physical design, and multiple substrates 130 can also be arranged in parallel. In one embodiment, each computer system 200 may include a plurality of memory devices 112 and a plurality of logic circuits 122, and have the same three-dimensional wafer structure. In other words, the memory devices 112 and logic circuits 122 included in each computer system 200 are pre-arranged in the memory crystal layer 110 and the logic circuit layer 120, respectively, and then manufactured in the form of wafer stacking to form a three-dimensional structure. In the three-dimensional structure, the circuit wires between the chipsets do not need to occupy extra area, and the connection pads 102 and 104 can be directly used as the path for signal transmission, so that the performance problem of data transmission is effectively solved to realize the computer system 200 of the present application.

In the wafer stacking architecture of Figure 1, since the number of transmission lines is no longer limited by the planar design, a large number of dedicated wiring can be used to solve the performance problem of data transmission. The spacing between the memory crystal layer 110 and the logic circuit layer 120 becomes smaller, so more interfaces can be laid out in the same area. The bandwidth is obtained by multiplying the number of interfaces by the frequency formula of the channel, so more interfaces can get higher bandwidth. Thanks to wafer stacking technology, applications that require a large amount of memory access, such as machine learning, artificial intelligence or blockchain applications, can achieve exponential performance improvements.

FIG2 is a computer system 200 of an embodiment of the present application. The computer system 200 is a product formed by stacking and then cutting the memory crystal layer 110, the logic circuit layer 120 and the substrate 130 in FIG1. The computer system 200 may include one or more memory devices 210 cut out of the memory crystal layer 110, and multiple chips cut out of the logic circuit layer 120, such as firmware 202, computing module 204 and judgment module 206. The computing module 204 may include the function of a memory controller, and the memory device 210 is connected through the multiple connection pads 102 shown in FIG1. For example, the memory device 210 may include a plurality of memory banks, each of which includes a plurality of memory cells (not shown). Each memory cell is used to store bit data 0 or 1. Each row or column of memory cells may be connected to the computing module 204 via a plurality of corresponding connection pads 102. There are known standard specifications for the internal circuits of the memory, so the detailed implementation will not be repeated.

Generally speaking, the common memory test method is to build the memory test logic into the chip. For example, when the computing module 204 receives a command to execute a test, it will automatically test the memory device. This method is called a built-in self-test module (Build-In-Self-Test; BIST). However, as the number of memory devices gradually increases, the time required to execute a complete BIST (including the time to execute the test and the time required to read the results) will also increase, and this point has a great impact on the wafer stacking architecture.

In the embodiment proposed in the present application, the memory block in the memory device 210 is first divided into a plurality of memory sub-blocks 212, and then the computing module 204 executes the native function of the computing module 204 on at least two memory sub-blocks 212 at the same time, so as to quickly estimate the data error rate of all memory sub-blocks 212. In this embodiment, the native function of the computing module 204 can be a proof-of-work algorithm. In this embodiment, if the data error rate of a memory sub-block 212 is greater than a critical value, the memory sub-block 212 is marked as an unavailable block. In contrast, if the data error rate of the memory sub-block 212 is less than the critical value, the memory sub-block 212 is marked as an available block. After the memory test is completed, the information of the available block can be stored in the firmware 202 to facilitate subsequent applications of the computer system 200.

3 , in this embodiment, the operation module 204 may further define a plurality of sub-operation modules 2041, and each sub-operation module 2041 may execute the native function of the operation module 204 on different memory sub-blocks 212 to quickly estimate the data error rates of the plurality of memory sub-blocks 212. In one embodiment, the number of sub-operation modules 2041 may be the same as or different from the number of memory sub-blocks 212, and the present application is not limited thereto.

The above-mentioned proof-of-work algorithm is a block-solving algorithm based on a hash function. Input any initial value, and after passing through the hash function, a corresponding result will be obtained. As long as the initial value changes by one bit, it will cause an avalanche effect, so it is almost impossible to reverse. Therefore, by looking for calculation results with specified characteristics, users can perform a large number of exhaustive calculations to achieve proof of work. Common proof-of-work algorithms include SHA-256, Ethash, Scrypt, Equihash, CryptoNode, or algorithms based on Memory Hard Function. The following only uses Ethash as an example, and the detailed operation details of other algorithms will not be repeated.

Ethereum Hash (Ethash) is a proof-of-work algorithm modified from the Dagger-Hashimoto algorithm. The main principle is to increase the memory load through a large number of random table lookups to counteract the acceleration effect of application-specific chip ASICs. Ethash uses a data table with an initial value of 1GB and a pseudo-noise table (cache) with an initial value of 16MB. The data table and pseudo-noise table will be recalculated after every interval of 30,000 blocks. This interval of 30,000 blocks is called an epoch. The content generated by each epoch will increase, so 1GB and 16MB are just basic values. The computer system of the embodiment of the present application will store the entire data table and pseudo-noise table. When a computer system performs a proof-of-work calculation on a block, it first fills a random number (nonce) into the block header and continuously looks up the table in SHA-3 form to find the mixed value MIX to calculate the solution of the block.

The data table used by the Ethereum hashing algorithm during operation is called a directed acyclic graph (DAG). When the sub-operation module 2041 performs the proof-of-work algorithm, it will randomly read 64 data from the DAG, and each data is 128 bytes. The sub-operation module 2041 will first randomly select an initial value, and then randomly read a data from the DAG. After the sub-operation module 2041 combines the initial value with the data read from the DAG, it can be converted into an intermediate product through the hash function SHA-3. Then, the sub-operation module 2041 randomly reads a piece of data from the DAG again, mixes it with the intermediate product and executes the next hash function SHA-3. After repeating this 64 times, the sub-operation module 2041 can obtain the proof of work of the corresponding memory sub-block 212.

The memory testing method of the present application will be described below with reference to FIG. 2 and FIG. 3. In the present embodiment, when performing a memory test, the memory device 210 is basically divided into a plurality of memory sub-blocks 212, and each of the memory sub-blocks 212 is tested separately. First, the same data table is established in a plurality of memory sub-blocks 212, and the plurality of memory sub-blocks 212 are, for example, at least two memory sub-blocks 212. In one embodiment, the same data table can be established for all memory sub-blocks 212, and the present application is not limited thereto. Then, the plurality of sub-operation modules 2041 in the operation module 204 execute the test program on the plurality of memory sub-blocks 212 at the same time. That is, a sub-operation module 2041 executes a test program on a memory sub-block 212 with a data table, and at the same time, a plurality of sub-operation modules 2041 execute the test program on a plurality of memory sub-blocks 212 individually. The test program provides a plurality of different pre-prepared initial values #N and a known solution #A corresponding to each initial value #N for each sub-operation module 2041. Each initial value #N is a value required for the sub-operation module 2041 to perform a workload proof operation. In one embodiment, the sub-operation module 2041 can also use an externally input hash value #H as an initial value. In each workload proof operation, the sub-operation module 2041 can read and write the data table in the memory sub-block 212 multiple times to generate multiple operation results corresponding to each initial value #N. After the judgment module 206 obtains the operation results from the sub-operation module 2041 and compares them with the corresponding known solution #A, it can calculate the error rate of the tested memory sub-block 212.

After calculating the error rate of the memory sub-block 212, the judgment module 206 compares it with a critical value #T to determine whether the availability of the memory sub-block 212 is available or unavailable. Afterwards, the judgment module 206 records the number #R of the available or unavailable memory sub-block 212 in the firmware 202. For example, in some applications, the critical value #T only requires 80%. In more stringent applications, the critical value #T may require 99% or 99.999%.

In this embodiment, by establishing the same data table for the tested memory sub-block 212, the memory testing method of the present application can only use the initial value #N corresponding to the data table and the corresponding known solution #A to determine the availability of the tested memory sub-block 212, thereby effectively reducing the complexity of the memory testing method. At the same time, by testing multiple memory sub-blocks 212 at the same time, the overall testing time of the memory device is further reduced, thereby achieving the purpose of improving the testing efficiency.

The workload proof operation mentioned in this embodiment can be an Ethereum hashing algorithm. The data table is the aforementioned directed acyclic graph DAG. In order to fully test the memory units in each memory sub-block 212, a directed acyclic graph DAG with a size consistent with the memory sub-block 212 can be generated in the memory sub-block 212 through the program configuration of the computing module 204.

Furthermore, the pre-prepared initial value #N and the corresponding known solution #A may be pre-stored in the firmware 202 at the time of leaving the factory, or may be values inputted from the outside in real time.

In the embodiment of the computer system 200 of the present application, the initial size of the directed acyclic graph DAG may be 1 GB. However, the size of the directed acyclic graph DAG increases as the number of blocks on the blockchain increases. In other words, the size of the directed acyclic graph DAG is not always a fixed value, and may increase or decrease as required in actual applications.

Assuming that the total size of the memory device in the computer system 200 is 4GB, we can divide the memory device into 8192 memory sub-blocks 212, and each memory sub-block 212 has the same size of 512 kilobytes (KB). At the same time, the size of the directed acyclic graph DAG in the Ethash algorithm is also configured to be 512KB. In this way, running the Ethash algorithm once to obtain a proof of work step is equivalent to randomly reading 64*128 bytes = 8KB of data from the memory sub-block 212 of size 512KB. In a further approach, the segmentation size of each memory sub-block 212 can be flexibly adjusted. For example, if a memory sub-block 212 is found to have a high error rate after testing, it can be cut into smaller memory sub-blocks and tested separately to reduce the scope of unusable sub-blocks and increase available capacity.

In this embodiment, multiple sets of initial values of known results can be prepared in advance as test samples. When the sub-operation module 2041 of the operation module 204 uses a memory sub-block 212 to obtain an operation result, the operation result can be compared with the known result. If the two are the same, it means that the 8KB data randomly read this time are all correct. In this embodiment, different initial values can be repeatedly used to make the sub-operation module 2041 perform multiple operations on the same memory sub-block 212 to increase the number of memory units accessed in the memory sub-block 212. It is understandable that, since a directed acyclic graph DAG is stored in the memory sub-block 212, after multiple test operations are performed on the same memory sub-block 212 using a certain number of different initial values, it can be confirmed that all memory units in the memory sub-block 212 are tested. Similarly, the above process can also be applied to 8192 areas in the memory device. After testing all available areas in the memory sub-block 212, the memory device can be used for subsequent calculations and applications.

FIG4 is a memory testing method according to an embodiment of the present application, which includes steps S100 and S200. In step S100, a data table is established in at least two memory sub-blocks. In this step, the data table is a directed acyclic graph DAG, and the data tables in at least two memory sub-blocks 212 are the same. In one embodiment, the same data table can be established in all memory sub-blocks 212 in the memory device 210, and the present application is not limited thereto. In step S200, the memory sub-blocks for which the data table is established are tested simultaneously. In this step, the plurality of sub-operation modules 2041 of the operation module 204 can simultaneously perform the test procedure on the corresponding memory sub-blocks 212 for which the data tables have been established. That is, the plurality of memory sub-blocks 212 can execute the test procedure at the same time, thereby greatly reducing the test time of the memory device and achieving the purpose of improving the test efficiency.

Furthermore, step S200 further includes step S210 to step S260, as shown in FIG5 .

In step S210, the computer system 200 starts to perform a memory test. The sub-operation module 2041 tests one of the memory sub-blocks 212 in the memory device 210, and sequentially uses a plurality of different pre-prepared starting values to perform a workload proof operation on the memory sub-block 212. In step S220, the result of each workload proof operation is compared with the corresponding known solution to determine whether the operation result is correct, and the correct and incorrect records of multiple operation results are stored. In step S230, it is determined whether the workload operation of all initial values is completed. If so, the execution continues to step S240. If there are unused initial values, step S210 is repeated.

In step S240, the data error rate of the memory sub-block 212 is calculated. Since the correct and error records of multiple calculation results have been obtained in steps S210 to S230, the data error rate of the memory sub-block 212 can be calculated. In step S250, the judgment module 206 can mark the memory sub-block 212 as available or unavailable according to the data error rate.

In step S260, the determination module 206 stores the marking information of the memory sub-block 212 determined to be available or unavailable in the firmware. It is to be understood that the above steps are only exemplary, and the execution order can be reasonably adjusted. The memory test method can be performed when the computer system 200 is turned on, or when the computer system 200 is in an idle state. The memory test method can also be triggered only when the user requests it.

In summary, the embodiment of the present application proposes a memory test method and a computer system suitable for a wafer stacking architecture. By utilizing the native algorithm in the operation module 204 in combination with different initial values and known solutions, the availability of the memory device can be directly determined based on the operation result of the operation module 204, without the need to design additional test logic in the computer system 200. At the same time, the same data table is established for the tested memory sub-block 212. The memory test method of the present application can only use the initial value #N and the corresponding known solution #A corresponding to the data table to determine the availability of the tested memory sub-block 212, effectively reducing the complexity of the memory test method. In addition, the computer system of the present application is defined with multiple sub-computing modules 2041, so that multiple memory sub-blocks 212 can be tested at the same time, which greatly reduces the overall testing time of the memory device and achieves the purpose of improving the testing efficiency.

It should be noted that, in this article, the term "includes", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the phrase "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

The embodiments of the present application are described above in conjunction with the drawings, but the present application is not limited to the above-mentioned specific embodiments. The above-mentioned specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, a person skilled in the art to which the present invention belongs can make many forms without departing from the purpose of the present application and the scope of protection of the patent application, all of which are within the protection of the present application.

100: 3D wafer products

102:Connection pad

104:Connection pad

110:Memory crystal layer

112: Memory device

120: Logic Circuit Layer

122:Logic Circuit

130: Base

200:Computer System

202: Firmware

204: Computational Module

2041: Sub-computation module

206: Judgment module

210: Memory device

212: Memory sub-block

S100, S200, S210~S260: Steps

#R:Number

#N: Initial value

#H: hash value

#T: critical value

#A: Known solution

The figures described here are used to provide a further understanding of the present application and constitute a part of the present application. The schematic embodiments of the present application and their description are used to explain the present application and do not constitute an improper limitation on the present application. In the figures: Figure 1 is a schematic diagram of a three-dimensional wafer product architecture according to an embodiment of the present application. Figure 2 is a schematic diagram of a computer system architecture according to an embodiment of the present application. Figure 3 is a schematic diagram of a computing module architecture according to an embodiment of the present application. Figure 4 is a flow chart of a memory test method according to an embodiment of the present application. Figure 5 is a flow chart of a memory sub-block test method according to an embodiment of the present application.

200:Computer system

110: Memory crystal layer

120: Logic circuit layer

130: Base

202: Firmware

204: Computation module

206: Judgment module

210: Memory device

212: Memory sub-block

#R:Number

#N: Initial value

#H: hash value

#T: critical value

#A: known solution

Claims (9)

A memory testing method is applied in a computer system; wherein the computer system comprises at least one memory device, a firmware, a computing module connected to the firmware and the at least one memory device, and a judgment module connected to the computing module; wherein the memory testing method comprises: dividing the at least one memory device into a plurality of memory sub-blocks; establishing the same data table in at least two of the plurality of memory sub-blocks; and making the at least two memory sub-blocks simultaneously perform a testing procedure to judge the availability of the at least two memory sub-blocks, wherein the computing module A plurality of sub-operation modules are defined, each of which performs the test procedure on a memory sub-block; the test procedure includes: providing a plurality of different initial values and a known solution corresponding to each initial value; the operation module performs multiple proof-of-work operations on a memory sub-block, and each proof-of-work operation reads and writes the data table multiple times according to one of the initial values to generate multiple operation results corresponding to each initial value; and the judgment module obtains the operation results from the operation module and compares them with the corresponding known solutions to calculate the error rate of the memory sub-block. The memory testing method as described in claim 1 further comprises: the judgment module compares the error rate of the memory sub-block with a critical value to judge the availability of the memory sub-block. The memory testing method as described in claim 2 further comprises: the judgment module records the number of the memory sub-block in the firmware according to the judgment result of the availability. A memory testing method as described in claim 1, wherein: the proof-of-work operation is a block solving algorithm based on a hash function; and the data table is a directed acyclic graph. A memory testing method as described in claim 4, wherein: the size of the directed acyclic graph is consistent with the size of the memory sub-block; and the computer system is based on a wafer stacking architecture, comprising a memory crystal layer, a logic circuit layer and at least one substrate stacked into a three-dimensional structure. A computer system based on a wafer stacking architecture comprises: at least one memory device; a firmware; a computing module connected to the firmware and the at least one memory device to test the at least one memory device; and a judgment module connected to the computing module; wherein: when the computing module divides the at least one memory device into a plurality of memory sub-blocks, when the computing module tests at least two of the plurality of memory sub-blocks, the same data table is established in the at least two memory sub-blocks, and the at least two memory sub-blocks are tested simultaneously. A proof-of-work operation is performed using multiple initial values in sequence, so that the data table in the at least two memory sub-blocks is read and written multiple times to generate multiple operation results corresponding to the initial values, wherein each initial value corresponds to a known solution; and the judgment module obtains the operation results from the operation module and compares them with the corresponding known solutions to calculate the error rate of the at least two memory sub-blocks; wherein the operation module defines multiple sub-operation modules, each of which performs the proof-of-work operation on a memory sub-block using the multiple initial values in sequence. A computer system based on a wafer stacking architecture as described in claim 6, wherein the judgment module compares the error rate of the at least two memory sub-blocks with a critical value to judge the availability of the memory sub-blocks. A computer system based on a wafer stacking architecture as described in claim 6, wherein: the proof-of-work operation is a block solving algorithm based on a hash function; and the data table is a directed acyclic graph. The computer system based on the wafer stacking architecture as described in claim 6 further comprises a memory crystal layer, a logic circuit layer and at least one substrate stacked into a three-dimensional structure; wherein: the logic circuit layer is connected to the at least one memory device and the substrate through a plurality of connection pads; the firmware, the computing module, and the judgment module are configured in the logic circuit layer; and the at least one memory device is configured in the memory crystal layer.