TWI890246B - Integrated circuit for gate overvoltage protection of power devices - Google Patents

Abstract

An integrated gate overvoltage protection circuit for protecting the gate of a main field effect transistor (FET). The gate protection circuit includes a blocking FET and a discharge FET connected between the gate and the drain of the main FET. The gate overvoltage protection circuit is configured to turn on both the first FET and the second FET in the event of a fault condition, such that charge on the gate of the main FET is discharged through the first FET and the second FET to the drain of the main FET, thereby protecting the gate of the main FET.

Description

Integrated circuit for gate overvoltage protection of electrical equipment

Invention Field

The present invention generally relates to an integrated circuit (IC) for gate overvoltage protection in electrical devices.

Background of invention

Overvoltage protection circuits prevent damage to electrical components such as transistors. For example, back-to-back Zener diodes are used to protect silicon MOSFETs and field-effect transistors (FETs) from overvoltage. FIG. 1 , based on U.S. Patent No. 5,172,290, shows one such known overvoltage protection circuit. In FIG. 1 , two Zener diodes 3 and 4 are connected back-to-back between the gate terminal G and the source terminal S of a power MOSFET 1. Zener diodes 3 and 4 protect the gate of MOSFET 1 from excessive positive and negative voltages.

However, the simple protection circuit in Figure 1 has undesirable parasitic inductance, so a more integrated solution that saves PCB area is needed.

In other prior art protection circuits, a series-connected stack of gate-drain FETs (effectively, diodes) is coupled to the drain of a gallium nitride (GaN) FET for overvoltage protection. Such a circuit is shown in Figures 2A and 2B of U.S. Patent Publication No. 2016/0372920. Protection circuit 80 includes an enhancement-mode GaN FET transistor 85 connected between nodes A and B. When the voltage at node A is greater than the sum of the voltage thresholds of a diode-connected transistor 82, which is higher than the voltage at node B, diode-connected transistor 82 conducts current from node A to node B through resistor 84. As a result, the gate voltage of enhancement-mode GaN FET transistor 85 rises, and GaN FET transistor 85 conducts current from node A to node B, thereby reducing the voltage difference between nodes A and B and clamping it to approximately the sum of the voltage thresholds of transistor 82. FIG2B shows a similar protection circuit 90 that includes a depletion-mode GaN transistor 94 cascaded with a diode-connected enhancement-mode GaN transistor 96, replacing resistor 84 of FIG2A.

However, if there is a high positive gate-to-drain bias voltage, the circuits of Figures 2A and 2B cannot provide gate protection because there is no effective current path to discharge the gate. Diode 82 of Figure 2A cannot provide a path to discharge the gate because the diodes are reverse biased. FET 94 in series at the gate with the two FETs 96 in Figure 2B cannot provide a good current path because FET 94 is in the off state.

Therefore, it is necessary to provide an integrated gate protection circuit that does not have the above-mentioned drawbacks.

Summary of the Invention

The present invention addresses the above-mentioned shortcomings of prior art protection circuits by providing an integrated gate protection circuit for protecting the gate of a main FET from voltage stresses due to fault conditions.

Advantageously, the circuit of the present invention provides gate overvoltage protection up to at least 25 V, which is significantly higher than the 5 V or 6 V gate voltage rating of typical GaN FET power transistors.

In a preferred embodiment, the gate protection circuit of the present invention is provided as an integrated circuit for protecting the gate of a main field-effect transistor (FET), such as a bidirectional GaN FET. The gate protection circuit includes a blocking FET and a discharge FET connected between the gate and drain of the main FET. The gate overvoltage protection circuit is configured to turn on both the first FET and the second FET in the event of a fault condition, causing the charge on the gate of the main FET to discharge through the first and second FETs to the drain of the main FET, thereby protecting the gate of the main FET.

The above and other preferred features described herein, including various novel details of implementation and component combinations, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It should be understood that the specific methods and apparatus are shown for illustration only and are not intended to limit the scope of the claims. Those skilled in the art will understand that the principles and features taught herein can be employed in various and numerous embodiments without departing from the scope of the claims.

Detailed description of the preferred embodiment

In the following detailed description, reference is made to certain embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to practice them. It should be understood that other embodiments may be employed and that various structural, logical, and electrical changes may be made. Combinations of features disclosed in the following detailed description may not be necessary to practice the teachings in the broadest sense and are provided solely to specifically describe representative examples of the present teachings.

FIG3 illustrates a first embodiment of a gate protection circuit according to the present invention. Gate protection circuit 300 includes a blocking FET 302 and a discharge FET 304. In a preferred embodiment of the present invention, FETs 302 and 304 are GaN FETs. The drain of blocking FET 302 is connected to the drain of discharge FET 304. The source and gate of FET 302 are connected to terminal G, which is connected to the gate of the main power FET (not shown) protected by the circuit. The source of discharge FET 304 is connected to the drain of the main power FET, and the gate of discharge FET 304 is connected to capacitor 306 and gate resistor 314.

The gate protection circuit 300 also includes a gate resistor 308 connected between a driver 310 and the gate of the main FET. The driver 310 generates a voltage equal to Vdd (the power supply voltage for the main FET) plus an additional bias voltage (e.g., 5 V), as shown in FIG4.

The fault input is received at port 312 connected to terminal DS, which is connected to the drain of the main FET and also to the discharge FET 304 through a gate resistor 314.

4 , when the main FET is turned on during normal operating conditions (no faults), the circuit of the present invention behaves as if the gate protection circuit 300 is not present. More specifically, voltage Vdd is connected to the drain of the main FET. As mentioned above, driver 310 generates a voltage equal to voltage Vdd plus a small bias voltage (e.g., 5 V). For example, if Vdd is 25 V, driver 310 can generate a voltage of 30 V. Thus, the present invention provides gate overvoltage protection for voltages up to at least 25 V, which is significantly higher than the typical 5 V or 6 V gate voltage rating of typical power GaN FET devices.

The current Ig associated with the generated voltage is supplied to the gate of the main FET (through gate resistor 308). Under these conditions, the current through capacitor 306 will be approximately zero, and the discharge FET 304 will be off due to the zero gate-to-source voltage. When the discharge FET 304 is off, the main FET operates as if the gate protection is not present due to the zero current passing through the discharge FET 304 and the blocking FET 302.

5 , when the main FET is off during normal operating conditions (no faults), the system will behave similarly as if gate protection 300 is not present. In the main FET's off state, the voltage supplied by driver 310 is 0 V, thereby disconnecting blocking FET 302 and thereby preventing current from flowing through blocking FET 302 and discharge FET 304.

Referring now to FIG6 , when a fault occurs during the on-state of the main FET, the voltage at the fault input port 312 is shorted to zero, and Vdd rapidly drops to zero. A high gate voltage stress (Vdd + 5 volts) is present on the main FET, triggering the gate protection circuit 300 to activate and rapidly discharge the main FET Ciss. The gate protection circuit 300 operates in two steps. First, the voltage across capacitor 306 remains approximately the same, and therefore the gate voltage of the discharge FET 304 remains the same. However, the source voltage of the discharge FET (Vdd) has dropped to 0 V. Therefore, the discharge FET 304, with its positive gate-to-source voltage, turns on. The relatively large discharge gate resistor 314 is used to maintain the gate voltage Vg and slow down the discharge of the gate voltage of the discharge FET 304.

After the discharge FET 304 is turned on, the charge stored by the input capacitance of the main FET's gate is quickly discharged through the blocking FET 302 and the discharge FET 304 (both turned on), thereby effectively reducing the voltage surge at the gate terminal of the main FET and thereby protecting the gate of the main FET.

FIG7 illustrates a second embodiment of a gate protection circuit according to the present invention. In gate overvoltage protection circuit 700, gate resistor 308 is moved to a different location, namely, between the source of blocking FET 302 and the gate of the main FET. This configuration has the advantage that leakage current through discharge FET 304 does not increase the voltage drop across gate resistor 308, which in the configuration of FIG3 reduces the effective gate drive voltage of the main FET.

FIG8 illustrates a gate overvoltage protection circuit 800 according to a third embodiment of the present invention, which includes two voltage clamps 822 and 824. Voltage clamp 822 limits the voltage across capacitor 306, as capacitors may have a finite breakdown voltage. Voltage clamp 824 protects the gate-to-source voltage of discharge FET 304 from voltage overshoot and undershoot. Resistor 326 is an optional current limiting resistor.

Figures 9A and 9B illustrate implementations of voltage clamps that may be used in the embodiment of Figure 8. Figure 9A shows a voltage clamp 900 that may be used for the first voltage clamp 822, where terminal 1 of the clamp 900 is connected to the gate drive output (with an optional current limiting resistor 826), and terminal 2 is connected to the gate of the discharge FET 304.

Voltage clamp 900 includes one or more diodes 930a, 930b, ..., 930n connected in series. Diodes 930a, 930b, ..., 930n can be implemented as GaN Schottky diodes, source-gate connected GaN FETs, or a combination of both. The number n of diodes is determined by the breakdown voltage of capacitor 306, the forward voltage drop of each diode, and/or the threshold voltage of the GaN FET.

FIG9B illustrates an embodiment of a second voltage clamp 824, wherein terminal 1 of clamp 950 is connected to the gate of discharge FET 304 of FIG8 , and terminal 2 is connected to the drain of the main FET. Voltage clamp 950 of FIG9B includes two series-connected diode strings 952, 954 connected in an anti-parallel configuration. The diodes in the two parallel series are oriented oppositely to provide clamping in two directions. As shown, the first series of diodes 952a, 952b, ..., 952n includes n diodes oriented from terminal 1 to terminal 2, and the second series of diodes 954a, 954b, ..., 954m includes m diodes oriented from terminal 2 to terminal 1. As in FIG9A , the diodes can be GaN Schottky diodes, source-to-gate connected GaN FETs, or a combination thereof. The number of diodes, n and m, is determined by the maximum gate-to-source voltage of the discharge FET 304, the forward voltage drop of each diode, and/or the voltage threshold of the series-connected GaN FETs.

The implementation of capacitor 306 of the present invention is not limited to a passive metal-insulator-metal (MIM) structure. FIG10 illustrates an example of an alternative integrated circuit capacitor implementation consisting of a gate-source connection FET 1056 in series with a Schottky diode 1058. The gate-source connection serves as the bottom plate of the capacitor, and the drain of FET 1056 serves as the top plate of the capacitor. Diode 1058 is optional. The purpose of including diode 1058 (if included) is to prevent potential reverse current flow in FET 1056 when the main FET is in the off state.

Figures 11-13 provide examples of bidirectional GaN FETs with the integrated gate protection circuit of the present invention.

FIG11 shows a bidirectional GaN FET 1162 with integrated gate protection between the gate G and the two drains D1 and D2 of the back-to-back GaN FETs 1102-1 and 1102-2 of the bidirectional GaN FET. The integrated protection circuit 1160 includes a main gate protection building block 800 having terminals Cin, DS, and G similar to those shown in FIG8 .

12 shows a bidirectional GaN FET 1262 with integrated gate protection between the gates G and the common source S of the back-to-back GaN FETs 1268-1 and 1268-2 of the bidirectional GaN FET. Likewise, the integrated protection circuit 1260 includes a main gate protection building block 800 having terminals Cin, DS, and G similar to those shown in FIG8 .

FIG13 shows a bidirectional GaN FET 1362 with integrated gate protection between the gates G and sources of two pairs of back-to-back GaN FETs 1368-1 and 1368-2, and 1368-3 and 1368-4. Similarly, the integrated protection circuit 1360 includes a main gate protection building block 800 having terminals Cin, DS, and G similar to those shown in FIG8 .

In summary, in the various embodiments described above, the present invention provides an integrated gate protection circuit that protects the gate of a power device from voltage stresses exceeding the gate breakdown voltage. Advantageously, the present invention provides gate overvoltage protection up to at least 25 V, which is significantly higher than the 6 V or 7 V gate voltage rating of typical GaN FET power devices.

The above description and drawings are merely illustrative of specific embodiments that achieve the features and advantages described herein. Modifications and substitutions may be made to specific process conditions. Therefore, the embodiments of the present invention are not to be considered as limited by the above description and drawings.

1: Terminal/Power MOSFET 2: Terminal 3, 4: Zener diode 80, 90: Protection circuit 82: Diode-connected transistor/transistor/diode 84, 326: Resistor 85: Enhancement-mode GaN FET 94: Depletion-mode GaN transistor/FET 96: Enhancement-mode GaN transistor/FET 300: Gate protection circuit 302: Blocking FET 304: Discharge FET 306: Capacitor 308: Gate resistor 310: Driver 312: Fault input 314: Gate resistor/discharge gate resistor 700: Gate overvoltage protection circuit 800: Gate overvoltage protection circuit/Main gate protection building block 822: Voltage clamp/First voltage clamp 824: Voltage clamp/Second voltage clamp 900, 950: Voltage clamp 930a, 930b, 930n, 952a, 952b, 952n, 954a, 954b, 954m: Diode 1056: Gate-to-source connection FET/FET 1058: Schottky diode/Diode 1102-1, 1102-2, 1268-1, 1268-2, 1368-1, 1368-2, 1368-3, 1368-4: Back-to-back GaN FETs 1160, 1260, 1360: Integrated protection circuitry 1162, 1262, 1362: Bidirectional GaN FETs A, B: Nodes Cin, DS: Terminals D1, D2: Drain G: Gate terminal/Gate/Terminal Ig: Current S: Source terminal/Common source Vdd: Voltage Vg: Gate voltage

The features, objects, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals designate corresponding elements throughout and in which:

Figure 1 shows a conventional gate overvoltage protection circuit using back-to-back Zener diodes.

2A and 2B show a circuit using a series gate-to-drain connected diode in a conventional overvoltage protection circuit.

FIG3 is a schematic diagram of the gate protection circuit of the present invention.

FIG4 illustrates the operation of the gate protection circuit of the present invention during the on-state of the main FET.

FIG5 illustrates the operation of the gate protection circuit of the present invention during the off state of the main FET.

FIG6 illustrates the operation of the gate protection circuit of the present invention during an on-state fault condition of the main FET.

FIG7 shows a second embodiment of a gate protection circuit in which the gate resistor for the main FET is external to the circuit.

FIG8 shows a third embodiment of a gate protection circuit with voltage clamping.

9A and 9B illustrate a voltage clamping implementation.

FIG10 shows an implementation of an integrated capacitor.

Figure 11 shows a bidirectional GaN FET with integrated gate protection between the gate and two drains of the bidirectional GaN FET.

FIG12 shows a bidirectional GaN FET with integrated gate protection between the gate and source of the bidirectional GaN FET.

Figure 13 shows a bidirectional GaN FET with two embedded back-to-back FETs, with integrated gate protection between the gate and source of the bidirectional GaN FET.

300: Gate protection circuit

302: Blocking FET

304: Discharge FET

306: Capacitor

308: Gate resistor

310:Driver

312: Fault input port

314: Gate Resistor/Discharge Gate Resistor

DS: Terminal

G: Gate terminal/gate/terminal

S: Source terminal/common source

Claims (15)

A gate overvoltage protection circuit for protecting a main field effect transistor (FET) having a gate and a drain, comprising: a first FET and a second FET, the FETs being connected between the gate and the drain of the main FET, wherein the first FET and the second FET each have a drain, a source, and a gate, and wherein: the drain of the first FET is connected to the drain of the second FET, and the source and the gate of the first FET are connected to the gate of the main FET; and The source of the second FET is connected to the drain of the main FET, the gate of the second FET is connected to a first terminal of a capacitor, and the gate of the first FET is coupled to a second terminal of the capacitor; wherein the first FET and the second FET are turned off under a normal condition, and wherein the gate overvoltage protection circuit is configured to turn on both the first FET and the second FET under a fault condition, causing the charge on the gate of the main FET to discharge to the drain of the main FET through the first FET and the second FET, thereby protecting the gate of the main FET. The circuit of claim 1, further comprising a driver for supplying a voltage equal to a voltage at the drain of the main FET plus a bias voltage, wherein the voltage supplied by the driver is applied to the gate of the main FET and the capacitor. The circuit of claim 2, wherein the voltage at the drain of the main FET is 25 V and the bias voltage is 5 V. The circuit of claim 1, further comprising a gate resistor having a first end connected to the gate of the second FET and the first end of the capacitor, and having a second end connected to the drain of the main FET. The circuit of claim 1, further comprising a gate resistor connected to the gate of the main FET. The circuit of claim 1, further comprising a first voltage clamp connected in parallel with the capacitor. The circuit of claim 6, wherein the first voltage clamp comprises a plurality of serially connected diodes or a plurality of serially connected gate-to-source connected FETs. The circuit of claim 6, further comprising a second voltage clamp connected between the gate of the second FET and the drain of the main FET. The circuit of claim 8, wherein the second voltage clamp comprises a plurality of series-connected diodes connected in an anti-parallel configuration or a plurality of series-connected gate-to-source connected FETs connected in an anti-parallel configuration. The circuit of claim 1, wherein the main FET and the first FET and the second FET are gallium nitride (GaN) FETs. The circuit of claim 1, wherein the capacitor comprises a gallium nitride (GaN) FET with a source-to-gate connection. The circuit of claim 11, wherein the source-to-gate connected GaN FET is connected in series with a diode. The circuit of claim 1, wherein the main FET is a bidirectional FET. The circuit of claim 13, wherein the bidirectional FET is a bidirectional GaN FET. An integrated gate protection circuit comprises: A bidirectional field effect transistor (FET) having a gate and a drain; and A gate overvoltage protection circuit for protecting the bidirectional FET, the gate overvoltage protection circuit comprising: A first FET and a second FET, the FETs being connected between the gate and the drain of the bidirectional FET, wherein the first FET and the second FET each have a drain, a source, and a gate, and wherein: The drain of the first FET is connected to the drain of the second FET, and the source and the gate of the first FET are connected to the gate of the bidirectional FET; and The source of the second FET is connected to the drain of the bidirectional FET, the gate of the second FET is connected to a first terminal of a capacitor, and the gate of the first FET is coupled to a second terminal of the capacitor; wherein the first FET and the second FET are turned off under a normal condition, and wherein the gate overvoltage protection circuit is configured to turn on both the first FET and the second FET under a fault condition, causing charge from the gate of the bidirectional FET to discharge through the first FET and the second FET to the drain of the bidirectional FET, thereby protecting the gate of the bidirectional FET.