TWI903348B - Apparatus and method for encoding and decoding bayer pattern images - Google Patents
Apparatus and method for encoding and decoding bayer pattern imagesInfo
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本發明係有關於視訊編解碼器(codec),特別地,尤有關於一種用以編碼及解碼拜耳圖像影像(Bayer pattern images)之裝置及方法。This invention relates to a video codec, and more particularly to an apparatus and method for encoding and decoding Bayer pattern images.
數位相機、智慧型手機及其他成像(imaging)系統中,影像訊號處理器(image signal processor,ISP)是一特殊元件,主要功能是用來處理來自拜耳顏色濾波器陣列(Bayer color filter array,CFA)的原始輸出資料,並將其轉換為一高品質影像。在去馬賽克(demosaicing)步驟之前,ISP取得與拜耳圖像影像有關之低/標準動態範圍(low/standard dynamic range,LSDR)影像(各像素僅包含一種顏色)。於此階段,透過合併一連串具不同曝光時間的LSDR影像,ISP可產生一高動態範圍(high dynamic range,HDR)影像。因為這些LSDR影像是在不同時間點拍攝的,故這些LSDR影像會依序被壓縮並儲存於動態隨機存取記憶體(DRAM)內。之後,這些壓縮資料再從DRAM被讀回、解壓縮及被合併影像以產生HDR影像。因此,業界亟需一種無失真壓縮方案,令壓縮資料佔據較少的記憶體空間,並且使用者不會感受到任何畫質失真。In digital cameras, smartphones, and other imaging systems, the image signal processor (ISP) is a specialized component whose primary function is to process the raw output data from the Bayer color filter array (CFA) and convert it into a high-quality image. Before the demosaicing step, the ISP acquires a low/standard dynamic range (LSDR) image (each pixel containing only one color) associated with the Bayer image. At this stage, by merging a series of LSDR images with different exposure times, the ISP can generate a high dynamic range (HDR) image. Because these LSDR images were captured at different times, they are sequentially compressed and stored in Dynamic Random Access Memory (DRAM). Subsequently, this compressed data is read back from DRAM, decompressed, and merged to produce HDR images. Therefore, the industry urgently needs a lossless compression solution that occupies less memory space and ensures users do not experience any image quality distortion.
有鑒於上述問題,本發明的目的之一是提供一種拜耳圖像影像之視訊編碼裝置,令壓縮資料佔據較少的記憶體空間,並且使用者不會感受到任何畫質失真。In view of the above problems, one of the purposes of this invention is to provide a video encoding device for Bayer image processing that allows compressed data to occupy less memory space and does not cause any image quality distortion to be perceived by the user.
根據本發明之一實施例,係提供一種拜耳圖像影像之視訊編碼裝置,包含:一量化器、一預測器以及一可變長度編碼器。該量化器,用以根據一量化參數Q及一方程式,對一輸入像素及一目前預測像素之間的差值D進行量化,以產生一量化序列中之一量化值 ,其中,該方程式為 。該預測器,耦接至該量化器,用以進行一組第一操作,包含:根據一目前區段在一目前拜耳圖像影像中的位置,提供該目前預測像素。該可變長度編碼器,耦接至該量化器,用以進行一組第二操作,包含:(1)計算連續零的數目ZR,其中ZR個連續零是位在該量化序列的下一個非零整數之前,或是位在該量化序列的末段;(2)以一第一碼字組,將該ZR個連續零編碼為一第一碼字;(3)以一第二碼字組,將該下一個非零整數編碼為一第二碼字;以及,(4)重複第二操作(1)至(3),直到處理完該量化序列中所有量化值為止,以產生一編碼位元組。其中,A滿足以下方程式:(Q A +1)=N,以及其中N=2 d 2 n,n代表該輸入像素的位元寬度以及d為一整數。 According to one embodiment of the present invention, a video encoding apparatus for Bayer image processing is provided, comprising: a quantizer, a predictor, and a variable length encoder. The quantizer is used to quantize the difference D between an input pixel and a currently predicted pixel according to a quantization parameter Q and an equation, to generate a quantized value in a quantization sequence. The equation is: The predictor, coupled to the quantizer, performs a set of first operations, including: providing the current predicted pixel based on the position of a current segment in a current Bayer image. The variable length encoder, coupled to the quantizer, performs a set of second operations, including: (1) calculating the number of consecutive zeros ZR, wherein ZR consecutive zeros are located before the next non-zero integer in the quantization sequence or at the end of the quantization sequence; (2) encoding the ZR consecutive zeros into a first codeword using a first codeword group; (3) encoding the next non-zero integer into a second codeword using a second codeword group; and (4) repeating the second operations (1) to (3) until all quantized values in the quantization sequence have been processed to generate an encoded byte. Wherein, A satisfies the following equation: (Q A + 1) = N, and where N = 2 d 2n , where n represents the bit width of the input pixel and d is an integer.
本發明之另一實施例,係提供一種拜耳圖像影像之視訊編碼方法,包含以下步驟:根據一量化參數Q及一方程式,對一輸入像素及一目前預測像素之間的差值D進行量化,以產生一量化序列中之一量化值 ,其中,該方程式為 ;根據一目前區段在一目前拜耳圖像影像中的位置,提供該目前預測像素;計算連續零的數目ZR,其中ZR個連續零是位在該量化序列的下一個非零整數之前,或是位在該量化序列的末段;以一第一碼字組,將該ZR個連續零編碼為一第一碼字;以一第二碼字組,將該下一個非零整數編碼為一第二碼字;以及,重複該計算步驟、該將該ZR個連續零編碼為該第一碼字步驟以及該將該下一個非零整數編碼為該第二碼字步驟,直到處理完該量化序列中所有量化值為止,以產生一編碼位元組;其中,A滿足以下方程式:(Q A +1)=N;以及,其中,N=2 d 2 n,n代表該輸入像素的位元寬度以及d為一整數。 Another embodiment of the present invention provides a video encoding method for Bayer imagery, comprising the following steps: quantizing the difference D between an input pixel and a currently predicted pixel according to a quantization parameter Q and an equation to generate a quantized value in a quantization sequence. The equation is: Based on the position of a current segment in a current Bayer image, provide the current predicted pixel; calculate the number of consecutive zeros ZR, where ZR consecutive zeros are located before the next non-zero integer in the quantization sequence or at the end of the quantization sequence; encode the ZR consecutive zeros into a first codeword using a first codeword group; encode the next non-zero integer into a second codeword using a second codeword group; and repeat the calculation steps, the steps of encoding the ZR consecutive zeros into the first codeword, and the steps of encoding the next non-zero integer into the second codeword, until all quantization values in the quantization sequence have been processed to generate an encoded byte; wherein A satisfies the following equation: (Q A + 1) = N; and, where N = 2 d 2n , where n represents the bit width of the input pixel and d is an integer.
本發明之另一實施例,係提供一種拜耳圖像影像之視訊解碼裝置,包含:一可變長度解碼器及一預測器。該可變長度解碼器,用以進行一組第一操作,包含:以交替的方式,比較一編碼位元組之前端位元樣式與一第一碼字組及一第二碼字組中所有的碼字,以產生一解碼數值,該解碼數值可以是一組連續零或是一個非零整數。該預測器,耦接至該可變長度解碼器,用以進行一組第二操作,包含:根據一目前重建區段在一目前重建拜耳圖像影像中的位置,提供一目前預測像素。Another embodiment of the present invention provides a video decoding apparatus for Bayer imagery, comprising: a variable-length decoder and a predictor. The variable-length decoder performs a first set of operations, including: alternately comparing the leading bit pattern of an encoded byte with all codewords in a first codeword group and a second codeword group to generate a decoded value, which may be a sequence of consecutive zeros or a non-zero integer. The predictor, coupled to the variable-length decoder, performs a second set of operations, including: providing a currently predicted pixel based on the position of a currently reconstructed segment in a currently reconstructed Bayer imagery.
本發明之另一實施例,係提供一種拜耳圖像影像之視訊解碼方法,包含以下步驟:以交替的方式,比較一編碼位元組之前端位元樣式與一第一碼字組及一第二碼字組中所有的碼字,以產生一解碼數值,該解碼數值可以是一組連續零或是一個非零整數;以及,根據一目前重建區段相對於一目前重建拜耳圖像影像的位置,提供一目前預測像素。Another embodiment of the present invention provides a video decoding method for Bayer imagery, comprising the following steps: alternately comparing the leading bit pattern of an encoded byte with all codewords in a first codeword group and a second codeword group to generate a decoded value, which may be a set of consecutive zeros or a non-zero integer; and providing a currently predicted pixel based on the position of a currently reconstructed segment relative to a currently reconstructed Bayer imagery.
茲配合下列圖示、實施例之詳細說明及申請專利範圍,將上述及本發明之其他目的與優點詳述於後。The above and other objectives and advantages of this invention are described in detail below with reference to the following figures, detailed descriptions of embodiments, and the scope of the patent application.
在通篇說明書及後續的請求項當中所提及的相關用語定義如下,除非本說明書中另有特別指明:「一」及「該」等單數形式的用語,都同時包含單數及複數的涵義;「/」的符號包含「或」與「及」的涵義。在通篇說明書中,具相同功能的電路元件使用相同的參考符號。The following definitions apply to terms used throughout this specification and in subsequent requests, unless otherwise specified in this specification: the singular forms of "a" and "the" have both singular and plural meanings; the slash "/" has the meanings of "or" and "and". Throughout this specification, circuit components with the same function use the same reference symbols.
請注意,內嵌於ISP 120的編解碼系統100僅是示例,而非本發明之限制,實際實施時,編解碼系統100可採用任何其他的配置,例如內嵌於其他影像處理裝置,此亦落入本發明之範圍。Please note that the encoding/decoding system 100 embedded in the ISP 120 is merely an example and not a limitation of the invention. In actual implementation, the encoding/decoding system 100 may adopt any other configuration, such as being embedded in other image processing devices, which also falls within the scope of the invention.
圖1係根據本發明一實施例,顯示一編解碼系統100的示例。參考圖1,編解碼系統100係內嵌於一成像系統(如數位相機)的ISP 120中。ISP 120從影像感應器110(如拜耳CFA)接收拜耳圖像影像,並於進行去馬賽克步驟之前,於去雜訊(denoising)、白平衡(white balancing)、色彩轉換(color transform)、曝光校正(exposure correction)及伽瑪校正(gamma correction)步驟之中,選擇性地進行零個或更多個步驟,以產生LSDR影像。在LSDR影像中,各像素只有一個顏色,並以8、10、12、14、或16位元資料(即位元寬度(bit width))來表示。因為這些LSDR影像是在不同時間點拍攝的,編解碼系統100依序壓縮這些LSDR影像,並儲存於DRAM 130,之後,編解碼系統100再從DRAM 130讀回資料壓縮資料及解壓縮資料,接著,ISP 120合併影像以產生HDR影像。圖1的實施例中的編解碼系統100包含圖2的區段(segment)編碼器200及圖5的區段解碼器500,同時,區段編碼器200及區段解碼器500係設置於ISP 120內。另一實施例中,區段編碼器200及區段解碼器500係分別設置於二個不同成像裝置/系統內。Figure 1 illustrates an example of an encoding/decoding system 100 according to an embodiment of the present invention. Referring to Figure 1, the encoding/decoding system 100 is embedded in an imaging system (such as a digital camera) ISP 120. The ISP 120 receives a Bayer image from an image sensor 110 (such as a Bayer CFA) and, before performing a demosaic step, selectively performs zero or more steps in denoising, white balancing, color transform, exposure correction, and gamma correction to generate an LSDR image. In the LSDR image, each pixel has only one color and is represented by 8, 10, 12, 14, or 16 bits of data (i.e., bit width). Because these LSDR images were captured at different times, the encoding/decoding system 100 sequentially compresses these LSDR images and stores them in the DRAM 130. Then, the encoding/decoding system 100 reads back the compressed and decompressed data from the DRAM 130. Next, the ISP 120 merges the images to generate an HDR image. In the embodiment of Figure 1, the encoding/decoding system 100 includes the segment encoder 200 of Figure 2 and the segment decoder 500 of Figure 5. Both the segment encoder 200 and the segment decoder 500 are located within the ISP 120. In another embodiment, the segment encoder 200 and the segment decoder 500 are located in two different imaging devices/systems.
圖2係根據本發明一實施例,顯示拜耳圖像影像之區段編碼器200的示意圖。參考圖2,本發明區段編碼器200包含一減法器210、一量化器(quantizer)220、一可變長度編碼器(variable length coder,VLC)230、一限幅器(clipper)240、一預測器(predictor)230、一加法器260以及一乘法器270。一般而言,各LSDR影像係分成多個區段(segment),且以逐區段及逐像素方式,饋入至區段編碼器200。以下詳述區段編碼器200及區段解碼器500的運作方式,且假設各區段寬度W為32個像素以及各像素只有一個顏色並以8位元(n=8)資料來表示,其中n代表輸入像素s[k]的位元寬度。Figure 2 is a schematic diagram of a Bayer image segment encoder 200 according to an embodiment of the present invention. Referring to Figure 2, the segment encoder 200 of the present invention includes a subtractor 210, a quantizer 220, a variable length coder (VLC) 230, a clipper 240, a predictor 230, an adder 260, and a multiplier 270. Generally, each LSDR image is divided into multiple segments and fed to the segment encoder 200 in a segment-by-segment and pixel-by-pixel manner. The operation of the segment encoder 200 and the segment decoder 500 is described in detail below, assuming that the width W of each segment is 32 pixels and that each pixel has only one color and is represented by 8 bits (n=8) of data, where n represents the bit width of the input pixel s[k].
一目前LSDR影像的一目前區段的一輸入像素s[k]被饋入至減法器210,之後,減法器210將輸入像素s[k]的值減去目前預測像素p[k]的值,以得到一差值D,其中k=0~31。接著,量化器220根據一量化階層(step)/參數Q,對差值D進行量化,例如計算 ,以產生一量化值delta,其中⌊ ⌋代表下取整函數(floor function)。然而,在計算機系統中,除法不容易實施,但乘法及往右移位(right shift)則相對容易實施。一實施例中,於量化器220中提供下列程式碼及方程式1以進行量化: ; // 方程式1 delta=D<0 ? - : ; //若D<0, delta= - ,否則, delta= An input pixel s[k] of a current segment of a current LSDR image is fed into subtractor 210. Subtractor 210 then subtracts the value of the currently predicted pixel p[k] from the value of the input pixel s[k] to obtain a difference D, where k = 0~31. Next, quantizer 220 quantizes the difference D according to a quantization step/parameter Q, for example, by calculating... This generates a quantized value delta, where ⌊⌋ represents the floor function. However, division is not easy to implement in computer systems, but multiplication and right shift are relatively easy to implement. In one embodiment, the following code and Equation 1 are provided in quantizer 220 for quantization: // Equation 1 delta = D < 0 ? - : //If D < 0, delta = - Otherwise, delta =
其中,N及A都是整數。若輸入像素s[k]包含一n位元資料,則N=2 n。因為N是2的冪次方,故可用”往右移位(right shift)”來取代除法。例如,若N=4096,則須將分子( )往右移12次/個位元,來得到 值。 Where N and A are integers. If the input pixel s[k] contains n bits of data, then N = 2^ n . Since N is a power of 2, a right shift can be used instead of division. For example, if N = 4096, then the numerator ( Shift right 12 times per bit to get value.
圖3顯示N、Q及A值之間的關係。圖3中的A值為一整數且必須滿足條件:(Q A +1)=N。選擇A值時,選定的N值必須大於或等於對應的2 n值。例如,假設n=10且Q=5,根據圖3,從最左邊數來第3行(column),沒有支援任何A值;此時,有二個選擇,可選擇對應N=4096之行的A=819,或選擇對應N=65536之行的A=13107,請注意上述二個對應的N值都大於2 10(n=10)。 Figure 3 shows the relationship between N, Q, and the value of A. The value of A in Figure 3 is an integer and must satisfy the condition: (Q...) A + 1) = N. When choosing a value for A, the selected value for N must be greater than or equal to the corresponding 2^ n value. For example, assuming n = 10 and Q = 5, according to Figure 3, the 3rd column from the left does not support any value for A; at this time, there are two choices: you can choose A = 819 for the column corresponding to N = 4096, or you can choose A = 13107 for the column corresponding to N = 65536. Note that both of these corresponding N values are greater than 2 ^10 (n = 10).
圖4顯示具相同量化階層/參數Q=3的不同方程式經計算所得出的結果值的一部份(D值範圍從-3到14),其中方程式3( )是習知的,而方程式1是根據N=4096及A=1365來計算。圖4表中的第二列顯示計算 的結果值,方程式2( )則是源自 的修改版。從圖4可以觀察到,相較於第二列(row)的商,第三列(方程式2)的計算結果值的分布更加平均,且所有群組係以3的倍數為中心。為了逼近方程式2的計算結果值,業界之前已經公布方程式3。然而,很明顯的,第三列及第四列的資料並不匹配,以及對應方程式3之第四列中,D=0附近的資料也未平均分布;相反地,第三列(方程式2)及第五列(方程式1)的資料則完美地匹配。本發明方程式1的計算結果值絕對的正確性及平均分布,最小化量化錯誤(quantization error)並幫助進行無失真壓縮/解壓縮,其中,上述量化錯誤指的是差值D與其量化值delta之間的差值。 Figure 4 shows a portion of the calculated results (D values ranging from -3 to 14) for different equations with the same quantization level/parameter Q=3, where equation 3 ( The first equation is known, while Equation 1 is calculated based on N=4096 and A=1365. The second column of the table in Figure 4 shows the calculation. The result value of equation 2 ( ) is derived from The revised version. As can be observed from Figure 4, compared to the quotients in the second column (row), the calculated results in the third column (Equation 2) are more evenly distributed, and all groups are centered around multiples of 3. To approximate the calculated results of Equation 2, Equation 3 was previously published in the industry. However, it is clear that the data in the third and fourth columns do not match, and the data near D=0 in the fourth column of Equation 3 is not evenly distributed; conversely, the data in the third column (Equation 2) and the fifth column (Equation 1) match perfectly. The calculated results of Equation 1 of this invention have absolute accuracy and even distribution, minimize quantization error, and help with lossless compression/decompression, where the aforementioned quantization error refers to the difference between the difference D and its quantized value delta.
回到圖2,VLC 230係以本發明的運行值編碼方法(run value coding method)對一量化值delta序列進行編碼,以產生一編碼位元流(bitstream)。在本說明書中,「零運行(zero-run,ZR)」一詞指的是上述量化值delta序列中連續零的數目,而這些連續零是位在量化序列的下一個非零整數之前,或是位在量化序列的末段。表一顯示不同ZR(即連續零的不同數目)的編碼表。
於表一中,「區段末端(end of segment,EOS)」一詞指的是在上述量化值delta序列中,後續/剩餘的值(直到量化值delta序列的末端)都等於0。「逃離運行(ESC-run,ER)」一詞指的是在上述量化值delta序列中,連續零的預設數目;因此,在上述量化值delta序列中,當ZR> ER時,ZR個連續零會以ER加上(ZR-ER)個連續零來編碼。例如,7個連續零(ZR=7及ER=3)會以{3, 3, 1}的格式,亦即10’b1110111010來編碼。於表一中,五個碼字(codeword)為五個一元碼(unary code),分別對應上述量化值delta序列中,有0個零(即沒有零)、1個零、2個零、3個零、以及其剩餘值(直到序列的末端)都等於0。於表一中,各碼字(即各一元碼)採用ZR個1加上一個0來表示一對應的ZR值,然而,此非本發明之限制,於另一實施例中,各碼字(即各一元碼)係採用ZR個0加上一個1來表示一對應的ZR值。In Table 1, the term "end of segment (EOS)" refers to the fact that in the aforementioned delta quantization sequence, all subsequent/remaining values (up to the end of the delta quantization sequence) are equal to 0. The term "ESC-run (ER)" refers to the default number of consecutive zeros in the aforementioned delta quantization sequence; therefore, in the aforementioned delta quantization sequence, when ZR > ER, ZR consecutive zeros will be encoded as ER plus (ZR - ER) consecutive zeros. For example, 7 consecutive zeros (ZR=7 and ER=3) will be encoded in the format {3, 3, 1}, i.e., 10’b1110111010. In Table 1, the five codewords are five unary codes, corresponding to the following in the above-mentioned delta quantization value sequence: 0 zeros (i.e., no zeros), 1 zero, 2 zeros, 3 zeros, and the remainder (up to the end of the sequence) is equal to 0. In Table 1, each codeword (i.e., each unary code) uses ZR 1s plus one 0 to represent a corresponding ZR value. However, this is not a limitation of the present invention. In another embodiment, each codeword (i.e., each unary code) uses ZR 0s plus one 1 to represent a corresponding ZR value.
表二顯示非零整數的編碼表。
於表二中,x代表0或1,s代表delta值的正負號;另外,delta值的量越大,對應的碼字中的位元數/深度也越大。例如,若”s=+1”代表負號,delta值為-5會被編碼為碼字6’b110011,delta值為+8會被編碼為碼字8’b11100000。各碼字依序包含一階級碼、一索引碼及一符號碼,其中,該階級碼為一元碼。對於一個非零的delta值等於-9,利用一元編碼法來編碼其階級q,會產生一階級碼4’b1110,其中q= =3;利用q位元且以二進位格式來表示一整數C= modulo 2 q=1,以產生一索引碼3’b001;最後,附加一符號位元值1至索引碼,以形成碼字8’b11100011。於表二的各碼字中,各階級碼(即各一元碼)採用q個1加上一個0來表示一階級q,以及索引碼被排在階級碼及符號碼之間,然而,此非本發明之限制。於另一實施例中,於各碼字中,各階級碼(即各一元碼)採用q個0加上一個1來表示一階級q,以及符號碼被排在階級碼及索引碼之間。 In Table 2, x represents 0 or 1, and s represents the sign of the delta value. Furthermore, the larger the delta value, the greater the number of bits/depth in the corresponding codeword. For example, if "s=+1" represents a negative sign, a delta value of -5 will be encoded as codeword 6'b110011, and a delta value of +8 will be encoded as codeword 8'b11100000. Each codeword sequentially contains a first-order code, an index code, and a symbol code, where the first-order code is a unary code. For a non-zero delta value equal to -9, encoding its order q using unary coding will produce the first-order code 4'b1110, where q = =3; Represent an integer C using q bits in binary format. The code modulo 2 q = 1 is used to generate an index code 3'b001; finally, a symbol bit value of 1 is appended to the index code to form the codeword 8'b11100011. In each codeword in Table 2, each level code (i.e., each unary code) uses q ones plus one zero to represent level q, and the index code is placed between the level code and the symbol code; however, this is not a limitation of the invention. In another embodiment, in each codeword, each level code (i.e., each unary code) uses q zeros plus one 1 to represent level q, and the symbol code is placed between the level code and the index code.
本發明運行值編碼方法的特色之一是:根據表一及表二的編碼表,以交替的方式對連續零及一非零整數進行編碼。換言之,VLC 230的輸出包含二種標誌,二者一直重複直到區段結束。這二種標誌分別是代表ZR個連續零的第一碼字(由表一決定)及代表非零整數的第二碼字(由表二決定)。例如,在接收如下量化值delta序列(共W個量化值delta):{+2, -3, 0, 0, 0, 1, 4, 0, 0, 0, 0 …., 0}之後,VLC 230將(+2)視為”ZR=0加上(+2)”,並將其編碼為5’b01000(=1’b0+4’b1000);VLC 230將(-3)視為”ZR=0加上(-3)”, 並將其編碼為5’b01011(=1’b0+4’b1011);VLC 230將{0, 0, 0, 1}視為”ER=3、ZR=0加上(+1)”, 並將其編碼為7’b1110000(=4’b1110 + 1’b0 + 2’b00);VLC 230將序列末段中後續/剩餘的零:{0, 0, 0, 0 …., 0}視為EOS,並將其編碼為單一碼字4’1111。One of the features of the operating value encoding method of this invention is that consecutive zeros and a non-zero integer are encoded alternately according to the encoding tables in Tables 1 and 2. In other words, the output of the VLC 230 contains two flags that are repeated until the end of the segment. These two flags are the first codeword representing ZR consecutive zeros (determined by Table 1) and the second codeword representing a non-zero integer (determined by Table 2). For example, after receiving the following sequence of quantized delta values (W quantized delta values in total): {+2, -3, 0, 0, 0, 1, 4, 0, 0, 0, 0 …., 0}, the VLC 230 treats (+2) as "ZR=0 plus (+2)" and encodes it as 5’b01000 (=1’b0+4’b1000); the VLC 230 treats (-3) as "ZR=0 plus (-3)" and encodes it as 5’b01011 (=1’b0+4’b1011); the VLC 230 treats {0, 0, 0, 1} as "ER=3, ZR=0 plus (+1)" and encodes it as 7’b1110000 (=4’b1110 + 1’b0 + 2’b00); VLC 230 treats the subsequent/remaining zeros at the end of the sequence: {0, 0, 0, 0 …., 0} as EOS and encodes them as a single codeword 4’1111.
一實施例中,於VLC 230中提供下列程式碼以對量化值delta序列進行編碼: main(void) { ZR =p= 0; while (p<W) { // W 代表區段寬度 if (seq[p]==0) ZR++; // 首先,計算連續零的數目ZR;seq[.] 代表量化值delta序列 else { encode_ZR(ZR); // 接著,對 ZR編碼 ZR = 0; encode_value(seq[p]); // 最後,對一非零整數編碼 } p++; } if (ZR>0) output ‘1111’; // 表示有EOS事件 } encode_ZR(int ZR){ while (ZR>=3){ output ‘1110’; //表示有 ER 事件 ZR-=3; // 每跳三個零檢查一次ZR } if (ZR==0) output ‘0’; // 請參考表一的碼字 else if (ZR==1) output ‘10’; else if (ZR==2) output ‘110’; } encode_Value (int value) { if (value<0) sign=1; else sign=0; V = abs(value); Le = 0; // Le 代表階級 bound = 2; while (1) { if (V < bound) break; bound = bound*2; Le=Le+1; } Base = bound/2; Index = V – Base; output Le consecutive ‘1’; //請參考表二的碼字 output ‘0’; // 輸出階級碼 output ‘Index’ with Le bits; // 輸出索引碼 output ‘sign’ with one bit; // 輸出符號碼 } In one embodiment, the following code is provided in VLC 230 to encode a sequence of quantized delta values: main(void) { ZR =p= 0; while (p<W) { // W represents the segment width if (seq[p]==0) ZR++; // First, calculate the number of consecutive zeros ZR; seq[.] represents the sequence of quantized delta values else { encode_ZR(ZR); // Next, encode ZR ZR = 0; encode_value(seq[p]); // Finally, encode a non-zero integer } p++; } if (ZR>0) output ‘1111’; // Indicates an EOS event } encode_ZR(int ZR){ while (ZR>=3){ output '1110'; // Indicates an ER event ZR-=3; // Check ZR every three zeros } if (ZR==0) output '0'; // Please refer to the code in Table 1 else if (ZR==1) output '10'; else if (ZR==2) output '110'; } encode_Value (int value) { if (value<0) sign=1; else sign=0; V = abs(value); Le = 0; // Le represents the class bound = 2; while (1) { if (V < bound) break; bound = bound*2; Le=Le+1; } Base = bound/2; Index = V – Base; output Le consecutive '1'; // Please refer to the code in Table 2 output '0'; // Output index code output ‘Index’ with 1 bit; // Output index code output ‘sign’ with one bit; // Output sign code }
接著,乘法器270將各delta值乘上Q,以得到一乘積值cp,之後,加法器260將乘積值cp及目前預測值p[k]相加,以得到一總和V。然後,限幅器240根據最小值Mi及最大值Ma,接收該總和V,以產生一目前重建像素r[k],故Mi<=r[k]<=Ma。Next, multiplier 270 multiplies each delta value by Q to obtain a product value cp. Then, adder 260 adds the product value cp to the current predicted value p[k] to obtain a sum V. Then, limiter 240 receives the sum V based on the minimum value Mi and the maximum value Ma to generate a currently reconstructed pixel r[k], so Mi <= r[k] <= Ma.
一實施例中,於預測器 250中提供下列程式碼以進行預測:p[k]=k<=1? (bx==0? dc : r[W-2+k]) : r[k-2] ;In one embodiment, the following code is provided in predictor 250 for prediction: p[k] = k <= 1? (bx == 0? dc : r[W-2+k]) : r[k-2] ;
(bx, by)是上述目前區段的最左側像素於目前LSDR影像中的座標,W是目前區段的寬度,以及dc=2 n-1,其中bx=0~(Wi-1)及by=0~(Hi-1),而Wi及Hi分別代表各LSDR影像的寬度及高度。上述有關預測的程式碼進行下列步驟:(1)當k>1時,目前預測像素p[k]的值等於先前第二個重建像素(the second immediately preceding reconstructed pixel)r[k-2] 的值(若k>1,則p[k]=r[k-2]);(2) 若k<=1,則檢查bx是否等於0;(3)若bx=0,則表示上述目前區段係位在目前LSDR影像的最左側,故設定p[k]=dc=2 n-1;(4)若bx 0且k<=1,則設定p[k]=r[W-2+k],其中r[W]是一個大小為W、共用且可覆蓋的一維陣列。若bx 0,則表示上述目前區段不是位在目前LSDR影像的最左側。 (bx, by) are the coordinates of the leftmost pixel of the current segment in the current LSDR image, W is the width of the current segment, and dc = 2n-1 , where bx = 0~(Wi-1) and by = 0~(Hi-1), and Wi and Hi represent the width and height of each LSDR image, respectively. The above prediction code performs the following steps: (1) When k > 1, the value of the currently predicted pixel p[k] is equal to the value of the second immediately preceding reconstructed pixel r[k-2] (if k > 1, then p[k] = r[k-2]); (2) If k <= 1, then check if bx is equal to 0; (3) If bx = 0, it means that the current segment is located on the leftmost side of the current LSDR image, so set p[k] = dc = 2n-1 ; (4) If bx If 0 and k <= 1, then set p[k] = r[W-2+k], where r[W] is a shared and covert one-dimensional array of size W. If bx 0 indicates that the current segment is not located on the far left of the current LSDR image.
圖5係根據本發明一實施例,顯示拜耳圖像影像之區段解碼器500的示意圖。參考圖5,本發明區段解碼器500包含一可變長度解碼器(variable length decoder,VLD)510、一限幅器240、一預測器520、一加法器260以及一乘法器270。大體來說,區段解碼器500所進行的解碼過程係相反於上述區段編碼器200所進行的編碼過程。VLD 510以交替的方式,比較編碼位元流的前端位元樣式(front/leading bit pattern)與表一及表二中所有的碼字,以在一解碼資料序列中產生一解碼數值delta,該解碼數值delta可以是一組連續零(即一連串的零)或是一個非零整數。換言之,VLD 510先比較編碼位元流的前端位元樣式與表一中所有的碼字以產生一對應解碼數值delta,再比較編碼位元流的下一個前端位元樣式與表二中所有的碼字以產生一對應解碼數值delta。依此方式,重複上述過程直到整個編碼位元流都處理完為止。詳情請參考後面的程式碼。Figure 5 is a schematic diagram of a Bayer image segment decoder 500 according to an embodiment of the present invention. Referring to Figure 5, the segment decoder 500 of the present invention includes a variable length decoder (VLD) 510, a limiter 240, a predictor 520, an adder 260, and a multiplier 270. Generally speaking, the decoding process performed by the segment decoder 500 is the opposite of the encoding process performed by the segment encoder 200 described above. The VLD 510 compares the front/leading bit pattern of the encoded bit stream with all the codewords in Tables 1 and 2 in an alternating manner to generate a decoded value delta in a decoded data sequence. The decoded value delta can be a set of consecutive zeros (i.e., a series of zeros) or a non-zero integer. In other words, VLD 510 first compares the pattern of the first bit of the encoded bit stream with all the codewords in Table 1 to generate a corresponding decoded value delta. Then, it compares the pattern of the next first bit of the encoded bit stream with all the codewords in Table 2 to generate a corresponding decoded value delta. This process is repeated until the entire encoded bit stream has been processed. Please refer to the code below for details.
預測器250及520的結構及運作是類似的。例如,於預測器 520中提供下列程式碼以進行預測:p[k]=k<=1? (ax==0? dc : r[W-2+k]) : r[k-2] ;The structures and operations of predictors 250 and 520 are similar. For example, predictor 520 provides the following code for prediction: p[k]=k<=1? (ax==0? dc : r[W-2+k]) : r[k-2] ;
(ax, ay)是上述目前重建區段的最左側像素於目前解壓縮/重建LSDR影像中的座標,k代表目前重建像素於該目前重建區段的索引值,W是目前重建區段的寬度,以及dc=2 n-1,其中k=0~(W-1)、ax=0~(Wi-1)及ay=0~(Hi-1),而Wi及Hi分別代表各重建LSDR影像的寬度及高度。上述有關預測器 520預測的程式碼進行下列步驟:(1)當k>1時,目前預測像素p[k]的值等於先前第二個重建像素r[k-2] 的值 (若k>1,則p[k]=r[k-2]);(2) 若k<=1,則檢查ax是否等於0;(3)若ax=0,則表示上述目前重建區段係位在目前重建LSDR影像的最左側,故設定p[k]=dc=2 n-1;(4)若ax 0且k<=1,則設定p[k]=r[W-2+k],其中r[W]是一個大小為W、共用且可覆蓋的一維陣列。若ax 0,則表示上述目前重建區段不是位在目前重建LSDR影像的最左側。 (ax, ay) are the coordinates of the leftmost pixel of the currently reconstructed segment in the currently decompressed/reconstructed LSDR image, k represents the index value of the currently reconstructed pixel in the currently reconstructed segment, W is the width of the currently reconstructed segment, and dc= 2n-1 , where k=0~(W-1), ax=0~(Wi-1) and ay=0~(Hi-1), and Wi and Hi represent the width and height of each reconstructed LSDR image, respectively. The above-mentioned predictor 520 prediction code performs the following steps: (1) When k>1, the value of the currently predicted pixel p[k] is equal to the value of the previous second reconstructed pixel r[k-2] (if k>1, then p[k]=r[k-2]); (2) If k<=1, then check if ax is equal to 0; (3) If ax=0, it means that the above-mentioned currently reconstructed segment is located on the leftmost side of the currently reconstructed LSDR image, so set p[k]=dc= 2n-1 ; (4) If ax If 0 and k <= 1, then set p[k] = r[W-2+k], where r[W] is a shared and covert one-dimensional array of size W. If ax 0 indicates that the currently reconstructed segment is not located on the far left of the currently reconstructed LSDR image.
至於區段解碼器500的其餘元件(240、260及270),則與在區段編碼器200的運作方式相同,不再贅述。最後,區段解碼器500輸出目前重建區段的目前重建像素r[k]。32個重建像素(因為W=32)形成一重建區段,而一組重建區段形成一重建LSDR影像。一實施例中,於VLD 510中提供下列程式碼以對編碼位元流進行解碼: main(void) { p = 0; while (p<W) { // W 代表區段寬度 {ZR, EOS} = Decode_Run_EOB(); // 先將”連續零” 解碼出來; 程式回傳 ZR 及 EOS if (EOS) break; //若EOS 旗標被設定,就跳出while迴圈 for (i=0; i<ZR; i++) { //若ZR>0,解碼數值=連續零 seq[p] = 0; p++; } {value} = Decode_Value(); // 再將 “非零整數” 解碼出來; 程式回傳值value=非零整數 seq[p] = value; p++; } while (p<W) { seq[p] = 0; //代表有一EOS事件 p++; } } Decode_Run_EOB(){ Z=peep(4, ptr); // 從目前位址ptr讀出4個位元,再將讀出值指定給Z,但不改變ptr;Z是一個4位元變數;ptr 是一指標/位址,指向編碼位元流的最前端 EOS = 0; ZR = 0; if (Z==‘1111’) { fetch(4, ptr); // 從目前位址ptr讀出4個位元,且將ptr 改為(ptr+4) EOS=1; exit; } else{ do { if (Z==‘0xxx’) ZR = ZR+0; else if (Z==’10xx’) ZR=ZR+1; else if (Z==‘110x’) ZR=ZR+2; else if (Z==‘1110’) { ZR=ZR+3; fetch(4, ptr); // 從目前位址ptr讀出4個位元,且將ptr 改為(ptr+4) Z=peep(4, ptr); // 從目前位址ptr讀出4個位元,再將讀出值指定給Z,但不改變ptr return ZR,EOS; } } while(Z==‘1110’) fetch (ZR+1, ptr); // 從目前位址ptr讀出(ZR+1)個位元,且將ptr 改為(ptr+(ZR+1)) } Decode_Value () { Level = 0; do { X=peep(8, ptr); // 從目前位址ptr讀出8個位元,再將讀出值指定給Z,但不改變ptr; X是一個8位元變數; ptr 是一指標/位址,指向編碼位元流的最前端 if (X==‘0xxxxxxx’) level=level+0; else if (X==’10xxxxxx’) level=level+1; else if (X==‘110xxxxx’) level=level+2; else if (X==‘1110xxxx’) level=level+3; else if (X==‘11110xxx’) level=level+4; else if (X==‘111110xx’) level=level+5; else if (X==‘1111110x’) level=level+6; else if (X==‘11111110’) level=level+7; else { level = level+8; // 連續1的數目是大於或等於8 fetch (8, ptr); // 從目前位址ptr讀出8個位元,且將ptr 改為(ptr+8) } } while(X==‘11111111’); index=fetch(level, ptr); // 從目前位址ptr讀出level個位元,再將讀出值指定給index,且將ptr 改為(ptr+level) sign=fetch(1, ptr); // 從目前位址ptr讀出一個位元,再將讀出值指定給sign,且將ptr 改為(ptr+1) value = (sign?-1:1)*((1<<level)+index); return value; } The remaining elements (240, 260, and 270) of the segment decoder 500 operate in the same way as the segment encoder 200, and will not be described in detail. Finally, the segment decoder 500 outputs the currently reconstructed pixels r[k] of the currently reconstructed segment. 32 reconstructed pixels (because W=32) form a reconstructed segment, and a group of reconstructed segments forms a reconstructed LSDR image. In one embodiment, the following code is provided in VLD 510 to decode the encoded bitstream: main(void) { p = 0; while (p<W) { // W represents the segment width {ZR, EOS} = Decode_Run_EOB(); // First decode the "consecutive zeros"; the program returns ZR and EOS if (EOS) break; // If the EOS flag is set, exit the while loop for (i=0; i<ZR; i++) { // If ZR>0, the decoded value = consecutive zeros seq[p] = 0; p++; } {value} = Decode_Value(); // Then decode the "non-zero integers"; the program returns value = non-zero integer seq[p] = value; p++; } while (p<W) { seq[p] = 0; // Represents an EOS event p++; } } Decode_Run_EOB(){ Z=peep(4, ptr); // Read 4 bits from the current address ptr, assign the read value to Z, but do not change ptr; Z is a 4-bit variable; ptr is a pointer/address pointing to the beginning of the encoded bit stream EOS = 0; ZR = 0; if (Z==‘1111’) { fetch(4, ptr); // Read 4 bits from the current address ptr, and change ptr to (ptr+4) EOS=1; exit; } else{ do { if (Z==‘0xxx’) ZR = ZR+0; else if (Z=='10xx') ZR=ZR+1; else if (Z=='110x') ZR=ZR+2; else if (Z=='1110') { ZR=ZR+3; fetch(4, ptr); // Read 4 bits from the current address ptr and change ptr to (ptr+4) Z=peep(4, ptr); // Read 4 bits from the current address ptr, assign the read value to Z, but do not change ptr return ZR,EOS; } } while(Z=='1110') fetch (ZR+1, ptr); // Read (ZR+1) bits from the current address ptr and change ptr to (ptr+(ZR+1)) } Decode_Value () { Level = 0; do { X=peep(8, ptr); // Read 8 bits from the current address ptr, then assign the read value to Z, without changing ptr; X is an 8-bit variable; ptr is a pointer/address pointing to the beginning of the encoded bit stream if (X=='0xxxxxxx') level=level+0; else if (X=='10xxxxxx') level=level+1; else if (X=='110xxxxx') level=level+2; else if (X=='1110xxxx') level=level+3; else if (X=='11110xxx') level=level+4; else if (X=='111110xx') level=level+5; else if (X=='1111110x') level=level+6; else if (X=='11111110') level=level+7; else { level = level+8; // The number of consecutive 1s is greater than or equal to 8 fetch (8, ptr); // Read 8 bits from the current address ptr and change ptr to (ptr+8) } } while(X=='11111111'); index=fetch(level, ptr); // Read level bits from the current address ptr, assign the read value to index, and change ptr to (ptr+level) sign=fetch(1, ptr); // Read one bit from the current address ptr, assign the read value to sign, and change ptr to (ptr+1) value = (sign?-1:1)*((1<<level)+index); return value; }
在上述程式碼中,函數peep(m, ptr)代表從目前指標/位址ptr讀出m個位元,但不改變ptr;函數fetch(m, ptr)代表從目前指標/位址ptr讀出m個位元,且將ptr 改為(ptr+m),其中,ptr 是一指標/位址,指向編碼位元流的最前端。In the code above, the function peep(m, ptr) reads m bits from the current pointer/address ptr without changing ptr; the function fetch(m, ptr) reads m bits from the current pointer/address ptr and changes ptr to (ptr+m), where ptr is a pointer/address pointing to the beginning of the encoded bit stream.
簡言之,本發明區段編碼器200的壓縮率是大於或等於2x;此外,區段編碼器200輸出的編碼位元流在區段解碼器500中可以數學方式逆轉以及解壓縮,以產生一高品質重建影像,因此,在人類的眼睛看來,是完全相同於輸入影像(饋入至區段編碼器200)。再者,本發明利用表一及表二的編碼表來進行編碼及解碼的過程是既簡單又準確。In short, the compression ratio of the segment encoder 200 of this invention is greater than or equal to 2x; furthermore, the encoded bit stream output by the segment encoder 200 can be mathematically reversed and decompressed in the segment decoder 500 to produce a high-quality reconstructed image, which, to the human eye, is exactly the same as the input image (feeded to the segment encoder 200). Moreover, the encoding and decoding process using the encoding tables in Tables 1 and 2 is both simple and accurate.
本發明區段編碼器200及區段解碼器500可以軟體、客製化硬體(如現場可程式閘陣列(field programmable gate array)或一特殊應用積體電路(application specific integrated circuit))、或軟體(或韌體)及硬體的組合來實施。一較佳實施例中,區段編碼器200中的VLC 230及預測器250係利用至少一第一儲存裝置以及至少一第一一般用途(general-purpose)處理器來實施;區段解碼器500中的VLD 510及預測器520係利用至少一第二儲存裝置以及至少一第二一般用途處理器來實施。該至少一第一儲存裝置儲存一第一處理器可執行程式,而該至少一第二儲存裝置儲存一第二處理器可執行程式。當該至少一第一一般用途處理器執行該第一處理器可執行程式時,該至少一第一一般用途處理器被組態(configured)以運作有如:VLC 230及預測器250。當該至少一第二一般用途處理器執行該第二處理器可執行程式時,該至少一第二一般用途處理器被組態以運作有如:VLD 510及預測器520。The segment encoder 200 and segment decoder 500 of the present invention can be implemented in software, custom hardware (such as a field programmable gate array or an application-specific integrated circuit), or a combination of software (or firmware) and hardware. In a preferred embodiment, the VLC 230 and predictor 250 in the segment encoder 200 are implemented using at least one first storage device and at least one first general-purpose processor; the VLD 510 and predictor 520 in the segment decoder 500 are implemented using at least one second storage device and at least one second general-purpose processor. The at least one first storage device stores a first processor executable program, and the at least one second storage device stores a second processor executable program. When the at least one first general-purpose processor executes the first processor executable program, the at least one first general-purpose processor is configured to operate as follows: VLC 230 and predictor 250. When the at least one second general-purpose processor executes the second processor executable program, the at least one second general-purpose processor is configured to operate as follows: VLD 510 and predictor 520.
上述僅為本發明之較佳實施例而已,而並非用以限定本發明的申請專利範圍;凡其他未脫離本發明所揭示之精神下所完成的等效改變或修飾,均應包含在下述申請專利範圍內。The above are merely preferred embodiments of the present invention and are not intended to limit the scope of the patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed in the present invention shall be included in the scope of the patent application below.
110:影像感應器 120:ISP 130:DRAM 200:區段編碼器 210:減法器 220:量化器 230:可變長度編碼器 240:限幅器 250、510:預測器 260:加法器 270:乘法器 500:區段解碼器 510:可變長度解碼器 110: Image Sensor 120: ISP 130: DRAM 200: Segment Encoder 210: Subtractor 220: Quantizer 230: Variable Length Encoder 240: Limiter 250, 510: Predictor 260: Adder 270: Multiplier 500: Segment Decoder 510: Variable Length Decoder
[圖1] 係根據本發明一實施例,顯示一編解碼系統100的示例。 [圖2] 係根據本發明一實施例,顯示拜耳圖像影像之區段編碼器200的示意圖。 [圖3]顯示N、Q及A值之間的關係。 [圖4]顯示具相同量化階層/參數Q=3的不同方程式經計算所得出的結果值的一部份(D值範圍從-3到14)。 圖5係根據本發明一實施例,顯示拜耳圖像影像之區段解碼器500的示意圖。 [Figure 1] illustrates an example of an encoding/decoding system 100 according to an embodiment of the present invention. [Figure 2] illustrates a schematic diagram of a Bayer image segment encoder 200 according to an embodiment of the present invention. [Figure 3] shows the relationship between N, Q, and A values. [Figure 4] shows a portion of the calculated values (D values ranging from -3 to 14) of different equations with the same quantization level/parameter Q=3. Figure 5 is a schematic diagram of a Bayer image segment decoder 500 according to an embodiment of the present invention.
200:區段編碼器 200: Segment Encoder
210:減法器 210: Subtraction Device
220:量化器 220: Quantizer
230:可變長度編碼器 230: Variable Length Encoder
240:限幅器 240: Limiter
250:預測器 250: Predictor
260:加法器 260: Adder
270:乘法器 270: Multiplier
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