US11127468B2 - Method for addressing a non-volatile memory on I2C bus and corresponding memory device - Google Patents

Method for addressing a non-volatile memory on I2C bus and corresponding memory device Download PDF

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US11127468B2
US11127468B2 US15/842,586 US201715842586A US11127468B2 US 11127468 B2 US11127468 B2 US 11127468B2 US 201715842586 A US201715842586 A US 201715842586A US 11127468 B2 US11127468 B2 US 11127468B2
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memory
mode
addressing
equal
bits
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US20180301196A1 (en
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François Tailliet
Marc Battista
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STMicroelectronics Rousset SAS
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands

Definitions

  • Embodiments and modes of implementation relate to non-volatile memories and particular embodiments relate to memories compatible with an I 2 C bus.
  • the I 2 C bus is a well-known inter-integrated circuit serial communication standard.
  • FIG. 1 represents the signals of an exemplary communication carried out on an I 2 C bus.
  • the I 2 C bus comprises two wires, a serial data line SDA and a serial clock line SCL, which transmit information between the apparatuses connected to the I 2 C bus.
  • Each apparatus is recognized by a unique slave address (whether it is for example with a microcontroller, a memory or a keyboard interface) and can operate as a sender or a receiver, depending on the function of the apparatus.
  • a memory can both receive and transmit data.
  • the peripherals can also be considered to be masters or slaves during the transmission of data.
  • a master is the device which triggers a transfer of data on the bus and generates the clock signals to allow this transfer. At that moment, any addressed device is considered to be a slave.
  • the line SDA is a bidirectional line and the data to be communicated via the I 2 C bus are materialized by signals that can have a HIGH level or a LOW level.
  • the signal of the line SDA must be stable during the HIGH period of the clock signal.
  • the HIGH or LOW state of the data line SDA can only change when the clock signal on the line SCL is LOW.
  • All the transactions begin with a starting condition “START” STT and terminate with an end condition “STOP” STP.
  • a HIGH to LOW transition on the line SDA while SCL is HIGH defines a starting condition SIT.
  • a LOW to HIGH transition on the line SDA while SCL is HIGH defines an end condition STP.
  • the HIGH and LOW levels of the signal represent the logic values “1” and “0” respectively.
  • the data transfers follow the format represented by FIG. 1 .
  • a slave address SLADR is dispatched. This address is coded on 7 bits followed by an eighth direction bit R/ W , a “zero” indicates a transmission (or write) W, a “one” indicates a request for data (or read) R.
  • the data DATA 1 , DATA 2 are transmitted byte-wise (i.e. 8 bits) on the line SDA.
  • the number of bytes which can be transmitted per transfer is unlimited. Each byte must be followed by a confirmation bit ACK.
  • the data DATA 1 , DATA 2 are transferred with the high-order bit MSB in first position.
  • Confirmation takes place after each byte.
  • the confirmation bit ACK allows the receiver to signal to the sender that the byte has been successfully received and that another byte can be dispatched.
  • a data transfer always terminates with an end condition STP generated by the master.
  • digital data are customarily stored in memory locations arranged in a memory plane.
  • the memory locations are tagged and accessible by respective memory addresses.
  • the direction bit R/ W makes it possible to indicate whether the memory is requested to read data stored in the memory plane or to write new data in the memory plane.
  • the first memory address to be accessed in the memory plane is communicated to the memory immediately after the slave address SLADR.
  • the slave address SLADR is coded in a customary form of the type 1010XXX.
  • the code 1010 is generally used to identify an EEPROM-type memory device, and the three low-order bits XXX of the slave address make it possible, if appropriate, to identify an EEPROM memory device from among several EEPROM memory devices connected to the same I 2 C bus.
  • the EEPROM memory device comprises three hardware-identification pins E 0 , E 1 , E 2 which are brought to respective potentials defining an assignment code on three bits.
  • the last three low-order bits of the slave address SLADR make it possible to select an EEPROM memory device from among several, by comparing the values XXX of the bits and the assignment code associated with each EEPROM memory device.
  • a memory address MEMADR is coded on 19 bits.
  • the standard approach for addressing of such a 4-Mbit memory is to use the last three low-order bits of the slave address not to identify a device, but to communicate the first 3 high-order bits of the memory address MEMADR.
  • the first two data bytes DATA 1 , DATA 2 make it possible to communicate the remaining 16 bits of the 19-bit memory address MEMADR.
  • a method for addressing an integrated circuit for a non-volatile memory of the electrically erasable and programmable type comprising a memory plane and able to be connected to a bus of the I 2 C type, and comprising J hardware-identification pins, with J an integer lying between 1 and 3.
  • the method comprises an assignment of potentials on each of the pins defining for the integrated circuit an assignment code on J bits, a transmission of a slave address on the bus, and then a transfer of data bytes on the bus.
  • the method according to this aspect makes it possible to address the memory plane of a non-volatile memory of the EEPROM type, 4-Mbit EEPROM memories in particular, either in a standard manner advantageously compatible with existing I 2 C bus systems (in the first mode of addressing), or in a way advantageously making it possible to install several non-volatile memories of the EEPROM type, for example of 4 Mbits, on one and the same I 2 C bus (in the second mode of addressing), and one or the other of these two modes of addressing is selectable by the value of the assignment code.
  • the method advantageously includes an identification between the assignment code and J bits from among the last three low-order bits of the slave address, making it possible to select a non-volatile memory integrated circuit from among 2 J -1 non-volatile memory integrated circuits potentially connected to the same I 2 C bus and having different one-to-one respective assignment codes.
  • the reference code can be o-o-o, and for example a simple OR function between the three bits of the assignment code advantageously makes it possible to know whether the assignment code is equal to the reference code.
  • the reference code can be o-o, and a simple OR function between the two bits of the assignment code advantageously makes it possible to know whether the assignment code is equal to the reference code.
  • the non-volatile memory integrated circuit can have a memory capacity of 4 Mbits, with in this case n equal to 19, N equal to 2 and M equal to 3 and include three hardware-assignment pins, i.e., J equal to 3.
  • the method in the first mode of addressing, can include, in the case where M is equal to 2 or to 1 and J is equal to 3, an identification between 3-M bits of the assignment code and 3-M bits from among the last three low-order bits of the slave address, making it possible to select a non-volatile memory integrated circuit from among 2 3-M potential non-volatile memory integrated circuits connected to the same I 2 C bus and having different one-to-one respective assignment codes.
  • an integrated circuit for a non-volatile memory of the electrically erasable and programmable type including a memory plane, able to be connected to a bus of the I 2 C type and including J hardware-identification pins, with J an integer lying between 1 and 3, which are intended to be assigned respective potentials defining for the integrated circuit an assignment code on J bits, the integrated circuit being configured to receive a slave address transmitted on the bus, and then to receive data bytes on the bus.
  • the test circuit is configured so that the logical test includes a logical OR test between the logic values of the J bits of the assignment code. This corresponds for example to a reference code equal to o-o-o (for equal to 3) or to o-o (for J equal to 2).
  • the test circuit is configured to, in the second mode of addressing, compare the assignment code with J bits from among the last three low-order bits of the slave address, and, in the case of difference, place the integrated circuit in the standby phase awaiting a starting condition of the I 2 C protocol.
  • the test circuit is configured to, in the first mode of addressing, compare 3-M bits of the assignment code with 3-M bits from among the last three low-order bits of the slave address, and, in the case of difference, place the integrated circuit in the standby phase awaiting a starting condition of the I 2 C protocol.
  • the integrated circuit has a memory capacity of 4 Mbits, with n equal to 19, N equal to 2 and M equal to 3 and includes three hardware-assignment pins, i.e. J equal to 3.
  • the system can be embodied in an integrated manner, for example in a system on chip (SoC).
  • SoC system on chip
  • An electronic apparatus forming for example a mobile telephone or an auditory prosthesis, advantageously includes a system such as defined hereinabove.
  • FIG. 1 represents the signals of an exemplary communication carried out on an I 2 C bus
  • FIGS. 2 to 5 represent examples of modes of implementation and of embodiment of the invention.
  • the non-volatile memory integrated circuit includes a memory plane making it possible to store digital data in memory locations arranged in rows and columns.
  • a memory location generally includes a floating-gate transistor able to physically store a representation of a digital datum (that is to say a bit), in a conventional manner known per se. Each bit is stored in a memory location and is assigned a respective memory address, the communication of this address allowing the memory to read- or write-access this memory location.
  • the integrated circuit NVM also includes a serial data line SDA input/output and a serial clock line SCL input, two power supply terminals VCC and VSS, as well as a write control pin WC.
  • the terminal VCC is intended to receive a supply voltage, and the terminal VSS a reference voltage such as earth.
  • the SDA input/output is used to transfer incoming or outgoing data.
  • the signal applied to the SCL input is used to regulate the incoming and outgoing signals on the line SDA.
  • the signal present on the write control pin makes it possible to protect the content of the memory from accidental writing operations.
  • the writing operations are rendered impossible in the memory when the signal present on the write control pin WC is at a high level.
  • the writing operations are possible when the signal present on the write control pin WC is at a low level or left floating.
  • the hardware-identification pins E 0 , E 1 , E 2 are intended to be assigned a respective potential defining an assignment code dedicated to the integrated circuit NVM.
  • the assignment of these potentials is performed in a hardware manner during the integration of the integrated circuit on a card for example.
  • the non-volatile memory integrated circuit NVM is configured to operate according to a first mode of addressing M 1 , or according to a second mode of addressing M 2 , as a function of the assignment code defined by the respective couplings of the hardware-identification pins E 0 , E 1 , E 2 to the voltages VCC or VSS.
  • a test circuit MT makes it possible to verify whether or not the assignment code is equal to a reference code, and is furthermore configured to place the integrated circuit NVM in the first mode of addressing M 1 or in the second mode of addressing M 2 , as a function of the result of this test.
  • test circuit MT is configured to carry out a logical test between signals present on the three hardware-identification pins E 0 , E 1 , E 2 .
  • the reference code can be o-o-o
  • the test carried out by the test circuit MT is a logical OR test between the three logic values of the signals present on the hardware-identification pins.
  • the assignment code is equal to “0-0-0”, otherwise, the assignment code includes at least one “1”.
  • the integrated circuit NVM is intended to receive the data A 18 -A 0 of a memory address MEMADR of the memory plane, which address is contained in the last three low-order bits LSB of the slave address SLADR and in the first two data bytes DATA 1 , DATA 2 .
  • the integrated circuit NVM is intended to receive the data A 18 -A 0 of a memory address MEMADR of the memory plane, which address is contained in the first three data bytes DATA 1 , DATA 2 , DATA 3 .
  • These first and second modes of addressing correspond here to a memory having a capacity of 4 Mbits, of which a memory address is coded on 19 bits.
  • a memory address MEMADR is contained in the last M low-order bits LSB of the slave address SLADR and in the first N data bytes
  • a memory address MEMADR is contained in the first N+1 data bytes.
  • the combination Xoo forms an exemplary reference code, with X the value on the arbitrary pin E 2 .
  • the first mode of addressing it is possible to select a 2-Mbit memory from among 2 on the same I 2 C bus with the pin E 2 (by identification of the remaining bit X).
  • this system SYS can be embodied in an integrated manner into a system on chip SOC.
  • FIG. 4 is a chart representing the implementation of addressing of a memory of the 4-Mbit EEPROM type on a bus of the I 2 C type having two modes of addressing M 1 , M 2 , of the type of the integrated circuit NVM described in conjunction with FIG. 2 .
  • the integrated circuit NVM is supplied on its power supply terminals, VCC, VSS, connected to an I 2 C bus and that its hardware-identification pins E 0 , E 1 , E 2 are brought to high or low voltages forming a three-bit assignment code.
  • the memory NVM is initially in a standby phase 100 awaiting the starting condition STT. As long as a starting condition is not sent on the I 2 C bus, the memory NVM remains in the standby phase 100 .
  • a slave address SLADR is transmitted afterwards.
  • a step of so-called integrated circuit identification ICID allows the various slave devices to recognize one another, in relation to the slave address SLADR, if their function is requested.
  • the slave address SLADR includes in this example 7 bits.
  • the code making it possible to identify an EEPROM memory device is 1010 .
  • the memory NVM tests ( 102 ) whether the first four high-order bits MSB of the slave address SLADR form the code 1010 .
  • the memory is placed back in the standby phase 100 .
  • a test circuit MT of the memory integrated circuit NVM tests ( 104 ) whether the assignment code which has been associated with it by wiring is equal to a reference code.
  • the reference code is 0-0-0 in this example, this corresponds to a wiring of the three hardware-identification pins E 0 , E 1 , E 2 to a reference voltage signal VSS.
  • the test can thus be implemented by an OR logic function between the three bits of the assignment code. Nonetheless any reference code can be chosen in association with a test 104 corresponding to this reference code.
  • the integrated circuit is placed in a first mode of addressing M 1 .
  • the first mode of addressing M 1 corresponds, for the following steps, to the customary operation of a 4-Mbit EEPROM memory, advantageously compatible with numerous existing systems using an I 2 C bus, but not being able to include more than a single 4-Mbit EEPROM memory.
  • the 19 bits A 18 -A 0 of the memory address MEMADR of the memory plane are transmitted, in the order from the first high-order bit A 18 to the last low-order bit A 0 , by anticipation in the last three low-order bits LSB of the slave address SLADR, and then in the first data byte DATA 1 , and then in the second data byte DATA 2 .
  • the data bytes following DATAi include the data to be written W received by the memory NVM or the data read R and sent by the memory NVM. These data are transmitted during a transfer step 108 which ends upon communication 110 of an end condition STP. The memory NVM is then placed in the standby phase 100 again.
  • the integrated circuit is placed in a second mode of addressing M 2 .
  • the second mode of addressing M 2 advantageously makes it possible to be able to connect a plurality of non-volatile memories in series, in particular from one to seven 4-Mbit EEPROM memories.
  • the 19 bits A 18 -A 0 of the memory address MEMADR of the memory plane are transmitted, in the order from the first high-order bit A 18 to the last low-order bit A 0 , in the content of the first three data bytes DATA 1 , DATA 2 , DATA 3 .
  • a memory address MEMADR is communicated in an extended manner in the content of the first N+1 data bytes.
  • the memory NVM tests ( 106 ) whether the assignment code E 0 -E 1 -E 2 which has been assigned to it by wiring corresponds to the last three low-order bits LSB of the slave address SLADR.
  • the master device seeks to address itself to another EEPROM-type memory integrated circuit on the I 2 C bus and the memory is placed back in the standby phase 100 .
  • the memory receives the 19 bits A 18 -A 0 of memory address MEMADR that is contained in the first three data bytes DATA 1 -DATA 3 and implements reads R or writes W of the following data bytes DATAi during the transfer step 108 .
  • the transfer step 108 ends upon a communication 110 of end condition STP and the memory NVM then places itself in the standby phase 100 again.
  • FIG. 5 represents an electronic apparatus APP including a system SYS in which a plurality of non-volatile memory integrated circuits NVM wired up to one and the same I 2 C bus, as well as for example a master device MC such as a microcontroller.
  • a master device MC such as a microcontroller.
  • system SYS can for example be embodied in the form of a complete system on chip.
  • the electronic apparatus APP represents the example of a mobile telephone, but it will be apparent to the person skilled in the art that the embodiments of such a system SYS or of such an integrated circuit NVM which were detailed previously can be included with any other known product not described here.
  • the invention is not limited to these embodiments but embraces all variants thereof.
  • N being a non-zero natural integer and M equal to 2 or to 3
  • the slave address of the I 2 C protocol has been described coded on 7 bits
  • the invention is also suited to a slave address coded on 10 bits.

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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US15/842,586 2017-04-12 2017-12-14 Method for addressing a non-volatile memory on I2C bus and corresponding memory device Active 2038-08-06 US11127468B2 (en)

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FR1753214 2017-04-12
FR1753214A FR3065304A1 (fr) 2017-04-12 2017-04-12 Procede d'adressage d'une memoire non-volatile sur un bus i²c et dispositif de memoire correspondant

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FR3065304A1 (fr) 2017-04-12 2018-10-19 Stmicroelectronics (Rousset) Sas Procede d'adressage d'une memoire non-volatile sur un bus i²c et dispositif de memoire correspondant
FR3097987A1 (fr) * 2019-06-26 2021-01-01 STMicroelectronics (Alps) SAS Procede d’adressage d’un circuit integre sur un bus et dispositif correspondant
JP7379888B2 (ja) * 2019-07-08 2023-11-15 オムロン株式会社 制御システム、および制御方法
FR3116146B1 (fr) * 2020-11-12 2023-12-01 St Microelectronics Rousset Procédé de gestion d’une opération de modification du contenu mémorisé d’un dispositif de mémoire, et dispositif de mémoire correspondant
FR3120267B1 (fr) * 2021-02-26 2024-03-15 St Microelectronics Rousset Communication sur bus I2C
CN119248586B (zh) * 2024-09-18 2025-09-26 中国兵器工业集团第二一四研究所苏州研发中心 一种基于i2c接口ip验证的寻址模式可灵活配置的仿真验证模型

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CN108694140A (zh) 2018-10-23

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