US12547883B2 - Neural network circuit and neural network system - Google Patents

Neural network circuit and neural network system

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US12547883B2
US12547883B2 US17/882,360 US202217882360A US12547883B2 US 12547883 B2 US12547883 B2 US 12547883B2 US 202217882360 A US202217882360 A US 202217882360A US 12547883 B2 US12547883 B2 US 12547883B2
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neural network
circuit
computation
output
precision
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US20220374694A1 (en
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Bin Gao
Qi Liu
Leibin Ni
Kanwen Wang
Huaqiang Wu
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Tsinghua University
Huawei Technologies Co Ltd
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Tsinghua University
Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0495—Quantised networks; Sparse networks; Compressed networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/56—Input signal compared with linear ramp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the subject matter and the claimed invention were made by or on the behalf of Tsinghua University, of Haidian District, Beijing, P.R. China and Huawei Technologies Co., Ltd., of Shenzhen, Guangdong province, P.R. China, under a joint research agreement titled “NEURAL NETWORK CIRCUIT AND NEURAL NETWORK SYSTEM”.
  • the joint research agreement was in effect on or before the claimed invention was made, and that the claimed invention was made as a result of activities undertaken within the scope of the joint research agreement.
  • This application relates to the field of artificial intelligence, and specifically, to a neural network circuit and a neural network system.
  • a neural network is a tool to realize artificial intelligence and has characteristics such as a high computation amount and intensive memory access when processing input data.
  • a method for improving processing efficiency of a neural network is to deploy the neural network by using an in-memory computing architecture. According to the method, a weight is written into a computing storage medium in advance based on a feature that the weight remains unchanged during computing of the neural network, and weight storage and computation are completed simultaneously. This can reduce consumption of time and energy caused by data exchange and computation.
  • a neural network computation array is a core module of a neural network circuit.
  • a neural network computation array may also be referred to as a computation array.
  • a multiply-add computation array constructed by a non-volatile storage medium usually includes several rows and columns. The row may also be referred to as a wordline, and the column may also be referred to as a bitline.
  • An intersection of a row and a column is a computation storage cell of a computation array, or a cell for short.
  • a weight is stored in a cell in advance in a form of conductance. After being processed by a digital-to-analog converter (DAC), input data enters a computation array in a form of voltage.
  • DAC digital-to-analog converter
  • a sum of obtained currents may represent an accumulation result of products of the input data and the weight.
  • the current further needs to be processed by an analog-to-digital converter (ADC) and restored to a digital signal.
  • ADC analog-to-digital converter
  • the DAC and the ADC cannot adapt to changes in computation precision of the neural network due to their fixed precision. Consequently, the following problems are caused: In an existing neural network circuit, a computation precision requirement cannot be met in a case of low precision of, and a waste of power consumption is caused in a case of high precision.
  • This application provides a neural network circuit and a neural network system, to adjust output precision of the neural network circuit based on computation precision of the neural network, so that the output precision of the neural network circuit adapts to a change of the computation precision of the neural network.
  • a neural network circuit including a first neural network computation array, a first sample-and-hold circuit, a reference voltage generation circuit, a first comparator circuit, and a first output circuit.
  • the first neural network computation array includes a first group of computation units.
  • the first group of computation units is configured to perform neural network computation on a first part of input data based on a weight, to obtain a first output current.
  • the first sample-and-hold circuit is connected to the first group of computation units, and is configured to generate a first analog voltage based on the first output current.
  • the reference voltage generation circuit is configured to generate a reference voltage based on a first control signal.
  • the first control signal is determined based on first computation precision, and the first control signal varies with the first computation precision.
  • the first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit, and is configured to output a first level signal based on the first analog voltage and the reference voltage.
  • the first output circuit is configured to sample the first level signal based on a second control signal, and output a first computation result.
  • the first computation result is a computation result that meets the first computation precision, and the second control signal is for controlling a frequency at which the first output circuit samples the first level signal.
  • the first computation precision changes accordingly. For example, a larger first output current requires higher precision of the neural network.
  • the neural network circuit may improve precision of the first computation result by increasing the sampling frequency of the first output circuit and extending duration of the first level signal, to meet the precision requirement of the neural network. This avoids the following problems: A computation precision requirement cannot be met in a case of low precision of an existing neural network, and a waste of power consumption is caused in a case of high precision.
  • the neural network circuit further includes a parameter adjustment circuit, configured to generate the first control signal and the second control signal based on the first computation precision.
  • the first level signal when the first analog voltage is higher than the reference voltage, the first level signal is a high-level signal; and when the first analog voltage is lower than the reference voltage, the first level signal is a low-level signal.
  • the first neural network computation array further includes a second group of computation units.
  • the second group of computation units is configured to perform neural network computation on a second part of data based on a weight, to obtain a second output current.
  • the neural network circuit further includes a second sample-and-hold circuit, a second comparator circuit, and a second output circuit.
  • the second sample-and-hold circuit is connected to the second group of computation units, and is configured to generate a second analog voltage based on the second output current.
  • the second comparator circuit is connected to the second sample-and-hold circuit and the reference voltage generation circuit, and is configured to output a second level signal based on the second analog voltage and the reference voltage.
  • the second output circuit is configured to sample the second level signal based on the second control signal, and output a second computation result.
  • the second computation result is a computation result that meets the first computation precision
  • the second control signal is for controlling a frequency at which the second output circuit samples the second level signal.
  • a plurality of groups of computation units may share one parameter adjustment circuit and one reference voltage generation circuit. This reduces a quantity of components and power consumption.
  • the neural network circuit further includes a second neural network computation array.
  • the first output circuit is connected to an input end of the second neural network computation array, and the second neural network computation array is configured to compute, based on a weight, data input into the second neural network computation array.
  • the data input into the second neural network computation array includes the first computation result, and the first computation result is a pulse signal.
  • the first computation result When the first computation result is a pulse signal, the first computation result can be used by another computation array without conversion processing, and no components such as a register and a shift accumulator are required. This reduces a quantity of components and power consumption required for conversion processing.
  • the reference voltage is a ramp voltage.
  • an initial voltage of the reference voltage is controlled by the first control signal.
  • the first level signal (COMP_OUT) output by the first comparator circuit maintains a ReLU functional relationship with an input current (Current_IN) of the first sample-and-hold circuit, so that the first comparator circuit has a function of the ReLU function. Therefore, in this embodiment, the function of the ReLU function can be implemented without an additional component.
  • the parameter adjustment circuit is further configured to generate a third control signal based on the first computation precision.
  • the third control signal is for controlling a reference current of an operational amplifier OPA in the first sample-and-hold circuit, to control precision of the first analog voltage and power consumption of the first sample-and-hold circuit.
  • the OPA can operate under action of the control signal generated by the parameter adjustment circuit.
  • the control signal is for controlling a reference current of the OPA, to reduce power consumption on a premise that a precision requirement of an output voltage of the first sample-and-hold circuit is met.
  • the parameter adjustment circuit is further configured to control a sampling start time point of the first output circuit.
  • an output result of the first output circuit and an output current of the first sample-and-hold circuit present a normal ReLU functional relationship.
  • the output result of the first output circuit and the output current of the first sample-and-hold circuit present a bias ReLU functional relationship. Therefore, in this embodiment, a function of a normal ReLU function or a function of a biased ReLU function can be implemented without additional components.
  • a neural network system including: the neural network circuit according to any one of the first aspect and the implementations of the first aspect; a memory configured to store input data, and a processor, configured to read the input data from the memory, and input the input data into the neural network circuit, so that the neural network circuit performs neural network computation on the input data.
  • the first computation precision changes accordingly. For example, a larger first output current requires higher precision of the neural network.
  • the neural network circuit may improve precision of the first computation result by increasing the sampling frequency of the first output circuit and extending duration of the first level signal, to meet the precision requirement of the neural network.
  • the neural network system including the neural network circuit can avoid the following problems: A computation precision requirement cannot be met in a case of low precision, and a waste of power consumption is caused in a case of high precision.
  • the memory is further configured to store a computer program.
  • the processor is further configured to invoke the computer program from the memory, to program a neural network computation array in the neural network circuit.
  • the programming is for configuring a weight of the neural network.
  • FIG. 1 is a schematic diagram of a structure of a neural network system according to this application.
  • FIG. 2 is a schematic diagram of some neural network layers in a neural network according to this application.
  • FIG. 3 is a schematic diagram of a structure of a neural network circuit according to this application.
  • FIG. 4 is a schematic diagram of a structure of a computation array according to this application.
  • FIG. 5 is a schematic diagram of an operating time sequence of a neural network circuit according to this application.
  • FIG. 6 is a schematic diagram of a structure of another neural network circuit according to this application.
  • FIG. 7 is a schematic diagram of a level signal generation method according to this application.
  • FIG. 8 is a schematic diagram of another level signal generation method according to this application.
  • FIG. 9 is a schematic diagram of still another level signal generation method according to this application.
  • FIG. 10 is a schematic diagram of an output result of a comparator circuit according to this application.
  • FIG. 11 is a schematic diagram of an output result of an output circuit according to this application.
  • FIG. 12 is a schematic diagram of a structure of a neural network circuit including a plurality of groups of computation units according to this application;
  • FIG. 13 A and FIG. 13 B are a schematic diagram of a structure of a neural network circuit applicable to a multilayer neural network according to this application.
  • FIG. 14 is a schematic diagram of an operating time sequence of another neural network circuit according to this application.
  • An artificial neural network referred to as a neural network (NN) or a neural-like network for short, is a mathematical model or a computational model that mimics a structure and function of a biological neural network (a central nervous system of an animal, especially a brain) in the field of machine learning and cognitive science, and is for function estimation or approximation.
  • the artificial neural network may include neural networks such as a convolutional neural network (CNN), a deep neural network (DNN), and a multilayer perceptron (MLP).
  • FIG. 1 is a schematic diagram of a structure of a neural network system according to an embodiment of the present invention. As shown in FIG. 1 , the neural network system 100 may include a host 105 and a neural network circuit 110 .
  • the neural network circuit 110 is connected to the host 105 through a host interface.
  • the host interface may include a standard host interface and a network interface.
  • the host interface may include a peripheral component interconnect express (PCIe) interface.
  • PCIe peripheral component interconnect express
  • the neural network circuit 110 may be connected to the host 105 by using a PCIe bus 106 . Therefore, data may be input to the neural network circuit 110 by using the PCIe bus 106 , and data that is obtained through processing performed by the neural network circuit 110 is received by using the PCIe bus 106 .
  • the host 105 may monitor an operating status of the neural network circuit 110 through the host interface.
  • the host 105 may include a processor 1052 and a memory 1054 . It should be noted that, in addition to the components shown in FIG. 1 , the host 105 may further include other components such as a communication interface and a magnetic disk used as an external memory. This is not limited herein.
  • the processor 1052 is a computation core and control core of the host 105 .
  • the processor 1052 may include a plurality of processor cores.
  • the processor 1052 may be a very large scale integrated circuit.
  • An operating system and another software program are installed in the processor 1052 , so that the processor 1052 can access the memory 1054 , a cache, a magnetic disk, and a peripheral device (e.g., the neural network circuit in FIG. 1 ).
  • the core of the processor 1052 may be, for example, a central processing unit (CPU) or another application-specific integrated circuit (ASIC).
  • CPU central processing unit
  • ASIC application-specific integrated circuit
  • the memory 1054 is a main memory of the host 105 .
  • the memory 1054 is connected to the processor 1052 through a double data rate (DDR) bus.
  • the memory 1054 is usually configured to store various software running in the operating system, input data and output data, information exchanged with an external memory, and the like. To increase an access speed of the processor 1052 , the memory 1054 needs to have an advantage of a high access rate.
  • a dynamic random access memory (DRAM) is usually used as the memory 1054 .
  • the processor 1052 can access the memory 1054 at a high speed by using a memory controller (not shown in FIG. 1 ), and perform a read operation and a write operation on any storage cell in the memory 1054 .
  • the neural network circuit 110 is a chip array including a plurality of neural network chips.
  • the neural network circuit 110 includes a plurality of neural network chips (chip, C) 115 for data processing and a plurality of routers (router, R) 120 .
  • the neural network chip 115 in this application is referred to as a chip 115 for short in this embodiment of the present invention.
  • the plurality of chips 115 are connected to each other through the routers 120 .
  • one chip 115 may be connected to one or more routers 120 .
  • the plurality of routers 120 may form one or more network topologies. Data transmission may be performed between the chips 115 by using the plurality of network topologies.
  • the neural network system 100 shown in FIG. 1 is an example of the neural network system provided in this application, and should not be construed as a limitation on the protection scope of this application.
  • the neural network system applicable to this application may further include more circuits or fewer circuits.
  • the neural network chips may be directly connected without a router.
  • a neural network may include a plurality of neural network layers.
  • the neural network layer is a logical layer, and one neural network layer means that one neural network operation is to be performed. Computation of each neural network layer is implemented by a computing node.
  • the neural network layer may include a convolutional layer, a pooling layer, and the like.
  • the neural network may include n neural network layers (which may also be referred to as n layers of neural networks), where n is an integer greater than or equal to 2.
  • FIG. 2 shows some neural network layers in the neural network.
  • the neural network 200 may include a first layer 202 , a second layer 204 , a third layer 206 , a fourth layer 208 , a fifth layer 210 to an n th layer 212 .
  • the first layer 202 may perform a convolution operation
  • the second layer 204 may perform a pooling operation on output data of the first layer 202
  • the third layer 206 may perform a convolution operation on output data of the second layer 204
  • the fourth layer 208 may perform a convolution operation on an output result of the third layer 206
  • the fifth layer 210 may perform a summation operation on the output data of the second layer 204 and output data of the fourth layer 208 , and the like.
  • FIG. 2 shows only a simple example of neural network layers in a neural network, and does not constitute a limitation on a specific operation of each neural network layer.
  • the fourth layer 208 may perform a pooling operation
  • the fifth layer 210 may perform another neural network operation such as a convolution operation or a pooling operation.
  • a computation result of the i th layer is temporarily stored in a preset cache.
  • a computation unit needs to load the computation result of the i th layer and a weight of the (i+1) th layer from the preset cache to perform computation.
  • the i th layer is any layer in the neural network.
  • the neural network circuit for example a neural network chip C in FIG. 1
  • the neural network circuit uses a computation array constructed by a non-volatile storage medium. Therefore, a weight may be configured on a cell of the computation array before computation.
  • a computation result can be directly sent to a next layer for pipeline computation. Therefore, each neural network layer only needs to cache very little data. For example, each neural network layer needs to cache input data enough only for one time of window computing.
  • FIG. 3 shows a neural network circuit including a computation array.
  • the neural network circuit 300 includes: an input circuit 301 , configured to store input data of a neural network, and send the input data to a drive circuit 302 ; the drive circuit 302 , connected to the input circuit 301 , and configured to convert the input data into a voltage signal that can be applied to a first computation array 303 ; the first computation array 303 , connected to the drive circuit 302 , and configured to generate an output current based on the voltage signal input by the drive circuit 302 and a pre-stored weight; a first sample-and-hold circuit 305 , connected to a first group of computation units in the first computation array 303 , and configured to generate a first analog voltage based on a first output current, where the first group of computation units may belong to one column of computation units, or may belong to a plurality of columns of computation units; a parameter adjustment circuit 304 , connected to the input circuit 301 and the first sample-and-hold circuit 305 , and configured
  • a circuit in the neural network circuit 300 other than the input circuit 301 , the drive circuit 302 , and the first computation array 303 may be referred to as a neuron core circuit.
  • circuits are an example, and is merely a logical function division. In actual implementation, another division manner may be used.
  • the foregoing circuits and a connection relationship between the circuits are examples rather than limitations. A person skilled in the art can reconstruct the neural network circuit 300 without creative efforts.
  • one circuit may be integrated into another circuit, and the connection relationship changes accordingly.
  • the drive circuit 302 may be integrated into the input circuit 301 ; in this case, the first computation array 303 is connected to the input circuit 301 .
  • the first comparator circuit 307 may be integrated into the first sample-and-hold circuit 305 ; in this case, the first output circuit 308 and the reference voltage generation circuit 306 are separately connected to the first sample-and-hold circuit 305 .
  • some circuits may be removed.
  • the parameter adjustment circuit 304 may be removed, and another circuit in the neural network circuit 300 may operate based on a control signal input externally or information preset internally.
  • first and second are for indicating different individuals of a same type.
  • first comparator circuit 307 and a second comparator circuit described below indicate two different comparator circuits. There is no other limitation on the terms.
  • the neural network circuit 300 may be a submodule of the neural network circuit 110 in the neural network system 100 shown in FIG. 1 (that is, the neural network circuit 300 is the neural network chip C in FIG. 1 ).
  • the neural network system 100 may first program the first computation array 303 , that is, complete mapping from a weight of the neural network to a conductance value.
  • the input circuit 301 may send the input data to the drive circuit 302 through time division.
  • 1-bit (bit) information is sent in each clock cycle. For example, if the input data is 10, the input circuit 301 may send 1 in 10 consecutive clock cycles, and send 0 in all clock cycles after the 10 consecutive clock cycles. This output method is called rate-coding.
  • the drive circuit 302 may convert 1 and 0 into voltage signals and load the voltage signals onto the first computation array 303 .
  • the first sample-and-hold circuit 305 accumulates currents in time domain output by the first group of computation units in the first computation array 303 until the input data is input.
  • the first computation array 303 may operate simultaneously with the drive circuit 302 .
  • the following describes, with reference to FIG. 4 , an operating process in which the first computation array 303 performs an operation based on the weight of the neural network and the input data.
  • a weight is usually for indicating importance of input data to output data.
  • a weight is usually represented by using a matrix. As shown in Table 1, a matrix of j rows and k columns shown in Table 1 may be a weight of a neural network layer, and each element in the matrix represents one weight value.
  • the weight may be configured on the first computation array in advance.
  • an element in a matrix is configured in a cell of a computation array, and one element is configured for each cell.
  • a multiply-add operation can be performed on the input data and a matrix representing a weight by using the computation array.
  • FIG. 4 shows a structure of a computation array.
  • One computation array may include a plurality of cells, such as G 1,1 and G 2,1 . Cells are located at row-column intersections. If one computation array includes 1000 rows and 1000 columns, there are one million cells in the computation array.
  • the weight shown in Table 1 may be input into the computation array through bitlines (an input port 402 in FIG. 4 ) of the computation array shown in FIG. 4 , so that each weight value in the weight is configured into a corresponding cell. For example, the weight value W 0,0 in Table 1 is configured into G 1,1 in FIG. 4 , and the weight value W 1,0 in Table 1 is configured into G 2,1 in FIG. 4 .
  • a computation array in which a weight is stored may also be referred to as a synaptic array.
  • the computation array shown in FIG. 4 is a 1T1R array.
  • 1T1R means that each cell has one transmit end and one receive end.
  • a computation array applicable to this application may alternatively be a 1T2R array, a 2T2R array, or another type of array.
  • the first comparator circuit 307 and the reference voltage generation circuit 306 start to operate. At the same time, the first output circuit 308 is also operating.
  • FIG. 5 shows an operating time sequence of each circuit in the neural network circuit 300 .
  • a precision requirement of the neural network varies with a magnitude of the current output by the first group of computation units.
  • a larger current output by the first group of computation units requires higher precision of the neural network.
  • the parameter adjustment circuit 304 may improve precision of the first computation result based on the control signal by increasing a sampling frequency of the first output circuit 308 and extending duration of the first level signal, to meet the precision requirement of the neural network.
  • the parameter adjustment circuit 304 may generate a control signal X 1 and a control signal X 2 based on the computation precision B.
  • the control signal X 1 controls the reference voltage generation circuit 306 to generate a reference voltage, so that the first comparator circuit 307 generates a voltage signal with longer duration after comparing the first analog voltage with the reference voltage. In this way, the first output circuit 308 can sample more information.
  • the control signal X 2 may control the first output circuit 308 to increase the sampling frequency, and sample more information per unit time.
  • the output range information is, for example, a quantity of rows enabled by the first computation array and an algorithm requirement.
  • the output range adjustment circuit After obtaining the output range information from an output circuit, the output range adjustment circuit generates a control signal K that controls a switched capacitor.
  • the control signal K is for controlling a switch group (K i0 , K i1 , and K i2 ) in a first sample-and-hold circuit, and switches in the switch group are respectively connected to integration capacitors.
  • the first sample-and-hold circuit 605 may include an operational amplifier (OPA) and an integration capacitor.
  • the integration capacitors are C i0 , C i1 , and C i2 as in FIG. 6 .
  • S&H_OUT is an output voltage (a first analog voltage) of the first sample-and-hold circuit 605
  • Current_IN is an input current of the first sample-and-hold circuit 605
  • A is a linear coefficient.
  • the integration capacitor controlled by the switch group may scale a ratio of an input current to an output voltage of the first sample-and-hold circuit 605 .
  • the linear coefficient A is a scaling multiple of the input current and the output voltage of the first sample-and-hold circuit 605 .
  • the OPA can operate under a control signal L generated by the precision adjustment circuit.
  • the control signal L is for controlling a reference current of the OPA, to reduce power consumption on a premise that a precision requirement on the output voltage of the first sample-and-hold circuit 605 is met. After the reference current decreases, a current of an amplifier of the OPA decreases under mirroring of a current mirror, reducing power consumption of the first sample-and-hold circuit 605 .
  • RST_integ is a reset switch
  • EN_integ is an enable switch
  • V CLP is a clamp voltage
  • the precision information described above is used by the parameter adjustment circuit 604 to generate control signals, for example, the control signal L generated by an OPA current controller and clock control signals (CLK_ramp and CLK_out) generated after a frequency divider (frequency divider) modulates a clock signal (CLK) of a neural network system.
  • the OPA current controller and the frequency divider may be referred to as precision adjustment modules.
  • the function of the control signal L has been described above, and a function of the clock control signal is described in detail below.
  • the clock control signal K is for controlling a ramp voltage generated by a ramp voltage generation circuit 606 .
  • the ramp voltage generation circuit 606 is an example of the reference voltage generation circuit 306 described above.
  • the ramp voltage output by the ramp voltage generation circuit 606 and the first analog voltage output by the first sample-and-hold circuit 605 are used by the first comparator circuit 607 to generate the first level signal.
  • An operating principle of the first comparator circuit 607 is as follows:
  • the first level signal is a high-level signal.
  • the first level signal is a low-level signal.
  • FIG. 7 to FIG. 9 are several examples in which the first comparator circuit generates a first level signal based on a ramp voltage and a first analog voltage.
  • V represents a voltage
  • t represents time
  • S&H_OUT represents the first analog voltage output by the first sample-and-hold circuit 605
  • Ramp_OUT represents the ramp voltage output by the ramp voltage generation circuit 606
  • COMP_OUT represents the first level signal output by the first comparator circuit 607
  • Neuron_OUT represents the first computation result obtained after a first output circuit 608 samples the first level signal.
  • values of the first analog voltages are the same.
  • a slope of Ramp_OUT in FIG. 7 is less than a slope of Ramp_OUT in FIG. 8 .
  • duration of COMP_OUT in FIG. 7 is longer than duration of COMP_OUT in FIG. 8 .
  • frequencies at which the first output circuit 608 samples COMP_OUT are the same, an information amount of Neuron_OUT in FIG. 7 is greater than an information amount of Neuron_OUT in FIG. 8 .
  • the slope of the ramp voltage is controlled by the clock control signal CLK_ramp. It can be learned that the parameter adjustment circuit 604 can control the output precision of the neural network circuit shown in FIG. 6 . In addition, longer duration of the high-level signal leads to higher power consumption. Therefore, the parameter adjustment circuit 604 can further control the power consumption of the neural network circuit shown in FIG. 6 by controlling the slope of the ramp voltage.
  • the slope of Ramp_OUT in FIG. 7 is the same as a slope of Ramp_OUT in FIG. 9 . Therefore, the duration of COMP_OUT in FIG. 7 is the same as duration of COMP_OUT in FIG. 9 .
  • a frequency in FIG. 7 at which the first output circuit 608 samples COMP_OUT is greater than the frequency in FIG. 9 at which the first output circuit 608 samples COMP_OUT. Therefore, an information amount of Neuron_OUT in FIG. 7 is greater than an information amount of Neuron_OUT in FIG. 9 .
  • the sampling frequency of the first output circuit 608 is controlled by the clock control signal CLK_out. It can be learned that the parameter adjustment circuit 604 can control the output precision of the neural network circuit shown in FIG. 6 . In addition, a higher sampling frequency leads to higher power consumption. Therefore, the parameter adjustment circuit 604 can further control the power consumption of the neural network circuit shown in FIG. 6 by controlling the sampling frequency.
  • the parameter adjustment circuit 604 may control the output precision and the power consumption of the neural network circuit in FIG. 6 by using both CLK_ramp and CLK_out, or may control the output precision and the power consumption of the neural network circuit by using either CLK_ramp or CLK_out.
  • the power consumption can be reduced on the premise of satisfying the output precision of the neural network circuit.
  • the parameter adjustment circuit 604 may further control a sampling start time point of the first output circuit 608 .
  • the initial voltage control circuit After the initial voltage control circuit obtains the initial voltage information from the input circuit 601 , the initial voltage control circuit outputs a voltage signal and applies it to a DAC of the ramp voltage generation circuit 606 , to control an initial voltage of the ramp voltage.
  • the DAC is a segmented switched-capacitor DAC and is configured to generate a ramp voltage.
  • C 0 to C 9 are segmented switched-capacitors in the DAC, and C 1 to C 9 may be connected to the ground (GND) under control of switches.
  • the ramp voltage generation circuit 606 further includes a counter. A bit width of the counter is, for example, 8 bits. 256 types of control signals may be output under control of CLK_ramp. As shown in S 1 to S 8 , S 1 to S 8 are for controlling switches corresponding to C 1 to C 9 , to adjust the slope of the ramp voltage.
  • the first comparator circuit 607 can output COMP_OUT in FIG. 10 , that is, COMP_OUT maintains a ReLU functional relationship with an input current Current_IN of the first sample-and-hold circuit 605 .
  • the first comparator circuit 605 has a function of a ReLU function.
  • FIG. 11 shows a relationship between Neuron_OUT and Current_IN generated by the first output circuit 608 , and a forward biased ReLU functional relationship is presented.
  • the delay means that sampling starts after the control signal of the parameter adjustment circuit 604 is received, and sampling is not performed on the first level signal before the control signal.
  • the first output circuit 608 may further advance the sampling start time point under the control of the parameter adjustment circuit 604 , so that Neuron_OUT and Current_IN present a reverse biased ReLU functional relationship.
  • the neural network circuit shown in FIG. 6 further includes the first output circuit 608 .
  • the first output circuit 608 can output two results: One is a data signal Y 1 output by the counter, and the other is a pulse signal Y 0 .
  • Y 0 may be generated based on Y 1 .
  • the bit width of the counter is 8 bits, there may be eight precision choices for Y 1 , as ⁇ 0:7> in FIG. 6 .
  • the input signal of the first computation array is usually a pulse signal.
  • the first output circuit 608 may output Y 0 .
  • the result output by the first output circuit 608 can be used by the another computation array without conversion processing. Therefore, components such as a register and a shift accumulator are not needed. This reduces a quantity of components and power consumption required for conversion processing.
  • FIG. 13 A and FIG. 13 B show this embodiment.
  • a first output circuit 1308 outputs Y 0
  • Y 0 may be directly loaded onto a second computation array 13114 by a drive circuit 1313 of a second neural network circuit. Therefore, an input circuit 1312 of the second neural network circuit in FIG. 13 B is an optional module.
  • the first output circuit 608 may output YT.
  • FIG. 12 shows a neural network circuit provided in this application.
  • a first computation array 1203 includes a plurality of groups of computation units, for example, a first group of computation units and a second group of computation units.
  • the first group of computation units and the second group of computation units compute different input data based on weights, and output different output currents.
  • the second group of computation units outputs a second output current to a second sample-and-hold circuit 1209 .
  • the second sample-and-hold circuit 1209 converts the second output current into a second analog voltage under control of a control signal L and a control signal K.
  • a second comparator circuit 1210 outputs a second level signal based on the second analog voltage and a reference voltage (for example, a ramp voltage).
  • a second output circuit 1211 samples the second level signal to generate a second computation result.
  • different groups of computation units in the first computation array 1203 use different sample-and-hold circuits, comparator circuits, and output circuits, and a parameter adjustment circuit 1204 and a reference voltage generation circuit 1206 are shared by all groups of computation units. This reduces a quantity of components and power consumption.
  • the neural network circuit shown in FIG. 12 is a circuit applicable to a single-layer neural network.
  • another circuit may be connected to the neural network circuit shown in FIG. 12 , to meet a requirement of a multilayer neural network.
  • FIG. 13 A and FIG. 13 B are a schematic diagram of a circuit applicable to a multilayer neural network.
  • a first neural network circuit is, for example, the circuit shown in FIG. 12 .
  • An input bit width of the first neural network circuit is M, a scale of a first computation array is M*N, and there are N output neurons (that is, N output circuits).
  • An input bit width of a second neural network circuit is N, a scale of a second computation array is N*K, and there are K output neurons (that is, K output circuits).
  • the output neurons of the second neural network circuit may further be connected to another neural network circuit.
  • FIG. 14 shows an operating time sequence of the circuit in FIG. 13 A and FIG. 13 B .
  • a reference voltage generation circuit, a comparator circuit, and an output circuit of the first neural network circuit operate, an input circuit, a drive circuit, a computation array, and a sample-and-hold circuit of the second neural network circuit also operate.
  • An optional workflow is as follows:
  • an input circuit 1301 of the first neural network circuit outputs input data in a rate-coding manner, where required time is determined by a data amount and a signal bit width.
  • a drive circuit 1302 , a first computation array 1303 , and each sample-and-hold circuit of the first neural network circuit start to operate.
  • the first computation array 1303 performs a multiply-add operation on the input data and weights stored in the first computation array 1303 .
  • An operation result is output after being processed by each sample-and-hold circuit.
  • each comparator circuit In a third step of the first neural network circuit, the reference voltage generation circuit 1306 , each comparator circuit, and each output circuit start to operate, to output a first computation result.
  • the input circuit 1312 of the second neural network circuit samples the first computation result of the first neural network circuit, and outputs a sampling result.
  • the drive circuit 1313 of the second neural network converts the sampling result in the previous step into an analog voltage signal and applies it to a second computation array 1314 .
  • the second computation array 1314 performs a multiply-add operation on the input data and weights stored in the second computation array 1314 .
  • An operation result is output after being processed by each sample-and-hold circuit. Time of 1 -S 3 , 2 -S 1 , and 2 -S 2 coincide.
  • a reference voltage generation circuit 1317 , each comparator circuit, and each output circuit of the second neural network circuit start to operate, to output a second computation result.
  • the neural network system outputs a final computation result.
  • precision of the first neural network circuit and the second neural network circuit may be represented by N1 and N2.
  • the first neural network circuit may output 2 N1 pulses, where each pulse serves as an input for the second neural network circuit.
  • the second neural network circuit may output 2 N2 pulses. Therefore, output precision of the second neural network circuit is (N1+N2) bits.
  • precision of each of ramp voltages of the first neural network circuit and the second neural network circuit is 8 bits.
  • both N1 and N2 are 1-8 bits
  • an output precision range of the second neural network circuit is 2-16 bits.
  • the foregoing describes in detail examples of the neural network circuit and the neural network system that are provided in this application.
  • the neural network circuit and the neural network system each include a corresponding hardware structure and/or software module for performing each function.
  • a person skilled in the art may be easily aware that this application can be implemented in a form of hardware or a combination of hardware and computer software with reference to the disclosed embodiments of this specification. Whether a specific function is performed by hardware or hardware driven by computer software depends on particular applications and design constraints of the technical solutions. A person skilled in the art may use different methods to implement the described functions for each particular application, but it should not be considered that the implementation goes beyond the scope of this application.
  • the disclosed system, apparatus and method may be implemented in other manners. For example, some features of the method embodiments described above may be ignored or not performed.
  • the described apparatus embodiments are merely examples. Division into the units is merely logical function division and may be other division in actual implementation. A plurality of units or components may be combined or integrated into another system.
  • coupling between the units or coupling between the components may be direct coupling or indirect coupling, and the coupling may include an electrical connection, a mechanical connection, or another form of connection.

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