US20030151753A1 - Methods and apparatuses for use in switching between streaming video bitstreams - Google Patents

Methods and apparatuses for use in switching between streaming video bitstreams Download PDF

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US20030151753A1
US20030151753A1 US10/185,741 US18574102A US2003151753A1 US 20030151753 A1 US20030151753 A1 US 20030151753A1 US 18574102 A US18574102 A US 18574102A US 2003151753 A1 US2003151753 A1 US 2003151753A1
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bitstream
switching
recited
quantization parameter
computer
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Shipeng Li
Feng Wu
Xiaoyan Sun
Goubin Shen
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Microsoft Technology Licensing LLC
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Priority to EP02028649A priority patent/EP1337111A3/fr
Priority to JP2003018057A priority patent/JP2003244700A/ja
Priority to KR10-2003-0007895A priority patent/KR20030067589A/ko
Priority to JP2003032872A priority patent/JP2003283340A/ja
Publication of US20030151753A1 publication Critical patent/US20030151753A1/en
Priority to US12/472,266 priority patent/US8576919B2/en
Priority to US14/071,540 priority patent/US9686546B2/en
Assigned to MICROSOFT TECHNOLOGY LICENSING, LLC reassignment MICROSOFT TECHNOLOGY LICENSING, LLC ASSIGNMENT OF ASSIGNOR'S INTEREST Assignors: MICROSOFT CORPORATION
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/234—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
    • H04N21/23424—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving splicing one content stream with another content stream, e.g. for inserting or substituting an advertisement
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H04N19/126—Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/577—Motion compensation with bidirectional frame interpolation, i.e. using B-pictures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/234—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
    • H04N21/2343—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
    • H04N21/23439—Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements for generating different versions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/25—Management operations performed by the server for facilitating the content distribution or administrating data related to end-users or client devices, e.g. end-user or client device authentication, learning user preferences for recommending movies
    • H04N21/266—Channel or content management, e.g. generation and management of keys and entitlement messages in a conditional access system, merging a VOD unicast channel into a multicast channel
    • H04N21/2662—Controlling the complexity of the video stream, e.g. by scaling the resolution or bitrate of the video stream based on the client capabilities

Definitions

  • This invention relates to data bitstreams, and more particularly to methods and apparatuses for switching between different streaming bitstreams.
  • a video sequence is compressed into several non-scalable bitstreams at different bit rates.
  • Some special frames known as key frames, are either compressed without prediction or coded with an extra switching bitstream.
  • Key frames provide access points to switch among these bitstreams to fit in the available bandwidth.
  • One advantage of this method is the high coding efficiency with non-scalable bitstreams.
  • this method only provides coarse and sluggish capability in adapting to channel bandwidth variations.
  • a video sequence is compressed into a single scalable bitstream, which can be truncated flexibly to adapt to bandwidth variations.
  • MPEG-4 Fine Granularity Scalable (FGS) coding has become prominent due to its fine-grain scalability. Since the enhancement bitstream can be truncated arbitrarily in any frame, FGS provides a remarkable capability in readily and precisely adapting to channel bandwidth variations.
  • low coding efficiency is the vital disadvantage that prevents FGS from being widely deployed in video streaming applications.
  • Progressive Fine Granularity Scalable (PFGS) coding scheme is a significant improvement over FGS by introducing two prediction loops with different quality references.
  • Improved methods and apparatuses are provided for switching of streaming data bitstreams, such as, for example, used in video streaming and other related applications.
  • Some desired functionalities provided herein include random access, fast forward and fast backward, error-resilience and bandwidth adaptation.
  • the improved methods and apparatuses can be configured to increase coding efficiency of and/or reduce the amount of data needed to encode a switching bitstream.
  • an encoding method includes encoding data into a first bitstream using a first quantization parameter and encoding the data into a second bitstream using a second quantization parameter that is different from the first quantization parameter.
  • the method also includes generating an encoded switching bitstream associated with the first and second bitstreams using the first quantization parameter to support up-switching between the first and second bitstreams and using the second quantization parameter to support down-switching between the first and second bitstreams.
  • An exemplary apparatus includes a first bitstream encoder configured to encode data into an encoded first bitstream using a first quantization parameter and a second bitstream encoder configured to encode the data into an encoded second bitstream using a second quantization parameter that is different from the first quantization parameter.
  • the apparatus also includes a switching bitstream encoder operatively coupled to the first bitstream encoder and the second bitstream encoder and configured to output an encoded switching bitstream that supports up-switching and down-switching between the first encoded bitstream and the second encoded bitstream based on information processed using the first and second quantization parameters.
  • An exemplary decoding method includes receiving at least one encoded bitstream, such as, a first bitstream that was generated using a first quantization parameter and/or a second bitstream that was generated using a second quantization parameter that is different from the first quantization parameter.
  • the received encoded bitstream is decoded.
  • the decoding method further includes receiving an encoded switching bitstream associated with the first and second bitstreams that was generated using the first quantization parameter to support up-switching between the first and second bitstreams and using the second quantization parameter to support down-switching between the first and second bitstreams.
  • the method also includes decoding the received encoded switching bitstream using the first and second quantization parameters.
  • Another exemplary apparatus includes a first decoder configured to decode a first encoded bitstream into a decoded first bitstream using a first quantization parameter and a second decoder configured to decode a second bitstream into a decoded second bitstream using a second quantization parameter that is different from the first quantization parameter.
  • the apparatus also includes a switching bitstream decoder that is operatively coupled to the first decoder and the second decoder and configured to output a decoded switching bitstream that supports up-switching and down-switching between the first decoded bitstream and the second decoded bitstream based on information processed using the first and second quantization parameters.
  • FIG. 1 is a block diagram depicting an exemplary computing environment that is suitable for use with certain implementations of the present invention.
  • FIG. 2 is a diagram illustratively depicting switching between bitstreams, in accordance with certain exemplary implementations of the present invention.
  • FIG. 3 is a block diagram depicting a conventional decoder.
  • FIG. 5 is block diagram depicting an improved decoder, in accordance with certain exemplary implementations of the present invention.
  • FIG. 6 is block diagram depicting an improved encoder, in accordance with certain exemplary implementations of the present invention.
  • FIG. 7 is block diagram depicting an improved decoder, in accordance with certain further exemplary implementations of the present invention.
  • FIG. 8 is block diagram depicting an improved encoder, in accordance with certain further exemplary implementations of the present invention.
  • FIG. 9 is block diagram depicting an improved decoder, in accordance with still other exemplary implementations of the present invention.
  • FIG. 10 is block diagram depicting an improved decoder, in accordance with still other exemplary implementations of the present invention.
  • FIG. 11 is block diagram depicting an improved encoder, in accordance with still other exemplary implementations of the present invention.
  • a similar representative switching process 200 is depicted in the illustrative diagram in FIG. 2. Here, switching is shown as occurring from bitstream 1 to bitstream 2 using SP pictures.
  • the streaming system When switching from bitstream 1 to bitstream 2 , the streaming system does not need to wait for a key frame to start the switching process. Instead, it can switch at the SP frames. At SP frames, the streaming system sends a switching bitstream S 12 , and the decoder decodes the switching bitstream using the same techniques without knowing whether it is S 1 , S 2 or S 12 . Thus, the bitstream switching is transparent to the decoder. The decoded frame will be exactly the same as the reference frame for the next frame prediction in bitstream 2 . As such, there should not be any drifting problems.
  • FIG. 3 and FIG. 4 An exemplary conventional decoder 300 and encoder 400 are depicted in FIG. 3 and FIG. 4, respectively. A more detailed description of the scheme can be found in Kurceren et al. There are some potential issues with the scheme in Kurceren et al.
  • the size of the down-switching bitstream may often be much smaller than that of the up-switching one. Since the high bit-rate bitstream typically contains most of the information of a low bit-rate one, in theory, one should be able to configure the scheme to make the size of switching bitstream sufficiently small.
  • FIG. 5 and FIG. 6 illustrate an improved decoder and encoder, respectively, in accordance with certain implementations of the present invention.
  • the proposed techniques solve the contradiction existing in the scheme proposed in Kurceren et al. so that the down-switching bitstream can be encoded to have significantly reduced, if not minimal, size while the coding efficiency of bitstreams 1 and 2 is also well preserved.
  • the switching points for up-switching and down-switching can be decoupled. This means that one can encode more switching down points than switching-up points, for example, to suit the TCP-friendly protocols, etc. Moreover, such decoupling allows for further improved coding efficiency of the bitstream that the system is switched from, for example, by individually setting the Qs in the reconstruction loop to an appropriately small value.
  • FIG. 7 and FIG. 8 illustrate an exemplary decoder and encoder, respectively, that support both high coding efficiency for the normal bitstreams and a compact size for the switching bitstream.
  • program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.
  • program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.
  • program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.
  • program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.
  • the invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network.
  • program modules may be located in both local and remote memory storage devices.
  • FIG. 1 illustrates an example of a suitable computing environment 120 on which the subsequently described systems, apparatuses and methods may be implemented.
  • Exemplary computing environment 120 is only one example of a suitable computing environment and is not intended to suggest any limitation as to the scope of use or functionality of the improved methods and systems described herein. Neither should computing environment 120 be interpreted as having any dependency or requirement relating to any one or combination of components illustrated in computing environment 120 .
  • the improved methods and systems herein are operational with numerous other general purpose or special purpose computing system environments or configurations.
  • Examples of well known computing systems, environments, and/or configurations that may be suitable include, but are not limited to, personal computers, server computers, thin clients, thick clients, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like.
  • computing environment 120 includes a general-purpose computing device in the form of a computer 130 .
  • the components of computer 130 may include one or more processors or processing units 132 , a system memory 134 , and a bus 136 that couples various system components including system memory 134 to processor 132 .
  • Bus 136 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures.
  • bus architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnects (PCI) bus also known as Mezzanine bus.
  • Computer 130 typically includes a variety of computer readable media. Such media may be any available media that is accessible by computer 130 , and it includes both volatile and non-volatile media, removable and non-removable media.
  • system memory 134 includes computer readable media in the form of volatile memory, such as random access memory (RAM) 140 , and/or non-volatile memory, such as read only memory (ROM) 138 .
  • RAM random access memory
  • ROM read only memory
  • a basic input/output system (BIOS) 142 containing the basic routines that help to transfer information between elements within computer 130 , such as during start-up, is stored in ROM 138 .
  • BIOS basic input/output system
  • RAM 140 typically contains data and/or program modules that are immediately accessible to and/or presently being operated on by processor 132 .
  • Computer 130 may further include other removable/non-removable, volatile/non-volatile computer storage media.
  • FIG. 1 illustrates a hard disk drive 144 for reading from and writing to a non-removable, non-volatile magnetic media (not shown and typically called a “hard drive”), a magnetic disk drive 146 for reading from and writing to a removable, non-volatile magnetic disk 148 (e.g., a “floppy disk”), and an optical disk drive 150 for reading from or writing to a removable, non-volatile optical disk 152 such as a CD-ROM/R/RW, DVD-ROM/R/RW/+R/RAM or other optical media.
  • Hard disk drive 144 , magnetic disk drive 146 and optical disk drive 150 are each connected to bus 136 by one or more interfaces 154 .
  • the drives and associated computer-readable media provide nonvolatile storage of computer readable instructions, data structures, program modules, and other data for computer 130 .
  • the exemplary environment described herein employs a hard disk, a removable magnetic disk 148 and a removable optical disk 152 , it should be appreciated by those skilled in the art that other types of computer readable media which can store data that is accessible by a computer, such as magnetic cassettes, flash memory cards, digital video disks, random access memories (RAMs), read only memories (ROM), and the like, may also be used in the exemplary operating environment.
  • a number of program modules may be stored on the hard disk, magnetic disk 148 , optical disk 152 , ROM 138 , or RAM 140 , including, e.g., an operating system 158 , one or more application programs 160 , other program modules 162 , and program data 164 .
  • the improved methods and systems described herein may be implemented within operating system 158 , one or more application programs 160 , other program modules 162 , and/or program data 164 .
  • a user may provide commands and information into computer 130 through input devices such as keyboard 166 and pointing device 168 (such as a “mouse”).
  • Other input devices may include a microphone, joystick, game pad, satellite dish, serial port, scanner, camera, etc.
  • a user input interface 170 that is coupled to bus 136 , but may be connected by other interface and bus structures, such as a parallel port, game port, or a universal serial bus (USB).
  • USB universal serial bus
  • a monitor 172 or other type of display device is also connected to bus 136 via an interface, such as a video adapter 174 .
  • personal computers typically include other peripheral output devices (not shown), such as speakers and printers, which may be connected through output peripheral interface 175 .
  • Computer 130 may operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 182 .
  • Remote computer 182 may include many or all of the elements and features described herein relative to computer 130 .
  • Logical connections shown in FIG. 1 are a local area network (LAN) 177 and a general wide area network (WAN) 179 .
  • LAN local area network
  • WAN wide area network
  • Such networking environments are commonplace in offices, enterprise-wide computer networks, intranets, and the Internet.
  • computer 130 When used in a LAN networking environment, computer 130 is connected to LAN 177 via network interface or adapter 186 .
  • the computer When used in a WAN networking environment, the computer typically includes a modem 178 or other means for establishing communications over WAN 179 .
  • Modem 178 which may be internal or external, may be connected to system bus 136 via the user input interface 170 or other appropriate mechanism.
  • FIG. 1 Depicted in FIG. 1, is a specific implementation of a WAN via the Internet.
  • computer 130 employs modem 178 to establish communications with at least one remote computer 182 via the Internet 180 .
  • program modules depicted relative to computer 130 may be stored in a remote memory storage device.
  • remote application programs 189 may reside on a memory device of remote computer 182 . It will be appreciated that the network connections shown and described are exemplary and other means of establishing a communications link between the computers may be used.
  • FIGS. 3 - 8 The modules and notations used in FIGS. 3 - 8 are defined as follows:
  • DCT Discrete cosine transform
  • IDCT Inverse discrete cosine transform
  • Entropy Encoding Entropy encoding of quantized coefficients. It could be arithmetic coding or variable length coding.
  • Entropy Decoding Entropy decoding of quantized coefficients. It could be arithmetic decoding or variable length decoding that matches the corresponding modules in the encoder.
  • Q ⁇ 1 Inverse Quantization or dequantization.
  • MC Motion compensation module, where a predicted frame is formed according to the motion vectors and the reference in the frame buffer.
  • ME Motion estimation module, where the motion vectors are searched to best predict the current frame.
  • Loop Filter A smoothing filter in the motion compensation loop to reduce the blocking artifacts.
  • FrameBuffer0 A frame buffer that holds the reference frame for next frame encoding/decoding.
  • P Picture A frame encoded using traditional motion compensated predictive coding.
  • SP Picture A frame encoded as a switching frame using the proposed motion compensated predictive coding.
  • Switching Bitstream The bitstream transmitted to make seamless transition from one bitstream to another.
  • K serr1 QP 1 ⁇ 1 (L err1 ).
  • K rec1 K pred1 +K serr1 .
  • L rec1 Qs(K rec1 ).
  • the levels L rec1 are dequantized using Qs ⁇ 1 and the inverse DCT transform is performed to obtain the reconstructed image.
  • the reconstructed image will go through a loop filter to smooth certain blocky artifacts and output to the display and to the frame buffer for the next frame decoding.
  • the resultant picture is the same as that decoded from S 2 .
  • a drifting-free switching from bitstream 1 to bitstream 2 is achieved.
  • Qs is encoded in the S 12 bitstream.
  • FIG. 4 Reference is now made to FIG. 4 and the exemplary conventional encoding process that is illustrated for encoding of SP frame S 1 or S 2 in a normal bitstream.
  • S 1 is used as an example.
  • DCT transform to the macroblock of the original video is performed, and the obtained coefficients as K ong1 denoted.
  • a DCT transform is performed to the predicted macroblock, and the obtained coefficients as K pred1 denoted.
  • the next step is to quantize K pred1 using Qs and obtain levels L pred1 .
  • L pred1 Qs(K pred1 ).
  • K err1 K orig1 ⁇ K pred1 .
  • L err1 QP 1 (K err1 ).
  • Entropy encoding is performed with L err12 and bitstream S 12 .
  • S 1 is used as an example.
  • the levels of the prediction error coefficients, L err1 , and motion vectors, are generated for the macroblock.
  • Levels L err1 are dequantized using quantizer QP 1 ⁇ 1 ,
  • K serr1 QP 1 ⁇ 1 (L err1 ).
  • L serr1 Qs(K serr1 ).
  • L pred1 Qs 1 (K pred1 ).
  • L pred1 is then dequantized by Qs 1 ⁇ 1 ,
  • K spred1 Qs 1 ⁇ 1 (L pred1 ).
  • L spred1 Qs(K spred1 ).
  • L rec1 L spred1 +L serr1 .
  • the reconstructed image will go through a loop filter to smooth certain blocky artifacts and output to the display and to the frame buffer for next frame decoding.
  • the decoding of switching bitstream S 12 for example, when switching from bitstream 1 to bitstream 2 , follows a similar decoding process similar except that the input is bitstream S 12 , QP 1 ⁇ 1 is replaced by Qs 2 ⁇ 1 , Qs is replaced by Qs 2 , Qs ⁇ 1 is replaced by Qs 2 ⁇ 1 , L rec1 is replaced by L rec2 , L err1 is replaced by L err12 , K serr1 is replaced by K serr12 , and L spred1 is replaced by L spred12 .
  • the resultant picture is the same as that decoded from S 2 .
  • a drifting-free switching from bitstream 1 to bitstream 2 is achieved.
  • S 1 is used as an example.
  • DCT transform is performed to the macroblock of the original video, and the obtained coefficients as K orig1 denoted.
  • K pred1 After motion compensation, DCT transform is performed to the predicted macroblock, and the obtained coefficients denoted as K pred1 . Then K pred1 is quantized using Qs 1 and levels L pred1 obtained,
  • L pred1 Qs 1 (K pred1 ).
  • the next step is to dequantize L pred1 using dequantizer Qs 1 ⁇ 1 ,
  • K spred1 Qs 1 ⁇ 1 (L pred1 ).
  • K err1 K orig1 ⁇ K pred1 .
  • L err1 QP 1 (K err1 ).
  • the encoding of switching bitstream S 12 is based on the encoding of S 1 and S 2 .
  • the process involves quantizing prediction coefficients K spred1 in the S 1 encoder using quantizer Qs 2 .
  • L spred12 Qs 2 (K spred1 ).
  • S 1 is used as an example.
  • Levels L err1 are dequantized using quantizer QP 1 ⁇ 1 :
  • K serr1 QP 1 ⁇ 1 (L err1 ).
  • K rec1 K pred1 +K serr1 .
  • L rec1 Qs 1 (K rec1 ).
  • the levels L rec1 are dequantized using Qs 1 ⁇ 1 and the inverse DCT transform is performed to obtain the reconstructed image.
  • the reconstructed image will go through a loop filter to smooth certain blocky artifacts and output to the display and to the frame buffer for next frame decoding.
  • the decoding of switching bitstream S 12 for example, when switching from bitstream 1 to bitstream 2 , follows a similar decoding process similar except that the input is bitstream S 12 , QP 1 ⁇ 1 is replaced by Qs 2 ⁇ 1 , Qs 1 is replaced by Qs 2 , Qs 1 ⁇ 1 is replaced by Qs 2 ⁇ 1 , K serr1 is replaced by K serr12 , K rec1 is replaced by K rec12 , L rec1 is replaced by L rec2 , and L err1 is replaced by L err12 .
  • the resultant picture is the same as that decoded from S 2 .
  • a drifting-free switching from bitstream 1 to bitstream 2 is achieved.
  • S 1 is used as an example.
  • the process includes subtracting K pred1 from K orig1 and obtaining error coefficients K err1 .
  • K err1 K orig1 ⁇ K pred1 .
  • K err1 is quantized using QP 1 and error levels L err1 obtained,
  • L err1 QP 1 (K err1 ).
  • the process includes reconstructing levels L rec1 and the reference for the next frame encoding. Note that here there is a quantizer Qs 1 and a dequantizer Qs 1 ⁇ 1 in the reconstruction loop.
  • the encoding of switching bitstream S 12 is based on the encoding of S 1 and S 2 .
  • prediction coefficients K pred1 are quantized in the S 1 encoder using quantizer Qs 2 .
  • L pred12 Qs 2 (K pred1 ).
  • the process includes subtracting L pred12 from the reconstructed level L rec2 in S 2 encoder.
  • FIG. 9 is a block diagram depicting a decoder 900 for S 1 and S 2 , in accordance with certain other implementations of the present invention.
  • the quantization Qs is operated on the reconstructed DCT reference rather than on the decoded DCT residue and the DCT prediction.
  • the quantization in this example can be described as:
  • X is the reconstructed DCT coefficient
  • Y is the quantized DCT coefficient
  • A(.) is the quantization table
  • Qs is the quantization step.
  • L err are the levels of the prediction error coefficients
  • K pred are prediction coefficients. This is quite different from that used in conventional SP coding.
  • One advantage is that a high quality display can be reconstructed from the part in [. . . ] of the above formula.
  • decoder 900 provides two ways for reconstructing the display image.
  • the reconstructed reference is directly used for the purpose of display. There is little if any complexity increase in this case.
  • the decoder is powerful enough, another high quality image can be reconstructed for display.
  • This process includes the modules within box 902 . These modules are, for example, non-normative parts for the current JVT standard.
  • FIG. 10 illustrates a decoder 1000 for the switching bitstream S 12 , in accordance with certain further implementations of the present invention.
  • decoder 1000 for the switching bitstream S 12 is slightly different from that for S 1 and S 2 , presented in previous sections.
  • the quantization Qs is only needed on the DCT prediction.
  • the quantization in this example can be described as:
  • Decoder 1000 is configured to know which SP bitstream is received. Therefore, for example, a 1-bit syntax can be employed to notify decoder 1000 .
  • An exemplary modification in the SP syntax and semantic include a Switching Bitstream Flag (e.g., 1 bit) and Quantization parameter (e.g., 5 bits).
  • the 1-bit syntax element “Switching Bitstream Flag” is inserted before the syntax element “Slice Qp”.
  • the Switching Bitstream Flag is 1, the current bitstream is decoded as Bitstream S 12 , and the syntax element “Slice QP” is skipped; otherwise it is decoded as Bitstream S 1 or S 2 , and the syntax element “Slice QP” is the quantization parameter Qp.
  • An encoder 1100 is illustrated in the block diagram of FIG. 11, in accordance with certain further exemplary implementations of the present invention.
  • encoder 1100 includes a switch 1102 .
  • the DCT prediction can be directly subtracted from the original DCT image without quantization and dequantization, or the DCT prediction can be subtracted from the original DCT image after quantization and dequantization. Whether the DCT prediction is quantized or not can be decided, for example, one by one coefficient with rate-distortion criterion.

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JP2003018057A JP2003244700A (ja) 2002-01-25 2003-01-27 スケーラブルビデオビットストリームのシームレスな切換え
KR10-2003-0007895A KR20030067589A (ko) 2002-02-08 2003-02-07 스트리밍 비디오 비트스트림들간의 스위칭에 사용하기위한 방법 및 장치
JP2003032872A JP2003283340A (ja) 2002-02-08 2003-02-10 符号化方法及び復号化方法
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EP1337111A3 (fr) 2006-07-12
US20140086308A1 (en) 2014-03-27
EP1337111A2 (fr) 2003-08-20
US8576919B2 (en) 2013-11-05
US9686546B2 (en) 2017-06-20

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