US20090184733A1 - Layout method for soft-error hard electronics, and radiation hardened logic cell - Google Patents

Layout method for soft-error hard electronics, and radiation hardened logic cell Download PDF

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Publication number
US20090184733A1
US20090184733A1 US12/354,655 US35465509A US2009184733A1 US 20090184733 A1 US20090184733 A1 US 20090184733A1 US 35465509 A US35465509 A US 35465509A US 2009184733 A1 US2009184733 A1 US 2009184733A1
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nets
circuit
single event
net
contact area
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Klas Olof Lilja
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Publication of US20090184733A1 publication Critical patent/US20090184733A1/en
Priority to US12/763,139 priority patent/US8495550B2/en
Assigned to UNITED STATES GOVERNMENT; DEFENSE THREAT REDUCTION AGENCY reassignment UNITED STATES GOVERNMENT; DEFENSE THREAT REDUCTION AGENCY CONFIRMATORY LICENSE (SEE DOCUMENT FOR DETAILS). Assignors: LILJA, KLAS O, ROBUST CHIP INC.
Priority to US13/277,135 priority patent/US8566770B2/en
Priority to US13/425,231 priority patent/US8468484B2/en
Priority to US13/463,688 priority patent/US20130038348A1/en
Priority to US13/463,706 priority patent/US20130227499A1/en
Priority to US13/692,800 priority patent/US9083341B2/en
Priority to US14/026,648 priority patent/US9081926B2/en
Priority to US14/060,162 priority patent/US20140157223A1/en
Priority to US14/666,043 priority patent/US20160048624A1/en
Assigned to DEFENSE THREAT REDUCTION AGENCY, US DOD reassignment DEFENSE THREAT REDUCTION AGENCY, US DOD CONFIRMATORY LICENSE (SEE DOCUMENT FOR DETAILS). Assignors: ROBUST CHIP INC.
Assigned to DEFENSE THREAT REDUCTION AGENCY, US DOD reassignment DEFENSE THREAT REDUCTION AGENCY, US DOD CONFIRMATORY LICENSE (SEE DOCUMENT FOR DETAILS). Assignors: ROBUST CHIP INC.
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors.
  • the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods.
  • the method is particularly useful for CMOS based logic circuits in modern technologies ( ⁇ 90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.
  • TMR triple mode redundancy
  • BiSER built-in soft-error resilience
  • Error correction codes for memory, which also (loosely) could be classified as RHBD, is more efficient than duplication/triplication and can, with additional overhead, handle multiple errors in memory circuitry.
  • ECC Error correction codes
  • RHBD Error correction codes
  • the application of a corresponding error correction to logic circuits is very limited and application specific (e.g., selective parity check or insertion of specialized checking circuit IP).
  • a radiation generated single event (soft-) error occurs when the charge, generated in the semiconductor material by one or more (e.g. secondary) charge particles, is collected by contact areas on the semiconductor substrate. This leads to current pulses on the circuit nets, connected to these contact areas, which, in their turn, cause voltage pulses in the circuit which can upset a sequential element (latch, flip-flop) or propagate through combinational logic and be latched in as errors at the next sequential element in the circuit.
  • This invention comprises a unique new layout method, which takes advantage of the overall circuit response to a single event effect, and, furthermore, comprises circuit cells, with layout, which are protected against soft errors.
  • the method uses an arrangement of critical contact areas in such a way that single event pulses in the circuit, that are generated on multiple nodes, act to oppose each other and hence cancel (or greatly reduce the effect of the single event).
  • a primary and secondary circuit is used to maintain, or process the signal in a circuit
  • addition rules, described in section 4 are used, so that no possibility remains that a error is generated in both primary and secondary circuit, and hence that the combination of primary and secondary circuit will be fully error free.
  • Table 1 The state for the nodes in a circuit that uses a primary (nodes n 1 ,n 2 ) and secondary (nodes n 3 ,n 4 ) circuit for storage or processing of the state.
  • Drawing 1 Primary opposing nodes in a latch cell.
  • Drawing 2 A principal arrangement of opposing node of a latch circuit.
  • FIG. 3 Basic netlist for the DICE latch cell (prior art [Nic05]) with nodes 1 - 4 .
  • p 1 -p 4 and n 1 -n 4 are the pMOSFET drains and the nMOSFET drains, respectively.
  • ns/ps are the source contacts for the two mosfets who's drains are adjacent.).
  • p 1 -p 4 and n 1 -n 4 are the pMOSFET drains and the nMOSFET drains of the 4 main storage nodes, respectively. Any cyclic simultaneous permutation of the n and p nodes will be equivalent (and part of the invention).
  • the mosfets can be placed in separate active areas, or the adjacent n and p nodes can be placed in the same active area.
  • the MOSFET sources can be placed in the line of the drains or in the direction vertical to the line of the drain nodes.
  • the well contacts can be placed on either side only, or also surround the adjacent node pairs.
  • the nodes can also be arranged in a different order subject to the following rules: two adjacent n-drains, or two adjacent p-drains are always an odd/even pair (e.g., p 1 & p 2 , or n 2 and n 3 ), adjacent n-drain to p-drain are always an odd/odd or and even/even pair (e.g., n 2 & p 2 , or p 3 & n 1 ).
  • Drawing 5 Net-list corresponding to the second preferred arrangement.
  • the yellow MOSFET may or may not be included, as long as node 6 is connected to drain 6 a in drawing 5 , and p 1 and 6 a are physically separate.
  • Drawing 6 A second preferred layout arrangement. ns/ps are the source contacts for the two mosfets who's drains are adjacent. Node 6 a and 6 b are connected. The yellow gate adjacent to node 6 a may or may not be included (both variants included in the claims), but p 1 and 6 a are physically separate.
  • the layout derives from the layout in drawing 1 , and the same variants w.r.t. node permutations, active, source, and well contact arrangements apply.
  • Drawing 7 Net-list corresponding to the third preferred arrangement.
  • the yellow MOSFET may or may not be included, as long as node 6 is connected to drain 6 a in drawing 4 , and p 1 and 6 a are physically separate, and node 7 is connected to drain 7 a in drawing 4 , and n 1 and 7 a are physically separate.
  • Drawing 8 A third preferred layout arrangement. ns/ps are the source contacts for the two mosfets who's drains are adjacent. Node 6 a - 6 b are connected, as are node 7 a / 7 b .
  • the yellow gate adjacent to node 6 a and 7 a may or may not be included (both variants included in the claims), but the adjacent drain areas are physically separate.
  • the layout derives from the layout in drawing 1 , and the same variants w.r.t. node permutations, active, source, and well contact arrangements apply.
  • Drawing 9 Net-list corresponding to the fourth preferred arrangement.
  • the yellow MOSFET may or may not be included, as long as node 6 is connected to drain 6 a , 7 to 7 a , 8 to 8 a , and 9 to 9 a in drawing 8 , and 6 a , 7 a , 8 a , 9 a are physically separate from their adjacent main drain node.
  • Drawing 10 A fourth preferred layout arrangement.
  • ns/ps are the source contacts for the two mosfets who's drains are adjacent.
  • Node 6 a / 6 b , 7 a / 7 b , 8 a / 8 b , and 9 a / 9 b are connected.
  • the yellow gates adjacent to nodes 6 a , 7 a , 8 a , 9 a may or may not be included (both variants included in the claims), but nodes 6 a , 7 a , 8 a , 9 a are physically separate from their adjacent MOSFET drains.
  • the layout derives from the layout in drawing 1 , and the same variants w.r.t.
  • node permutations, active, source, and well contact arrangements apply.
  • the claims also cover the various additional variants where and combination of the extra nodes 6 a / 6 b , 7 a / 7 b , 8 a / 8 b , 9 a / 9 b have been included or omitted.
  • Drawing 11 Circuit schematic and layout for duplicated latch cells (e.g. for BISER) using placement and sizing to ensure complete hardness against single and multiple node single event effects.
  • the primary latch can only be upset when node 1 is HIGH
  • the redundant latch can only be upset when node 1 (r) is LOW.
  • any single event that affects both latches can only upset one of the two latches in the BISER configuration, and therefore, cannot generate an error.
  • Drawing 12 Example of a duplicated circuit of claim 9 AND 10 .
  • error signals on both primary and redundant nodes can be generated if both ndrain 0 and pdrain 1 are affected (if D is high) or if both ndrain 1 and pdrain 0 are affected (D low).
  • This invention comprises a unique new layout method, which takes advantage of the overall circuit response to a single event effect. It also includes specific circuit cells with layout, which have been constructed in accordance with the new layout method.
  • a radiation generated single event (soft-) error (SEE) occurs when the charge, generated in the semiconductor material by one or more (e.g. secondary) charged particles, is collected by contact areas.
  • the contact areas are the low resistivity regions on, or in, the semiconductor substrate, which are connected to a net in the circuit, e.g., the source and drain areas in a MOSFET technology.
  • a circuit net (or node) refers to a part of the circuit, connected by low resistivity regions (metal), which maintains a certain voltage value (referred to as the voltage state of the net) throughout its' extent.
  • a net can be connected to any number of contact areas.
  • the charge collected by contact areas during a single event leads to current pulses in the circuit, which, in their turn, cause a change in the voltage of the circuit nets, connected to these contact areas, i,e, a voltage pulse in the circuit.
  • These pulses can upset a sequential element (latch, flip-flop) or propagate through combinational logic (i.e., a set of digital logic gates) and be latched in as errors at the next sequential element in the circuit.
  • a single event can have the effect of increasing the voltage on the net connected to the contact area, or decreasing it, depending on where the contact areas are located in substrate, and how they are connected to the circuit.
  • the method in this invention uses an arrangement of contact areas in such a way that single event generated pulses in the circuit, that occur on multiple contact areas, acts to oppose each other, w.r.t. the effects they have on the voltage of the circuit nets, and hence cancel (or greatly reduce the effect of the single event).
  • the method also comprises an adjustment the strength of the effect a single event has on the voltage of the circuit nets, when this is desirable to achieve the desired total effect on the circuit.
  • This adjustment can be achieved by changing the sizes of the contact areas, and by changing their positions relative to other components in the layout.
  • the method can be applied to sequential logic elements (latches, flip-flops, memory cells), to combinational logic (a connection of one or more digital logic gates), or to analog circuit cells.
  • the first, section 4.1 uses a placement, and strength adjustment, such that the single event effects, on several contact areas, cancel out each other, in terms of their effect on the circuit nets they are connected to.
  • the second, section 4.2 uses a placement, and strength adjustment, such that two, or more, redundant nets in the circuit, are affected differently by a single event, in such a way that a single event cannot simultaneously change their voltage state on several of the redundant nets.
  • redundant nets place the contact areas of the redundant nets in a direction, which is such that when the charge from one single event effects both primary, and redundant nets, it is in the direction which is such that it always also affects both opposing nodes in either the primary or the secondary circuit, or that it affects the opposing node of both primary and secondary circuit.
  • step one and two above would use the following to characterize the effect of a single event on a source or drain contact area:
  • step 3 above would use the following rules for two nodes, each connected to a net carrying redundant signals (primary and secondary nets):
  • an alternative to synthesizing a layout where single event effects cancel out each other is to deliberately let one of the contact areas be stronger w.r.t. single event charge collection. This contact area will then always determine the outcome of a single event in on the connected net (e.g., for a p-drain it would always end up HIGH (at Vdd)).
  • FIG. 1 shows the schematics of the fundamental components of a latch circuit implemented in a CMOS technology.
  • each of the two (main) net is connected to two contacts areas in the layout (the nmos device drain and the pmos drain).
  • FIG. 2 shows such an arrangement where we have utilized the first two of the opposing contact area identifications above. We now have a latch which cannot be upset if the single event has such a directions that is passes the two nets of the circuit.
  • Step 3 in methodology number 1, as well as method number 2 concerns the case when an additional (redundant) circuit (here a latch) is available.
  • an additional (redundant) circuit here a latch
  • n 1 , n 2 from the primary latch
  • n 3 , n 4 from the secondary latch.
  • the nodes from one latch will be in opposite states, and, during correct circuit operation, each node in the primary latch will always have the same state as one node in the secondary latch. This situation is shown in table 1, where n 1 and n 3 maintain the same state, and n 2 and n 4 maintain the same state.
  • step 3 the nodes of the second latch are now placed, w.r.t. the first latch, such that when an extended event occurs that affects both latches, it will be in a direction which affects both opposing nodes in each individual latch, or at least in one of them.
  • FIG. 11 shows such an arrangement, where the method with dominating nodes (methodology 2 above) has been used, and the two latches have been placed in such a way relative to each other that at the most, one of the latches can be upset, by any single event, but not both.
  • a filtering, or voting circuit is used.
  • the filtering ensuring that at any time where one of the redundant nets is wrong (e.g., for the redundant nets carrying the same voltage state; if the voltage states differ) the signal is not allowed to pass through the filtering circuit.
  • the Built-In Soft Error (BISER) design [Mitra2005] is an example of such a configuration.
  • a voting circuit being used on at least 3 redundant circuit, performs a vote between the voltage states of the redundant nets.
  • Triple mode redundancy (TMR) configurations use this type of redundancy.
  • This invention also comprises several specific DICE cells, created using the layout method.
  • the principal arrangement of the 4 storage nets, of the DICE cells in this inventions, is that the contact areas of the nets are placed along one direction (e.g., drawing 4 ), and that they have a certain order, than minimizes or removes the effect of the single event, and hence reduces or removes the possibility that the storage element can be upset by a single event.
  • the first variant (variant 1 ) is shown in drawing 4 .
  • the MOSFET pairs have been placed in the same active area with a common MOSFET source contact in-between. However, they can also be placed in separate active areas, using separate sources contacts, and they can also be oriented so that the sources are perpendicular to the direction of the drain nodes.
  • the most sensitive node pair in variant 2 is the n 1 -p 4 node pair, this pair is protected with the extension in variant 3 (drawings 7 - 8 ).
  • the latch can be made symmetric by adding additional protective nodes. A fully symmetric arrangement of protective nodes is shown in drawings 9 - 10 (third variant).
  • additional protective MOSFETs has a general application to circuits which uses redundant nets.
  • they can be used to keep the state of a circuit node which becomes floating (not connected to the power, i.e., to VSS or VDD) during a single event.
  • Floating nets become very sensitive to the single event charge, their voltage state can change very easily (i.e., even by very weak interaction with the single event).
  • the additional protective devices even if they just turn on partially during the single event, will make the nodes, that become floating during a single event, much more stable.
  • Another (not DICE) example of the addition of such protective devices for a c-element filtering circuit is shown in drawing 13 .
  • the invention also comprises a combinational circuit where all, or some of the nets have been duplicated, in such a way that there is one (primary) net that carries the signal, and a second (redundant) net carries the inverse of the signal on the primary net (i.e., when the voltage on the primary net is high, the voltage on the redundant net is always low, and vice versa), and where, in accordance with the layout method, the contact areas of the primary and redundant net, are placed in such a way that when a single event affects both nets, a voltage pulse can only be generated on one of the nets, but not on both.

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US12/354,655 2008-01-17 2009-01-15 Layout method for soft-error hard electronics, and radiation hardened logic cell Abandoned US20090184733A1 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
US12/354,655 US20090184733A1 (en) 2008-01-17 2009-01-15 Layout method for soft-error hard electronics, and radiation hardened logic cell
US12/763,139 US8495550B2 (en) 2009-01-15 2010-04-19 Soft error hard electronic circuit and layout
US13/277,135 US8566770B2 (en) 2008-01-17 2011-10-19 Layout method for soft-error hard electronics, and radiation hardened logic cell
US13/425,231 US8468484B2 (en) 2008-01-17 2012-03-20 Layout method for soft-error hard electronics, and radiation hardened logic cell
US13/463,688 US20130038348A1 (en) 2008-01-17 2012-05-03 Layout method for soft-error hard electronics, and radiation hardened logic cell
US13/463,706 US20130227499A1 (en) 2008-01-17 2012-05-03 Layout method for soft-error hard electronics, and radiation hardened logic cell
US13/692,800 US9083341B2 (en) 2008-01-17 2012-12-03 Soft error resilient circuit design method and logic cells
US14/026,648 US9081926B2 (en) 2008-01-17 2013-09-13 Soft error and radiation hardened sequential logic cell
US14/060,162 US20140157223A1 (en) 2008-01-17 2013-10-22 Circuit and layout design methods and logic cells for soft error hard integrated circuits
US14/666,043 US20160048624A1 (en) 2008-01-17 2015-03-23 Circuit and layout design methods and logic cells for soft error hard integrated circuits

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US1159908P 2008-01-17 2008-01-17
US1198908P 2008-01-22 2008-01-22
US6848308P 2008-03-07 2008-03-07
US12300308P 2008-04-05 2008-04-05
US12/354,655 US20090184733A1 (en) 2008-01-17 2009-01-15 Layout method for soft-error hard electronics, and radiation hardened logic cell

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US12/763,139 Continuation-In-Part US8495550B2 (en) 2008-01-17 2010-04-19 Soft error hard electronic circuit and layout
US13/277,135 Division US8566770B2 (en) 2008-01-17 2011-10-19 Layout method for soft-error hard electronics, and radiation hardened logic cell
US13/425,231 Continuation-In-Part US8468484B2 (en) 2008-01-17 2012-03-20 Layout method for soft-error hard electronics, and radiation hardened logic cell
US13/463,688 Continuation-In-Part US20130038348A1 (en) 2008-01-17 2012-05-03 Layout method for soft-error hard electronics, and radiation hardened logic cell
US13/463,706 Continuation-In-Part US20130227499A1 (en) 2008-01-17 2012-05-03 Layout method for soft-error hard electronics, and radiation hardened logic cell

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US14/026,648 Active US9081926B2 (en) 2008-01-17 2013-09-13 Soft error and radiation hardened sequential logic cell

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EP (2) EP2685633A3 (de)
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US20120054702A1 (en) * 2010-08-31 2012-03-01 International Business Machines Corporation Techniques for Employing Retiming and Transient Simplification on Netlists That Include Memory Arrays
US8566770B2 (en) 2008-01-17 2013-10-22 Klas Olof Lilja Layout method for soft-error hard electronics, and radiation hardened logic cell
WO2013082611A3 (en) * 2011-12-02 2013-12-19 Robust Chip Inc. Soft error hard electronics layout arrangement and logic cells
WO2014066402A1 (en) * 2012-10-22 2014-05-01 Klas Olof Lilja Circuit and layout design methods and logic cells for soft error hard integrated circuits
US20140245113A1 (en) * 2010-11-19 2014-08-28 Altera Corporation Memory Array with Redundant Bits and Memory Element Voting Circuits
US20140331197A1 (en) * 2011-06-02 2014-11-06 Arizona Board Of Regents On Behalf Of Arizona State University Sequential state elements in triple-mode redundant (tmr) state machines
US9041429B2 (en) 2011-06-02 2015-05-26 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University Sequential state elements for triple-mode redundant state machines, related methods, and systems
US9054688B2 (en) 2012-09-19 2015-06-09 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University Sequential state elements radiation hardened by design
US20150286772A1 (en) * 2014-04-07 2015-10-08 TallannQuest LLC Method and system for computer-aided design of radiation-hardened integrated circuits
US20160048624A1 (en) * 2008-01-17 2016-02-18 Klas Olof Lilja Circuit and layout design methods and logic cells for soft error hard integrated circuits
US9379689B2 (en) * 2014-07-18 2016-06-28 SK Hynix Inc. Integrated circuit
US20160229679A1 (en) * 2013-09-20 2016-08-11 Advanced Technology Materials, Inc. Apparatus and method for pressure dispensing of high viscosity liquid-containing materials
US9734272B2 (en) 2014-06-13 2017-08-15 Arizona Board Of Regents On Behalf Of Arizona State University Techniques for generating physical layouts of in silico multi mode integrated circuits
US10014048B2 (en) * 2016-11-08 2018-07-03 SK Hynix Inc. Dual interlocked storage cell (DICE) latch sharing active region with neighbor DICE latch and semiconductor device including the same
US10579536B2 (en) 2016-08-09 2020-03-03 Arizona Board Of Regents On Behalf Of Arizona State University Multi-mode radiation hardened multi-core microprocessors
US11711070B2 (en) 2019-09-27 2023-07-25 Nuvoton Technology Corporation Japan Semiconductor device

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