US20160164540A1 - Data processing device and data processing method - Google Patents

Data processing device and data processing method Download PDF

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US20160164540A1
US20160164540A1 US14/903,993 US201514903993A US2016164540A1 US 20160164540 A1 US20160164540 A1 US 20160164540A1 US 201514903993 A US201514903993 A US 201514903993A US 2016164540 A1 US2016164540 A1 US 2016164540A1
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parity check
ldpc code
matrix
check matrix
parity
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Yuji Shinohara
Makiko YAMAMOTO
Ryoji IKEGAYA
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Saturn Licensing LLC
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Sony Corp
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Publication of US20160164540A1 publication Critical patent/US20160164540A1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
    • H03M13/356—Unequal error protection [UEP]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • the present technology relates to a data processing device and a data processing method, and more particularly, a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code, for example.
  • a low density parity check (LDPC) code has a high error correction capability, and in recent years, the LDPC code has widely been employed in transmission schemes of digital broadcasting such as Digital Video Broadcasting (DVB)-S.2, DVB-T.2, and DVB-C.2 of Europe and the like, or Advanced Television Systems Committee (ATSC) 3.0 of the USA and the like (for example, see Non-Patent Literature 1).
  • DVD Digital Video Broadcasting
  • DVB-T.2 DVB-T.2
  • DVB-C.2 Advanced Television Systems Committee
  • the LDPC code has a property that a shortest distance is proportional to the code length, the LDPC code has advantages of a block error probability characteristic being superior and a so-called error floor phenomenon observed in a decoding characteristic of the turbo code being rarely generated, as characteristics thereof.
  • the LDPC code is converted into a symbol of an orthogonal modulation (digital modulation) such as Quadrature Phase Shift Keying (QPSK), and the symbol is mapped to a signal point of the orthogonal modulation and transmitted.
  • orthogonal modulation digital modulation
  • QPSK Quadrature Phase Shift Keying
  • the data transmission using the LDPC code has spread worldwide, and there is a demand to secure excellent communication (transmission) quality.
  • the present technology was made in light of the foregoing, and it is desirable to secure excellent communication quality in data transmission using the LDPC code.
  • a first data processing device/method is a data processing device/method including: an encoding unit/step configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length N is 64800 bits and an encoding rate r is 6/15; a group-wise interleaving unit/step configured to perform group-wise interleave of interleaving the LDPC code in units of bit groups of 360 bits; and a mapping unit/step configured to map the LDPC code to any of 4096 signal points decided in a modulation scheme in units of 12 bits.
  • bit group i when an (i+1)-th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes an information bit and a parity bit.
  • the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
  • the LDPC code includes an information bit and a parity bit.
  • the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
  • a second data processing device/method is a data processing device/method including: a group-wise deinterleaving unit/step configured to restore a sequence of an LDPC code that has undergone group-wise interleave and has been obtained from data transmitted from a transmitting device to an original sequence, the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of the LDPC code in which a code length N is 64800 bits and an encoding rate r is 6/15, a group-wise interleaving unit configured to perform the group-wise interleave of interleaving the LDPC code in units of bit groups of 360 bits, and a mapping unit configured to map the LDPC code to any of 4096 signal points decided in a modulation scheme in units of 12 bits.
  • bit group i when an (i+1)-th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes an information bit and a parity bit.
  • the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
  • a sequence of an LDPC code that has undergone group-wise interleave and has been obtained from data transmitted from a transmitting device is restored to an original sequence
  • the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of the LDPC code in which a code length N is 64800 bits and an encoding rate r is 6/15, a group-wise interleaving unit configured to perform the group-wise interleave of interleaving the LDPC code in units of bit groups of 360 bits, and a mapping unit configured to map the LDPC code to any of 4096 signal points decided in a modulation scheme in units of 12 bits.
  • bit group i when an (i+1)-th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes an information bit and a parity bit.
  • the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
  • a third data processing device/method is a data processing device/method including: an encoding unit/step configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length N is 64800 bits and an encoding rate r is 7/15; a group-wise interleaving unit/step configured to perform group-wise interleave of interleaving the LDPC code in units of bit groups of 360 bits; and a mapping unit/step configured to map the LDPC code to any of 4096 signal points decided in a modulation scheme in units of 12 bits.
  • bit group i when an (i+1)-th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the predetermined value g is 1080.
  • the A matrix and the C matrix are represented by a parity check matrix initial value table.
  • the parity check matrix initial value table is a table in which positions of 1 elements of the A matrix and the C matrix are indicated for every 360 columns, and includes
  • LDPC encoding is performed based on a parity check matrix of an LDPC code in which a code length N is 64800 bits and an encoding rate r is 7/15.
  • Group-wise interleave of interleaving the LDPC code in units of bit groups of 360 bits is performed.
  • the LDPC code is mapped to any of 4096 signal points decided in a modulation scheme in units of 12 bits.
  • a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the predetermined value g is 1080.
  • the A matrix and the C matrix are represented by a parity check matrix initial value table.
  • the parity check matrix initial value table is a table in which positions of 1 elements of the A matrix and the C matrix are indicated for every 360 columns, and includes
  • bit group i when an (i+1)-th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the predetermined value g is 1080.
  • the A matrix and the C matrix are represented by a parity check matrix initial value table.
  • the parity check matrix initial value table is a table in which positions of 1 elements of the A matrix and the C matrix are indicated for every 360 columns, and includes
  • a sequence of an LDPC code that has undergone group-wise interleave and has been obtained from data transmitted from a transmitting device is restored to an original sequence
  • the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of the LDPC code in which a code length N is 64800 bits and an encoding rate r is 7/15, a group-wise interleaving unit configured to perform the group-wise interleave of interleaving the LDPC code in units of bit groups of 360 bits, and a mapping unit configured to map the LDPC code to any of 4096 signal points decided in a modulation scheme in units of 12 bits.
  • bit group i when an (i+1)-th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the predetermined value g is 1080.
  • the A matrix and the C matrix are represented by a parity check matrix initial value table.
  • the parity check matrix initial value table is a table in which positions of 1 elements of the A matrix and the C matrix are indicated for every 360 columns, and includes
  • a fifth data processing device/method is a data processing device/method including: an encoding unit/step configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length N is 64800 bits and an encoding rate r is 8/15; a group-wise interleaving unit/step configured to perform group-wise interleave of interleaving the LDPC code in units of bit groups of 360 bits; and a mapping unit/step configured to map the LDPC code to any of 4096 signal points decided in a modulation scheme in units of 12 bits.
  • bit group i when an (i+1)-th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes an information bit and a parity bit.
  • the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
  • LDPC encoding is performed based on a parity check matrix of an LDPC code in which a code length N is 64800 bits and an encoding rate r is 8/15.
  • Group-wise interleave of interleaving the LDPC code in units of bit groups of 360 bits is performed.
  • the LDPC code is mapped to any of 4096 signal points decided in a modulation scheme in units of 12 bits.
  • a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes an information bit and a parity bit.
  • the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
  • a sixth data processing device/method is a data processing device/method including: a group-wise deinterleaving unit/step configured to restore a sequence of an LDPC code that has undergone group-wise interleave and has been obtained from data transmitted from a transmitting device to an original sequence, the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of the LDPC code in which a code length N is 64800 bits and an encoding rate r is 8/15, a group-wise interleaving unit configured to perform the group-wise interleave of interleaving the LDPC code in units of bit groups of 360 bits, and a mapping unit configured to map the LDPC code to any of 4096 signal points decided in a modulation scheme in units of 12 bits.
  • bit group i when an (i+1)-th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes an information bit and a parity bit.
  • the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
  • a sequence of an LDPC code that has undergone group-wise interleave and has been obtained from data transmitted from a transmitting device is restored to an original sequence
  • the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of the LDPC code in which a code length N is 64800 bits and an encoding rate r is 8/15, a group-wise interleaving unit configured to perform the group-wise interleave of interleaving the LDPC code in units of bit groups of 360 bits, and a mapping unit configured to map the LDPC code to any of 4096 signal points decided in a modulation scheme in units of 12 bits.
  • bit group i when an (i+1)-th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into a sequence of bit groups
  • the LDPC code includes an information bit and a parity bit.
  • the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
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US9787326B2 (en) * 2015-05-19 2017-10-10 Samsung Electronics Co., Ltd. Method and apparatus for encoding and decoding low density parity check codes
US10333550B2 (en) 2014-05-21 2019-06-25 Sony Corporation Data processing device and data processing method
TWI665877B (zh) * 2017-02-06 2019-07-11 日商索尼股份有限公司 送訊方法及收訊裝置
US10389387B2 (en) * 2015-05-19 2019-08-20 Sony Semiconductor Solutions Corporation Coding device and coding method for a DVB-like LDPC code and a LDPC code in an ETRI format
TWI675556B (zh) * 2017-02-06 2019-10-21 日商索尼股份有限公司 送訊方法及收訊裝置
TWI677197B (zh) * 2017-02-20 2019-11-11 日商索尼股份有限公司 送訊方法及收訊裝置
TWI683545B (zh) * 2018-01-18 2020-01-21 日商索尼股份有限公司 送訊方法及收訊裝置
TWI683544B (zh) * 2018-01-18 2020-01-21 日商索尼股份有限公司 送訊方法及收訊裝置
EP3584938A4 (de) * 2017-02-20 2020-04-15 Sony Corporation Sendeverfahren und empfangsvorrichtung
US10924136B2 (en) 2017-05-31 2021-02-16 Sony Corporation Transmission device, transmission method, reception device, and reception method
US10931312B2 (en) 2017-02-06 2021-02-23 Sony Corporation Transmission method and reception device
US11070235B2 (en) 2017-02-20 2021-07-20 Sony Corporation Transmission method and reception device
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