US3117309A - Arrangement for controlling a magnet core matrix - Google Patents

Arrangement for controlling a magnet core matrix Download PDF

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Publication number
US3117309A
US3117309A US174779A US17477962A US3117309A US 3117309 A US3117309 A US 3117309A US 174779 A US174779 A US 174779A US 17477962 A US17477962 A US 17477962A US 3117309 A US3117309 A US 3117309A
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pulse
cores
matrix
information
arrangement
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US174779A
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Wolf Gerhard
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Digital Kienzle Computersysteme GmbH and Co KG
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Kienzle Apparate GmbH
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
    • G11C11/06014—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit using one such element per bit
    • G11C11/06021—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit using one such element per bit with destructive read-out
    • G11C11/06028—Matrixes
    • G11C11/06042—"word"-organised, e.g. 2D organisation or linear selection, i.e. full current selection through all the bit-cores of a word during reading

Definitions

  • the present invention concerns a magnet core matrix, and more particularly an arrangement for subjecting such a matrix to non-obliterating read-out by which informa tion stored in the matrix is first read out and thereafter immediately re-introduced and stored again in the matrix.
  • Magnet core matrices are being used extensively as storage means in the field of electronic calculating machines. These matrices comprise a plurality of magnet cores of annular shape and made of material having a substantially rectangular hysteresis characteristic. As is well known, these cores can be changed between magnetic saturation of one polarity representing information storage and a magnetic saturation of opposite polarity representing no-information storage. For changing the magnetic saturation by the application of suitable pulses and for reading out stored information by application of other pulses column wires are arranged extending through the cores of each column thereof, and row wires are arranged extending through the cores of each row thereof.
  • the invention includes in an arrangement of the type set forth, in combination, matrix means comprising a plurality of magnet cores arranged in a plurality of rows and in a plurality of columns and being individually changeable from information storage rep resenting magnetic saturation of one polarity to no-information storage representing magnetic saturation of opposite polarity by application thereto of a read-out pulse of one polarity, and changeable from no-information storage representing saturation to information storage representing saturation by simultaneous application thereto of two half-re-storing pulses of the opposite polarity, each of said cores delivering an output pulse upon a change thereof to no-information representing saturation; pulse return means connected with said matrix means so as to receive said output pulses from any one of said cores and for returning, upon receiving an output pulse, a first halfre-storing pulse of said opposite polarity to at least one of said cores being in no-information representing saturation and located in at least one of said rows thereof; shift register means having a plurality of stages sequentially energizable by application of a sequence
  • FIG. 1 is a schematic diagram illustrating a conventional matrix and conventional read-out and re-storing means, for the purpose of explaining the basic principle of the operation;
  • FIG. 2 is a schematic circuit diagram of one embodiment of the invention including a Woo-type register
  • FIG. 3 is a schematic diagram of another embodiment of the invention including a different type of a shift register
  • FIG. 4 is a schematic diagram illustrating a further embodiment of the invention including electronic switch means
  • FIG. 5 is a schematic diagram illustrating a modification of the embodiment shown by FIG. 4;
  • FIGS. 5a and 5b are explanatory pulse diagrams illustrating the operation of the arrangement according to FIG. 5;
  • FIG. 6 is a schematic diagram illustrating a modification of a portion of the arrangement of FIG. 5, serving to shift information within the matrix;
  • FIG. 6a is a chart illustrating the operation of the arrangement according to FIG. 6.
  • FIG. 7 is a further modification of a portion of the arrangement according to FIG. 2, for the purpose of shifting information within the matrix in a different manner.
  • FIG. 1 illustrates a conventional arrangement which serves to read out information stored in the matrix and to re-introduce this information immediately after the read-out information, or to re-introduce into the matrix the result of a calculating operation.
  • the illustrated matrix of conventional type comprises a plurality of magnet cores as mentioned above and arranged in rows a, b, c, d and in columns 1, 2, 3, 4, 5,
  • Magnet cores having a substantially rectangular hysteresis characteristic are located at the respective intersections between rows and columns. While the illustrated example comprises only four rows and five columns it is evident that the following description applies analogously to matrices having any number of rows and of columns.
  • a column wire 5 is respectively associated with each of the columns 1 to 5 and is taken through the cores of the respective column, e.g., wire 15 through the cores in to id.
  • the cores of each row are associated with an output wire taken through the cores of the particular row and marked 16:: to 16d, respectively.
  • a second input wire is associated with each of the rows of cores and extends therethrough, these input wires being marked 17a to 17d, respectively.
  • a pulse retuming arrangement Z comprises in association with each of the rows a to d a set of devices 18, 2t ⁇ and 19 of which the unit 13 is an amplifier, the unit 29 may be a delay device and the unit 19 is a pulse generator.
  • the reference numerals of these devices are provided with a sufiix referring to the designation :of the respectively associated row a to d.
  • the output lines 16a to 16d are respectively connected with the corresponding amplifier 13a to 1 8d, respectively.
  • the outputs of the pulse generators 19a to 190! are respectively connected with the corresponding input lines 17a to 17d.
  • a first half-restoring pulse Hm T is to be introduced into the respective column wire, and a second half-restoring pulse is to be introduced into the corresponding row wire or input wire 17a to 17d, respectively.
  • the output pulse produced by the reversal of the magnetic saturation of the particular core and applied to the respective read-out amplifier i8 is amplified thereby and is applied, if desired via the corresponding delay device 2%, to the pulse generator 1'9 which produces the desired half-restoring pulse and returns from its output the desired half-restoring pulse Hm T through the corresponding input line 17a to 17d to the above mentioned intersection of the particular column and the particular row.
  • each of the columns 1 to 5 is associated with a pair of impulse generators 12 and 13, the one furnishing to the respective column wire a pulse Hm, the other furnishing to that line a pulse
  • each of these impulse generators must be triggered by a suitable pulse timing arrangement.
  • a mechanical or electronic shift register 10 is provided for this purpose in which some energy storage 11 is shifted in well known manner stepwise in the direction of the arrow. With every step of this shift register a triggering pulse is applied to the consecutive pulse generators 12, 13.
  • shift registers may be used for this purpose, e.g., a register composed of flip-flops or of interconnected flip-fiop tetrades, or also magnetic shift registers of suitable type.
  • a register composed of flip-flops or of interconnected flip-fiop tetrades, or also magnetic shift registers of suitable type.
  • the first impulse generator 12 applies a negative pulse Hm to the column wire 15
  • the magnetization of the 'core in is reversed so that the output line 16a carries an output pulse which appears in amplified form at the output of the read-out amplifier 18a.
  • the magnet cores 1b, 1c, 1d having been already in a state of negative magnetic saturation are not affected by the negative read-out pulse I-lm. Consequently no pulse is applied to or delivered by the read-out amplifiers 18b, 18c and 18d.
  • FIG. 2 illustrates for the sake of clarity only a fraction of the matrix of FIG. 1, namely only the columns 2 and 3 with the respective magnet cores 2a to 2d and 3a to 3d. While according to FIG. 1 a twopolarity pulse 14 had to be produced by separate impulse generators 12 and 13 and applied to the respective column, a corresponding two-polarity pulse 21 is obtained according to the invention as illustrated by FIG.
  • FIG. 2 shows as a read-out control means a shift register of the well known Woo-type. It may be mentioned here that instead of a Woo-type register also a register of the An Wang-type may be used. Both types of shift registers are described for instance in an article Static Magnetic Storage and Delay Line in Journal of Applied Physics, vol. 21, No. 6, pages 49-54 (1950).
  • the shift register comprises a plurality of cores 32, 33 and 34, input windings 42, 43 and 44 and output windings S2, 53 and 54, respectively associated with the cores and shift windings 62, 63, 64 respectively associated with the cores and connected in series with each other by a control line 20.
  • Each stage of the register further'includes a diode 72, 73 etc., and an intermediate storage condenser 32, 83 etc. connected between consecutive stages.
  • every step of shifting information through the shifting register produces a cycle of charge and discharge of the respective intermediate storage condenser.
  • the charge and discharge circuit of each of these condensers is connected with a different one of the column lines of the matrix.
  • one side of the condenser 82 is directly connected with the column line 15
  • the shift register core 32 is in a state of positive magnetic remanence.
  • the shift winding 62 is energized and causes reversal of the magnetic remanence of core 32. This generates a voltage across the output winding 52 whereby the condenser 82 is charged via line 15 and diode 72. Now the condenser is negatively charged.
  • This charging current has the form of the negative portion of the pulse 21 and passing through the line 15 it obliterates an information that may have been stored in the core 2a.
  • the resulting delivery of an output pulse to the arrangement Z and the return of a half-restoring pulse from there is the same as described above.
  • the application of the other halfrestoring pulse to the column wire 15 is now obtained by the discharge of the condenser 82 immediately after its charging.
  • the condenser 82 discharges across the resistor 32 and the input winding 43 of the next stage and of course also via the column Wire 15
  • the resistor 92 must be so dimensioned that the amplitude of the discharge current corresponds to the value It can be seen, therefore, that upon coincidence of the positive discharge pulse of the condenser 82 with the half-restoring pulse returned by the arrangement Z, the previously obliterated information is re-introduced into the core 2a.
  • FIG. 2 is remarkably simpler than the conventional arrangement according to FIG. 1 because the required two-polarity pulses are derived in a direct and simple manner from the charge and discharge of the intermediate condenser in the shift register which is required in any case for a stepwise read-out operation of the matrix. It is not even necessary to produce the required two-polarity pulse by decoupling from two different windings and via special distributing means. Instead all that is required is to arrange for one connection of the condenser to extend as a single wire through the cores of the respectively associated column of the matrix. Thus at least two blocking oscillators or other impulse generators per column are saved by the invention.
  • FIG. 3 illustrates an embodiment of the invention which differs from FIG. 2 only by incorporating a ditferent type of a magnetic shift register of the type disclosed in Gerrnan Patent No. 1,058,285, or in my copending US. patent application Serial No. 63,314.
  • This register comprises a plurality of cores 3-1, 32', 33" and 34, and in each stage respectively associated with these cores a circuit arrangement comprising, respectively, windings 61 to 64', diodes 71 to 74', intermediate storage condensers 81 to 84', and resistors 91' to 94-, respectively, interconnected as shown in FIG. 3.
  • one connection of each of the intermediate storage condensers 81 to 84 is taken through the respectively associated column of cores so that again the two-polarity pulse 21 is applied to the particular column upon every step of the shift register as described above.
  • the two-polarity pulse 21 is applied to the particular column upon every step of the shift register as described above.
  • FIG. 4 again illustrates only a portion comprising columns 2 and 3 of the matrix and the corresponding portions of the shift register.
  • the shift register of FIG. 4 is fundamentally the same as that shown and described with reference to FIG. 2.
  • This arrangement has the further advantage of being operable at a higher step frequency without an increase of the energy consumption because no resistors are provided in the discharge circuits of the intermediate storage condensers. Instead electronic switch means are provided as will be described further below.
  • the energy consumption of this arrangement is particularly low because not only no energy is consumed in resistors, but also no discharge current can be delivered by the condensers during their charging.
  • the shift register proper is supplemented by a shift impulse generator which may be any suitable type of a blocking oscillator 181 comprising on a magnetizable core a first winding 110 and a second winding 111.
  • the output of winding lllil is connected with the shift impulse line 253' via a transistor 103.
  • This transistor must be of such a construction that it is rendered conductive When its base is given negative polarity.
  • the blocking oscillator N31 delivers a two-polarity pulse as illustrated at 162 which has a negative portion corresponding to Hm and a positive portion corresponding to Only the negative portion Hm is capable of rendering the control transistor Hi3 conductive.
  • the second winding 111 of the blocking oscillator 161 furnishes also a two-polarity pulse as shown at 164- which is identical with the pulse 162 except that its polarity is reversed.
  • the output of the winding 111 is connected with the base of a second control transistor 1425 of the same type as transistor 193, the transistor 105 acting as a gate for the discharge line 196 which is connected via diodes 192, 93, 194-, respectively, with the input windings 42', 43, 44, respectively, of the shift register.
  • the transistor 165 is rendered conductive by the negative portion of the pulse 164 only at that time when a particular one of the condensers 82, 83" etc. is to be discharged.
  • This and the immediately following discharge of this condenser 82" causes the application of a two-polarity pulse as illustrated at 121 to the column wire
  • the negative portion Hm of the shift impulse 1% has decayed
  • the negative portion of the pulse 104 produced by the winding 111 renders the transistor 195 conductive so that only at this moment the capacitor 82" is able to discharge through Winding 43' and diode 193.
  • the positive portion of the pulse 121 is applied to the column wire 15
  • the discharge of the capacitor 82 causes energization of the input winding 43" and thus reversal of magnetization of core 33". In this manner the cycle of operations described above repeats for one stage of the shift register after the other and correspondingly for the consecutive columns of the matrix.
  • Each column wire of the matrix is supplied with the required impulses by the individual intermediate storage condensers of the register. It is only necessary to see to it that the form of the two-polarity pulse 121 is such that the impulse portion follows the preceding negative pulse portion Hm with a slight delay resulting of the unblocking of the transistor MP5.
  • the small time interval between the just mentioned pulse portions may be used for inserting between the obliteration of stored information and the re-introduction of this information a calculating operation.
  • means can be provided for increasing this time interval to a desirable magni de.
  • FIG. 5 illustrates mainly only those portions of the arrangement which differ from those in FIG. 4.
  • each stage of the shift register has two connec tions A and B taken through the matrix, for instance the first stage a line A from the winding 51a and a line B from the condenser 31a.
  • the lines A to A carry positive pulses +Hm when the respective condensers are charged.
  • the lines B to B however carry two-polarity pulses -Hm and
  • the connections taken from the output windings 51a to 54a and by thus causing the direction of the flow of current in the lines A to A; where they pass through the cores of the respective columns to produce a magnetic field strength Hm the current flowing through each output Winding 51a to 54:: when the latter is energized will produce an advance read-out pulse Hm in the cores of the column associated with the respectively next following shift register stage. For instance, in column 2 the line A from the first stage is taken through the cores 2:: to 2d in a direction opposite to the direction of the line B taken from the second stage through the just mentioned cores.
  • a first read-out impulse I-Im (as indicated at a in FIG. 5a) is applied through line A to the cores 2a to 2d of column 2.
  • the condenser 82a is first charged and thereafter discharged as described above, the above described two-polarity pulse as shown in FIG. 5a is applied through line B to the cores of column 2.
  • the positive portion is effective as a half-restoring pulse as described above. Consequently, between the first read-out impulse Hm furnished by one stage and the following half-restoring pulse furnished by the respectively following stage there appears a time interval of arbitrarily predeterminable duration corresponding to the interval between consecutive steps in the shift register.
  • This time interval may be used for carrying out intercalated calculating operations. It is true that the two-polarity pulse delivered by the respectively second stage has a negative pulse portion Hm as indicated at b in FIG. a is delivered. However this is not disturbing or detrimental because the respective magnet core has been changed already by the preceding advance read-out pulse to a state of negative magnetic remanence so that no output voltage is induced any more by the second pulse Hm. This second impulse can only have the favorable effect to make absolutely sure that in the particular column all cores are placed in a state of negative magnetic remanence.
  • FIG. 6 illustrates a modification of only a portion of the arrangement according to FIG. 5 for the purpose of shifting the entire information storage existing in a matrix in the direction of the rows thereof.
  • this mode of operation requires providing one additional column in addition to the normally required columns in the matrix so that any one of the existing columns may serve as a transfer column because at the moment when information is to be shifted from one core in a row to the next following core in that row, information from a core preceding said one core cannot be shifted simultaneously into that one core.
  • information can be shifted in the direction of the rows in the following manner. For instance, first information may be shifted from the core 3a to the core 40. In a next step information may be shifted from core 2a into core 3a, hereafter the information from core 1a may be shifted into core 2a etc.
  • core 2a is read out by a read-out impulse applied to line A and this information is re-introduced in the same manner as described above into the core 3a upon the arrival of the half-restoring impulse through line B
  • core in is read out by an impulse through line A; and is re-introduced into core 2a upon the arrival of the respective pulse through line B
  • a shift of information in the direction toward the left may be carried out in the same manner. If 11 cycles of operation of the shift register are carried out, the shift of information within the matrix will amount also to 11 steps.
  • This operation is preferably suitable for carrying out decimal shifts in a decimal matrix in which case every step of shift in the matrix would correspond to a multiplication with the factor 10, or the factor 1/ 10.
  • FIG. 6 serves to produce a shift of stored information in the direction of the rows
  • FIG. 2 it is also possible to modify the arrangement of, e.g., FIG. 2 in such a manner that a shift of information stored in the matrix is carried out in the direction of the columns.
  • This may be cfiected by cyclically changing the connections between the outputs of the generators 19a to 19d with the rows to which the half-restoring pulses furnished by these generators, respectively, are returned.
  • line 1711' being the input line for the row a is taken from the generator Nd
  • line 17b is taken from generator 1%
  • line 17c is taken from generator 1%
  • line 17d is taken from generator 1%.
  • matrix means comprising a plurality of magnet cores arranged in a plurality of rows and in a plurality of columns and being individually changeable from information storage representing magnetic saturation of one polarity to no-information storage representing magnetic saturation of opposite polarity by application thereto of a read-out pulse of one polarity, and changeable from Ito-information storage representing saturation to information storage representing saturation by simultaneous application thereto of two half-re-storing pulses of the opposite polarity, each of said cores delivering an output pulse upon a change thereof to no-information representing saturation; pulse return means connected with said rows of said matrix means so as to receive said output pulses from any one of said cores and for returning, upon receiving an output pulse, a first halfrestoring pulse of said opposite polarity to at least one of said cores being in non-information representing saturation and located in at least one of said rotws thereof;
  • shift register means having a plurality of stages respectively associated with said different columns and sequentially energizable by application of a sequence of shift pulses to one stage after the other, respectively, and including energy transfer means for transmitting energy from each stage energized by a shift pulse to the next following stage, said energy transfer involving the appearance of a sequence of consecutive pulses of respectively opposite polarities in the respective transfer means; shift pulse generator means for applying shift pulses to said shift register means; and a plurality of circuit means connecting said energy transfer means respectively with different ones of said columns of cores for channeling each of said sequences of pulses of opposite polarities through the respective columns and for applying out of such pulse sequence the pulse of one polarity as a readout pulse to at least one of the cores being in information storage representing saturation, and for applying the pulse of opposite polarity as a second half-re-storing pulse to that core to which said first half-re-storing pulse is being applied so as to change this particular core to information storage representing saturation.
  • matrix means comprising a plurality of magnet cores arranged in a plurality of rows and in a plurality of columns and being individually changeable from information storage representing magnetic saturation of one polarity to ire-information storage representing magnetic saturation of opposite polarity by application thereto of a read-out pulse of one polarity, and changeable from tic-information storage representing saturation to information storage representing saturation by simultaneous application thereto of two half-re-storing pulses of the opposite polarity, each of said cores delivering an output pulse upon a change thereof to no-informa tion representing saturation; pulse return means connected with said rows of said matrix means so as to receive said output pulses from any one of said cores and for returning, upon receiving an output pulse, a first half-restoring pulse of said opposite polarity to at least one of said cores being in inc-information representing saturation and locatcd in at least one of said rows thereof; shift register means having a plurality of stages respectively associated with said danderrent columns and
  • matrix means com rising a plurality of magnet cores arranged in a plurality of rows and in a plurality of columns and being individually changeable from information storage representing magnetic saturation of one polarity to tic-information storage representing magnetic saturation of opposite polarity by application thereto of a read-out pulse of one polarity, and changeable from Ito-information storage representing saturation to information storage representing saturation by simultaneous application thereto of two half-restoring pulses of opposite polarity, each of said cores delivering an output pulse upon a change thereof to no-information representing saturation; pulse return means connected with said rows of said matrix means so as to receive said output pulses from any one of said cores and for returning, upon receiving an output pulse, a first half-re-storing pulse of said opposite polarity to at least one of said cores being in tic-information representing saturation and located in at least one of said rows thereof; shift register means having a plurality of stages respectively associated with said diiferent columns and sequentially energizable by application
  • shift pulse generator means is adapted to furnish at the termination of said shift pulse additionally a control signal, and including control transistor means con- 14 nected with all said intermediate capacitor means and controllable by said control signal so as to permit discharge of any of said capacitor means only upon application of said control signal.

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  • Transforming Light Signals Into Electric Signals (AREA)
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US174779A 1961-02-23 1962-02-21 Arrangement for controlling a magnet core matrix Expired - Lifetime US3117309A (en)

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DEK42981A DE1168969B (de) 1961-02-23 1961-02-23 Einrichtung zum Lesen und Wiedereinschreiben von Informationen in Magnetkern-Matrizen

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3364475A (en) * 1964-09-24 1968-01-16 Telefunken Patent Time delay compensation for coincident current matrix selection circuits
US3991408A (en) * 1973-02-22 1976-11-09 International Business Machines Corporation Self-sequencing memory

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1073031B (de) * 1956-08-16 1960-01-14 IBM Deutschland Internationale Büro Maschinen Gesellschaft mbH Smdelfmgen (Wurtt) Steuer kette aus bistabilen magnetischen Element ten
DE1098256B (de) * 1956-11-05 1961-01-26 Zuse K G Informationsspeicher
DE1068920B (de) * 1957-03-04 1959-11-12 Kienzle Apparate G.M.B.H., Villingen (Schwarzw.) Speicher-Matrix

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* Cited by examiner, † Cited by third party
Title
None *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3364475A (en) * 1964-09-24 1968-01-16 Telefunken Patent Time delay compensation for coincident current matrix selection circuits
US3991408A (en) * 1973-02-22 1976-11-09 International Business Machines Corporation Self-sequencing memory

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CH400238A (de) 1965-10-15
DE1168969B (de) 1964-04-30
GB946521A (en) 1964-01-15

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