US3264455A - Binary counter - Google Patents

Binary counter Download PDF

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Publication number
US3264455A
US3264455A US250341A US25034163A US3264455A US 3264455 A US3264455 A US 3264455A US 250341 A US250341 A US 250341A US 25034163 A US25034163 A US 25034163A US 3264455 A US3264455 A US 3264455A
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Prior art keywords
adder
output
storage device
circuit
carry
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US250341A
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English (en)
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Gotz Elmar
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LICENTIA PATENTS VERWALTUNGS G
Licentia Patents-Verwaltungs-G M B H
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LICENTIA PATENTS VERWALTUNGS G
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers

Definitions

  • the present invention resides in an electronic binary counter at whose output natural binary code signals appear in parallel representation, i.e., simultaneously, which counter is characterized, basically, by the following features: (1) there are adders associated with each binary digit (2, 2 2 2 the carry circuits of which adders are coupled to each other galvanically, (2) the sum signals of the adders (L or 0, where L represents binary l) are applied to output storage devices which are capable of having clock pulses applied to them, which storage devices feed these sum signals back into the same adders. and (3) one of the binary signals applied to the adder of the lowest order binary digit constantly has the value L.
  • the adders are half-adders.
  • an intermediate storage device which is capable of being operated by a clock pulse, which intermediate storage device is connected between the output storage device and the adder pertaining thereto.
  • the adders are split up in such a manner that the transfer circuit is cut into the circuit arrangement ahead of the intermediate storage device which then additionally acts as an amplifier, and that the sum circuit is cut ahead of the output storage device which then also additionally acts as an amplifier.
  • the carry and sum signals are formed and amplified by two similar logic circuits comprising AND circuits and OR/ OR NOT circuits.
  • the carry circuit comprises three AND circuits acting as a holding stage, a transient shunt stage, and an input stage, respectively, and the intermediate storage device comprises an OR/OR NOT circuit, which three AND 3,254,455 Patented August 2, 1966 circuits have their outputs connected to the OR/ OR NOT circuit from whose affirmed output the outgoing carry signalis derived.
  • the sum circuit likewise comprises three AND circuits acting as a holding stage, a transient shunt stage, and an input stage, respectively, and the output storage device comprises a further OR/ OR NOT circuit, which three last-mentioned AND circuits have their outputs connected to the last-mentioned OR/OR NOT circuit at whose affirmed output there appears the result of the sum formation.
  • the input and shunt stages of the carry circuit are connected to the output of the respective 'output storage device to receive the sum signal and also to receive the incoming carry signal arriving from the preceding digit, the input stage of the sum circuit is connected to receive the incoming carry signal arriving from the preceding digit and also to receive the negated outgoing carry signal, and the shunt stage of the sum circuit is connected to receive the negated outgoing carry signal and to the output of the respective output storage device to receive the sum signal.
  • FIGURE 1 is a schematic diagram showing a basic unit pertaining to one binary digit.
  • FIGURE 2 shows the timed relationship of clock pulse trains used in the operation of the counter according to the present invention.
  • FIGURE 3 shows three digits of a counter incorporating three units associated with the respective digits.
  • FIGURE 4 is a schematic diagram showing a modified embodiment of a basic unit forming part of a counter according to the present invention.
  • FIGURE 5 shows two interconnected units according to FIGURE 4.
  • FIGURE 6 shows the details of an adder used in the counter according to the present invention.
  • FIGURE 7 shows the details of a half-adder used in the counter according to the present invention.
  • FIGURE 8 shows the details of one embodiment of a unit incorporated in a counter according to the present invention.
  • FIGURE 9 shows a sub-assembly incorporated in the unit of FIGURE 8.
  • FIGURE 10 shows the timed relationship of the pulse trains and the erasing pulse used in the operation of the embodiment of FIGURES 8 and 9.
  • FIGURES 11, 12, 13, 14, and 15 are Tables 1, 2, 3, 4, and 4a, respectively, which will be referred to for explanatory purposes.
  • FIGURE 1 shows a binary counter according to the present invention which uses an adder whose output signal s, is applied into an output storage device AS.
  • the adder comprises a sum circuit whose inputs a, b, w have binary signals (L or 0) applied to them, while the result of the sum formation appears at the output terminal s,.
  • the adder further includes a carry circuit having an output terminal u,,. g
  • a binary number a and b is applied to the adder If there is a carry from the preceding digit, such carry is applied to input u of the adder. As indicated above, these inputs are voltage signals of given polarity which correspond to the values '0 or L. The result signal is taken from the output a, of the output storage device AS. According to the present invention, one of the input signals of the adder of the lowest binary digit always has the value L.
  • the output storage device AS being a clock pulsable component, is opened, at a given instant, by means of a timing or clock pulse t As soon as this clock pulse 1 J (for example L) appears, the sum of the adder is -taken over by the. output storage, deviceAS.
  • the result appearing at'the output a is additionally fed back and applied to an intermediate storage device ZS, the latter also being clock pulsable and controlled by a further clock pulse t
  • the clock pulses t t are staggered, as shown in FIGURE 2.
  • clock pulse 1 appear in this intermediate storage. device and hence at a.
  • the adder forms the sum -a +b.
  • the value a in this case,'be the value coming from theintermediate-storage device ZS, and .let the value b in this case (the adder being that of the lowestbinary digit) always be the value L.
  • the adder then forms a+b,.and since b is always equal to L, the value formed will always be aI-L.
  • This value is then applied, at clock pulse t to the output storage device.
  • each unit will include the adder an output storage device AS connected to the output of the adder, and an intermediate storage device ZS to which the output value is fed back.
  • the storage devices AS and ZS of each of the three units are operated by the same clock pulses t t respectively.
  • the outgoingcarry formed in any one adder is applied to the adder.
  • the adder also has an output a for the outgoing carry which is applied to the unit pertaining to the next digit.
  • the units pertaining to the subsequent digits are characterized by the same basic reference numerals, except that they incorporate, instead out the subscripts O, the subscripts I and 2, respectively.
  • the result outputs 0,0, (1, a,; are fed back to the adders via respective intermediate storage devices.
  • the value. applied to the carry input M is equal to 0, as indicated within the parentheses, while the input b has the value L applied to it and the inputs b and b each have the value 0 applied -to them.
  • s represents the sum of a +b while u represents the outgoing carry.
  • the circuit of FIGURE 3 can be simplified if the input b too, has applied to itnot the value L but the i value 0 and, instead, the carry u fior the lowest binary digit is always. made equal to L, as indicated at there? spective inputs (thevalues shown not in parentheses)., In this case the adders to can betfashioned as half-' adders. a
  • Table 2 represents the function of a half-adder.
  • Table 3 (FIGURE. 13)" again shows the formation of the sum by means-of the adders, operating on the basis of. the combinations shown in Table 2.
  • FIGURE 14 gives a tabular representation of the operation of the circuit
  • FIGURE 4a (FIG- URE 15) gives the decimal equivalent outputs derived from the output signals at outputs 61, to a,
  • the starting position of all of the units pertaining to the respective digits are in the state .0.
  • the incoming carry n L is transferred into the output storagedevice A8
  • the result appearing at the outbut a is applied to the intermediate storage device ZS whereupon this result also appears at the input a of the adder
  • a further pulsable output storage device can be connected to adder which lastmentioned storage device is subjected to a further train of clock pulses and commences to add at a later instant.
  • the half adders of FIGURE 3 carry out two operations, namely, the formation of the sum and the formation of the outgoing carry. Accordingly, each half-adder has two outputs s, u,,.
  • the outgoing carry is always applied to the next adder, whose carry, in turn, is applied to. the next following adder.
  • the carry signal becomes progressively weaker.
  • the amplifiers increase the expense of the counter, and, While an arrangement incorporating such amplifiers would be operative, it is desirable, if possible, to make do without these amplifiers, and according to another feature of the present invention, these amplifiers can be dispensed with by splitting up the formation of the sum and carry signals.
  • This feature of the present invention is based on the following considerations: the counted result of a particular binary digit is present in an output storage device pertaining to the particular digit. This result is fed back into the respective intermediate storage device. The sum and the outgoing carry are thereafter formed separately, in contradistinction to the operation of FIGURE 3. This separate sum and carry formation is shown in FIGURE 4, in which the carry a is formed ahead of the intermediate storage device ZS.
  • the intermediate storage device ZS is also used for forming the sum.
  • the sum is then applied to the output storage device AS.
  • the result appearing at the output of storage device AS is then fed back to the carry stage u.
  • the carry u coming from the preceding stage is applied to the carry forming stage it and the sum forming stage s.
  • the carry 11,, for the following uni-t is derived from the output of the intermediate storage device ZS.
  • both the sum as well as the carry have to be formed. Both processes make use of the output a, and the input carry u As shown in FIG- URE 4, the value a, goes, via the carry stage u and the intermediate storage device ZS, to the sum stage s. The outgoing carry and the sum are thus formed separately.
  • the carry stage it has a, and u applied to it, exactly as in the case of the adder of FIGURE 3.
  • the arrangement of FIGURE 4 makes it possible to dispense with the amplifiers V which, in practice, would be needed for the circuit arrangement according to FIGURE 3, the reason for this being that the intermediate storage device ZS of each binary digit can take over this amplifying function.
  • the carry, in FIGURE 4 is formed by the carry stage it which itself does not have any amplifying means, it being the intermediate storage de- 6 vice ZS which amplifies the outgoing carry signal u,,,.
  • the sum is formed in the sum stage s which itself likewise has no amplifying means, it being the output storage device AS which acts as an amplifier for amplifying the output signals, of the sum stage s.
  • FIGURE 5 shows a counter for two binary digits, which counter can, of course, be expanded to as many digits as desired.
  • Each unit of the counter of FIGURE 4 corresponds to the unit shown in FIGURE 3, the first unit including two storage device ZS A5, A nonamplifying sum stage s for forming the sum is connected ahead of the output storage device AS there being a nonamplifying carry stage u for forming the outgoing carry connected ahead of the intermediate storage device ZS The outgoing carry u is applied to the succeeding carry stage u and sum stage s The carry stage u, has its output connected to the input of the intermediate storage device ZS while the output of sum stage s is connected to the input of the output storage device AS For purposes of sum formation, the output value a is fed back to the arry age l- It will be seen from the above that, in the counter of FIGURE 5, the adder of each unit of FIGURE 3 is, in effect, divided into independent sum and carry stages without amplification, the intermediate storage device now being additionally used as a means for amp
  • FIGURE 6 shows the adder of FIGURE 3 with its component sub-parts.
  • FIGURE 7 shows, in schematic form, one embodiment of such a half-adder.
  • An AND circuit &' is provided which serves for forming the carry, the inputs of this AND circuit having the values a, and li applied thereto.
  • the output of this AND circuit & produces the outgoing carry u,,,.
  • This AND circuit does not amplify the carry signal; if such amplification is to be obtained, two amplifier stages, for example transistorized NOT circuits, would have to be provided, as indicated by stages N and N.
  • each adder requires four NOT circuits N, N N", N-".
  • N, N N, N- In the case of the counters according to FIG- URES 4 and 5, these NOT circuits are eliminated, anc' their functions are taken over by the intermediate and output storage devices which must in any case be provided.
  • FIGURES 8 and 9 show the details of the counter 01 FIGURES 4 and 5. More particularly, the circuit arrangement of FIGURE 8 corresponds to that of FIGURE 4 and illustrates a single unit of the counter pertaining tc me binary digit. The unit usesstorage devices whose hange-over characteristics (signal changes from Lto r vice versa) are such that they will not assume the wrong ircuit condition (L or 0).
  • FIGURE, 9 shows a sub- .ssembly of the unit of FIGURE 8, which subassembly :omprises three AND circuits 8: & & whose outputs re applied to an OR circuit v, the output of the latter, in
  • the three IND circuits constitute either the carry circuit u or; the,
  • device ZS if the three AND cir-1 uits are the carry circuit u or the output storage device lulse 7.
  • the AND circuit & has applied to it the afiirmed lock pulse 1 and the input value e to be stored (L or 0).-
  • the signal e lasts longer than the clock pulse 1, .nd thanks to the transient shunt aiforded by AND ciruit & the values of the clock pulses 1-, a can change without this causing the value appearing at output a to hange.
  • the holding stage & maintains the value at utput u, even when the clock pulse ,7, after having asumed the value L, thereafter assumes the value 0.
  • the clock pulse : L and if, for. example,
  • the counter unit according to FIGURE 8 shows two hose output, in turn, is connected to the OR NOT ciruit E. These components serve to form and amplify 1e outgoing carry. Similarly, the AND circuit &' con.-
  • the AND'circuit 8 constituting the holding stagev of he carry circuit, has applied to it the clock pulse 1- as lell as the fed back signal u appearing at the output a f the OR NOT circuit E.
  • the AND circuit & constiuting the transient-shunt stage has applied to it the signal Y appearing at output a, as well as the input signal which tself is made up of two components. ndicated by the encircled leads, consists of a, and u,,,, rom which a is formed. This corresponds to the arangernent depicted in FIGURE .7. In FIGURE 8, a,
  • the output storage device AS at Whichthe circuit which, technically, constitutes the overall storage unit of which the output storage device AS is. a part: The result appearing at a, and the applied incoming carry u thus constituteinput signals which are combined with each other via the AND circuits 8: & thereby forming the.
  • the AND circuit & constituting the input stage also has the clock pulse 1- applied to it.
  • the input stage & also has the clock pulse r applied to it.
  • the holding stage & is connected in the same manner as holding stage.& except'that the applied clock pulse is
  • the transient shunt stage &.' has appliedto itthe output a, of the output storage device AS and the negated outgoing carry'fi iof the'intermediate storage'device ZS.
  • the outgoing carry u is formed in the intermediate.
  • FIGURE 10' shows the timed relationship .of the clock pulsesn- 1 ,1- aand the erasing pulses l, T.
  • the value 0 can, for example,.be equal to a given negative voltage and the value L be equal to a .givenpositive voltage,- or
  • the counter can be erased, i.e., reset, when the clock 1 pulses the incoming carry signal it and the erasing signal I are made equal to 0.
  • the clock pulses 7- 2,;0 theholding action via holding stages & &' is discontinued.
  • (c) means for constantly applying the value L as one of the binary signals applied to the adder associated with the lowest binary digit;
  • each intermediate storage device having an input connected to receive said output from the respective output storage device and an output connected to deliver the sum signal to said input of the respective adder;
  • said carry circuit comprises three AND-circuits constituting a holding stage, a transient shunt stage, and an input stage,
  • said intermediate storage device comprises an OR/ OR NOT-circuit, the outputs of said AND- circuits being connected to said OR/OR NOT-circuit from whose afi'irmed output the outgoing carry signal is taken oif;
  • said sum circuit comprises three further AND-circuits constituting a holding stage, a transient shunt stage, and an input stage, respectively, and said output storage device comprises a further OR/ OR NOT- circuit, the outputs of said last-mentioned three AND- circuits being connected to said last-mentioned OR/OR NOT-circuit from whose affirmed output the result of the sum formation appears;
  • said input and shunt stages of said carry circuit are connected (1) to the output of the respective output storage device to receive the sum signal and (2) to receive the incoming car-ry signal arriving from the preceding digit;
  • saidinput stage of said sum circuit is connected (1) to receive the incoming carry signal arriving from the preceding digit and (2) to receive the negated outgoing carry signal; and wherein said shunt stage

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US250341A 1962-01-09 1963-01-09 Binary counter Expired - Lifetime US3264455A (en)

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DEL40894A DE1240928B (de) 1962-01-09 1962-01-09 Gleichstromgekoppelter elektronischer Binaerzaehler

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3375350A (en) * 1962-11-28 1968-03-26 Licentia Gmbh Static counter having main and auxiliary stores
US3377468A (en) * 1963-08-05 1968-04-09 Licentia Gmbh Counter equipped with signal sorting out and suppressing means
US3387118A (en) * 1962-11-28 1968-06-04 Licentias Patent Verwaltungs G Static counter having main and aluxiliary stores and controlled by staggered counting and auxiliary counting signals
US3402283A (en) * 1965-01-21 1968-09-17 Jeumont Schneider Conditional jump sequencing arrangement for a counter register of a computer

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2803401A (en) * 1950-10-10 1957-08-20 Hughes Aircraft Co Arithmetic units for digital computers
US2962212A (en) * 1956-06-22 1960-11-29 Bell Telephone Labor Inc High speed binary counter
US3125676A (en) * 1961-11-30 1964-03-17 jeeves
US3125675A (en) * 1961-11-21 1964-03-17 jeeves
US3185822A (en) * 1958-08-05 1965-05-25 Ibm Binary adder

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2803401A (en) * 1950-10-10 1957-08-20 Hughes Aircraft Co Arithmetic units for digital computers
US2962212A (en) * 1956-06-22 1960-11-29 Bell Telephone Labor Inc High speed binary counter
US3185822A (en) * 1958-08-05 1965-05-25 Ibm Binary adder
US3125675A (en) * 1961-11-21 1964-03-17 jeeves
US3125676A (en) * 1961-11-30 1964-03-17 jeeves

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3375350A (en) * 1962-11-28 1968-03-26 Licentia Gmbh Static counter having main and auxiliary stores
US3387118A (en) * 1962-11-28 1968-06-04 Licentias Patent Verwaltungs G Static counter having main and aluxiliary stores and controlled by staggered counting and auxiliary counting signals
US3377468A (en) * 1963-08-05 1968-04-09 Licentia Gmbh Counter equipped with signal sorting out and suppressing means
US3402283A (en) * 1965-01-21 1968-09-17 Jeumont Schneider Conditional jump sequencing arrangement for a counter register of a computer

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GB1029691A (en) 1966-05-18
CH409005A (de) 1966-03-15
DE1240928B (de) 1967-05-24

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