US3302170A - Traffic light control buffer - Google Patents

Traffic light control buffer Download PDF

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Publication number
US3302170A
US3302170A US363147A US36314764A US3302170A US 3302170 A US3302170 A US 3302170A US 363147 A US363147 A US 363147A US 36314764 A US36314764 A US 36314764A US 3302170 A US3302170 A US 3302170A
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United States
Prior art keywords
light
registers
traffic light
counter
traffic
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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US363147A
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English (en)
Inventor
Robert A Jensen
Wilbur J Levine
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International Business Machines Corp
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International Business Machines Corp
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Priority to US363147A priority Critical patent/US3302170A/en
Priority to GB12003/65A priority patent/GB1041682A/en
Priority to DEJ27877A priority patent/DE1278298B/de
Priority to AT330665A priority patent/AT258173B/de
Priority to FR14325A priority patent/FR1431564A/fr
Application granted granted Critical
Publication of US3302170A publication Critical patent/US3302170A/en
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G08—SIGNALLING
    • G08G—TRAFFIC CONTROL SYSTEMS
    • G08G1/00—Traffic control systems for road vehicles
    • G08G1/07—Controlling traffic signals
    • G08G1/081—Plural intersections under common control

Definitions

  • CENTRAL PROCESSOR PERIOD DURATION VALUES PERIOD I READ-IN 1 i 17C 18C "'19C 17a 18b 7/CL00K PULSES I 21 20c I 19b I READ IN coIITRoI BUFFER BUFFER I BUFFER CONTROLLER CONTROLLER CONTROLLER (FIG. 2) 5 (FIR 2I ⁇ IRb (FIG. 2) 5 I f I 23 I #431:
  • This invention relates to systems for controlling traffic lights, and more particularly to a buffer controller which stores commands from a central processor and independ ently guides the operation of a traffic light.
  • the high density of trafiic in cities has brought about the use of highly complex control systems for controlling tratlic lights to relieve the traffic congestion.
  • Some of the control systems sample the trafiic at various points in the city and process the samples at a central processor to determine the manner in which the individual traffic lights should be operated in order to provide the most effective use of the roads.
  • control system described above employ a central processor which processes the data and computes the optimum manner in which the trafiic lights may be controlled.
  • the central processor is often a computer or other complex device for performing calculations and storing data.
  • the traffic lights are controlled directly by the central processor, a great deal of time and apparatus of the central processor is used to generate control signals to actuate the traffic lights.
  • Still another object of the present invention is to provide a traflic control system employing a minimum amount of control circuitry and other apparatus.
  • the buffer controller located between each trafiic light and the central processor.
  • the buffer controller stores commands sent by the central processor and guides the operation of the associated traffic light. The same repetitive operation is performed until a new command is sent from the central processor.
  • a number of registers one for each light energizing period (hereinafter called period) of the light cycle are included in the buffer controllers.
  • the registers store signals supplied by the central processor and are read out one by one in a sequential fashion.
  • the values stored in each register determine the length of the red, green and amber periods of the traflic light.
  • signals are fed back from the trafiic light to the associated buffer controller indicating the present period of the trafiic light. These signals are compared with the operation of the buffer controller to determine whether both are synchronized in operation. If not, the buffer controller automatically provides a series of signals to advance the operation of the trafiic light until synchronism is achieved.
  • FIG. 1 is a block diagram illustrating the general op eration of a trafiic control system employing the present invention.
  • FIG. 2 is a detailed block diagram illustrating the contents of the buffer controllers shown in FIG. 1.
  • FIG. 1 A traffic control system is shown in FIG. 1.
  • Three traffic lights Ila-c are controlled by three bufier controllers 13a-c.
  • the butter controllers 13a-c receive commands from a central processor 15 through a group of connections 17a-c, 1311-6, 1941-0, 200-0 and 21.
  • the bufiier controllers 13a-c store the commands from central processor 15 and provide signals on a group of lines 23a-c which are connected to stepper switches ZSa-c respectively. Stepper switches 25a-c advance the operation of trafiic lights Ila-c respectively in response to the signals on lines 23a-c.
  • the cycle of operation of trafiic lights Ila-c includes three periods. During the first period, the red indicators designated by the letter R as shown in FIG. 1 are illuminated. During the second and third periods the amber and green indicators designated by A and G are illuminated. Stepper switches ZSa-c advance the operation of the associated trafiic lights. Ila-c so that the indicators are illuminated in a sequential fashion, i.e., green, amber, red, green, etc. A group of connections 27a-c feed back signals identifying which indicatorin the associated traffic light Ila-c is illuminated. The signals in connections 27a-c are used to synchronize the operation of butter controllers 13a-c with the operation of trafiic lights Ila-c in a manner to be described in detail with reference to FIG. 2.
  • FIG. 2 illustrates the details of the butter controllers 13a-c shown in FIG. 1. The same designations are applied to the connections shown in FIGS. 1 and 2 with the exception of the letter designations a-c which are omitted in FIG. 2 since all three buffer controllers 13a-c are identical.
  • FIG. 2 Three registers 31-33 are shown in FIG. 2 which store 6-bit binary numbers representing the time duration of the red period, green period and amber period of the traffic light cycle.
  • Each of the registers 31-33 contain six conventional triggers arranged to turn on and off in response to six inputs as shown in FIG. 2.
  • Each of the triggers in registers 31-33 provides an output indicating whether the trigger is on or oil.
  • Registers 31-33 are supplied with inputs via a group of AND gates 41-43 which are opened one at a time by signals on connector 18 from the central processor 15.
  • Each of the AND gates 41-43 includes six AND gates, one for each line in connector 17. When one of the AND gates 41-43 is opened the signals on connector 17 are fed to the associated one of the registers 31-33.
  • commands are sent from the central processor 15 via connection 18 to open the corresponding one of the AND gates 41-43.
  • signals are supplied via connection 17 setting the six triggers in one of the registers 31-33 corresponding to the particular period to be adjusted.
  • each of the registers 31-33 There are 2 or 64 different possible settings of the six triggers in each of the registers 31-33. Therefore the interval of each of the periods can be made to vary between 1 and 64 units of time.
  • the number of triggers in each of the registers 31-33 can be expanded or contracted to suit the requirements of the trafiic control system. Also a variety of binary codes can be used to convert each period duration into a particular set of trigger conditions.
  • the outputs of registers 31-33 are fed through a group of AND gates 51-53 which are opened one at a time in a manner to be described later in the specification.
  • Each of the AND gates 51-53 includes six AND gates, one for each trigger in the register connected thereto.
  • the output of AND gates 51-53 is fed to an OR gate 55 which provides the input to a counter 57.
  • the counter 57 includes six conventional triggers arranged to receive the output of one of the registers 31-33, depending upon which one of the AND gates 51-53 is open.
  • the counter 57 also receives a series of clock pulses on a line 21' originating on line 21 from a central processor in a manner to be described in detail later in the specification.
  • the interconnections between the six triggers in counter 57 are arranged so that the clock pulses on line 21 cause the triggers to return to the off state after a number of clock pulses are received equal to the units of time represented by the trigger setting initially placed in counter 57.
  • the fifth trigger designated 5
  • the fifth trigger designated 5
  • the fifth trigger is turned on while the remaining triggers are turned off.
  • 16 clock pulses are received on line 21 all of the triggers are turned to the off state.
  • the specific interconnections between the six triggers in counter 57 for accomplishing this function are well known in the art and are not shown herein.
  • weights may be assigned to the trigger positions in counter 57 so that various other interconnections between the six triggers in counter 57 may be employed to perform the function of counting the number of clock pulses on line 21' corresponding to the number of units of time represented by the particular initial setting of the six binary triggers in counter 57.
  • Each of the six triggers in counter 57 supplies an output when the trigger is off.
  • an AND gate 59 provides a pulse on a line 61.
  • the pulse passes through an OR gate 63 to line 23 connected to a stepper switch 25 which advances a traffic light 11 as described above with reference to FIG. 1.
  • the pulse on line 61 is also fed to a ring circuit 65 having three stages designated 1, 2 and 3.
  • the stages are operated in a sequential manner in response to the pulses on line 61, i.e. stages 1, 2, 3, 1, etc.
  • the output of stages 1-3 of ring circuit 65 are connected to AND gates 51-53 respectively.
  • ring circuit 65 advances to the next stage opening another one of AND gates 51-53 and placing the contents of one of the registers 31-33 into counter 57.
  • AND gate 59 provides a pulse on line 61 thereby advancing ring circuit 65 resulting in the transfer of the contents of another one of the registers 31-33 into counter 57.
  • the clock pulses applied on line 21 are delayed before arriving at counter 57 via line 21.
  • the offset is needed only once at the beginning of the operation of the buffer controller 13 and need not be repeated each time the buffer 13 completes a cycle of operation.
  • a counter 57 identical to counter 57 is provided in FIG. 2 to perform the offset operation.
  • the value of the offset is set into counter 57' via connection 19.
  • the clock pulses on line 21 are blocked from counter 57 by a signal on line 20 which resets a trigger 67 inhibiting an AND gate 69 from passing the clock pulses on line 21 to the input of counter 57 via line 21'
  • the clock pulses on line 21 are applied to the input of counter 57'.
  • AND gate 59 is conditioned providing an output which sets trigger 67 thereby opening AND gate 69.
  • the clock pulses on line 21 pass through AND gate 69 at this time causing the counter 57 to begin operating in the manner described above.
  • the delayed commencement of operation of counter 57 provides the ofiset necessary to permit continuous flow of traffic through a plurality of innersections.
  • connection 27 includes three lines 27R, 276 and 27A which provide signals to a group of AND gates 71R, 71G, 71A when the red, green or amber indicators are illuminated respectively.
  • Stages 1-3 of ring circuit 65 supply a second input to AND gates 71R, 71G and 71A, respectively.
  • the output of AND gates 71 is applied to a three-way exclusive OR circuit 73 which provides an output whenever only one input is provided by AND gates 71.
  • An inverter '75 supplies OR gate 63 with an inverted form of the output of exclusive OR circuit 73.
  • inverter 75 supplies a signal to OR gate 63 which in turn advances the operation oftraffic light 11 when the ring 65 and traffic light 1.1 are out of synchronism.
  • the first stage of ring circuit 65 supplies a signal to AND gate 71R while the green indicator of trafiic light 11 is illuminated causing a signal to be applied to AND gate 71G.
  • none of the AND gates '71 supplies a signal to exclusive OR circuit 73 and no output signal is supplied to inverter 75.
  • a signal is provided at the output of inverter 75 which passes through OR gate 63 advancing the operation of trafiic light 11 from green to amber.
  • AND gate 71A receives a signal from line 27A and inverter 75 supplies a signal to OR gate 63 causing stepper switch 25 to continue advancing thereby changing traffic light 11 from the amber period to the red period.
  • OR gate 63 With the ring circuit 65 remaining in the first stage and trafiic light 11 in the red period both inputs to AND gate 71R are present and a signal is applied to exclusive OR circuit 73.
  • the exclusive OR circuit 73 provides a signal to inverter 75 which in turn inverts the signal causing the absence of a signal at OR gate 63 thereby permitting traffic light 11 to rest in the red period until counter 57 supplies a signal to OR gate 63.
  • a buffer controller circuit 13 which relieves the central processor 15 from the continuous control of traflic lights 11.
  • the individual period duration values are set into the registers 31-33 shown in FIG. 2 along with the particular offset value which is set into counter 57'.
  • the central processor 15 merely supplies clock pulses on lines 21 causing the buffer controllers 13 to guide the trafiic lights 11 through the same operating cycle in a repetitive manner until adjustments of the period duration values become necessary. Further the buffer cont-rollers 13 may be arranged to supply their own clock pulses thereby achieving completely independent operation.
  • the buffer controllers 13 may be located near the central processor 15 while the stepper switches 25 may be located near the traffic light-s 11 in accordance with the preferred embodiment of the present invention.
  • the stepper switches 25 may be provided with an internal control which causes the switches to advance the trafiic lights 11 in a predetermined manner should the advance signals on lines 23 fail to arrive after a certain interval of time.
  • the buflfer controllers 13 resume control over the traffic lights 11 automatic synchronization is accomplished by AND gates 71, exclusive OR circuit 73 and inverter 75 in the manner described above with regard to FIG. 2.
  • controller means actuating said switch means for advancing a traflic light display through a cycle including a plurality of light energizing periods in response to a series of clock pulses, said controller means comprising:
  • counting means for counting a number of said clock pulses corresponding to the number stored in each one of said registers and for providing a control sig nal to advance said traflic light dislay at the completion of each clock pulse count corresponding to said numbers stored in said registers.
  • controller means actuating said switch means for advancing a trafiic light display through a cycle including a plurality of light energizing periods in response to a series of clock pulses, said controller means comprising:
  • each one capable of storing numbers representing the duration of a light energizing period of said cycle
  • counting means capable of counting a number of said clock pulses corresponding to numbers applied thereto and providing a control signal to advance said trafiic light display after a number of clock pulses corresponding to the number applied thereto has been counted;
  • gating means for applying the number stored in each 5 register to said counting means one by one in a sequential fashion.
  • controller means actuating said switch means for advancing a t-rafiic light display through a cycle including a plurality of light energizing periods in response to a series of clock pulses, said controller means comprising:
  • each one capable of storing numbers representing the duration of a light energizing period of said cycle
  • counting means capable of counting a number of said clock pulses corresponding to the number applied thereto;
  • sensing means for sensing the end of said count and for providing a control signal to advance said traffic light display
  • gating means for applying the number stored in each register to said counting means one by one in a sequential fashion.
  • said gating means includes means for applying the number stored in each one of said registers to said counting means in response to said control signal.
  • Apparatus as defined in claim 5 further characterized by the addition of offset means for inhibiting the operation of said counting means for a certain number of clock pulses at the beginning of said series of clock pulses, whereby the cycle of said traffic light display is delayed.
  • a traflic light control system for controlling the operation of a traflic light display containing a plurality of indicators, means for synchronizing the operation of said controller and said trafiic light display, said means comprising:
  • timing means having a plurality of stages, each stage corresponding to a different one of said indicators,
  • exclusive OR means having inputs connected to said AND gate outputs and having an output signal
  • stepping switch means for sequentially actuating said indicators in response to said output signal, whereby said tralfic light display is advanced until the indicators and the corresponding timing means stages are synchronized in operation.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Traffic Control Systems (AREA)
US363147A 1964-04-28 1964-04-28 Traffic light control buffer Expired - Lifetime US3302170A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US363147A US3302170A (en) 1964-04-28 1964-04-28 Traffic light control buffer
GB12003/65A GB1041682A (en) 1964-04-28 1965-03-22 Traffic light control system
DEJ27877A DE1278298B (de) 1964-04-28 1965-04-09 Verfahren und Anordnung zur Steuerung von Verkehrsampeln
AT330665A AT258173B (de) 1964-04-28 1965-04-09 Schaltungsanordnung für Verkehrssignalanlagen mit einer zentralen Steuervorrichtung und mehreren, von dieser beeinflußbaren Pufferschaltern
FR14325A FR1431564A (fr) 1964-04-28 1965-04-23 Mémoire tampon pour la commande de feux de signaliation

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US363147A US3302170A (en) 1964-04-28 1964-04-28 Traffic light control buffer

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DE (1) DE1278298B (de)
GB (1) GB1041682A (de)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3363185A (en) * 1965-05-04 1968-01-09 Sperry Rand Corp Auxiliary reference signal generating means for controlling vehicular traffic flow or other moving elements
US3375494A (en) * 1963-09-11 1968-03-26 Siemens Ag Control units for programmed operation of traffic signals
US3434115A (en) * 1966-07-15 1969-03-18 Ibm Timed operation sequence controller
US3482208A (en) * 1966-02-21 1969-12-02 Gen Signal Corp Traffic signal control system
US3579207A (en) * 1967-11-14 1971-05-18 Gulf & Western Industries Load sequencer controller
US3675196A (en) * 1971-01-25 1972-07-04 Computer Systems Eng Inc Traffic signal control system
US3754210A (en) * 1971-03-30 1973-08-21 Fabrication D Instr De Mesure Traffic light control systems
US3764973A (en) * 1970-04-14 1973-10-09 Omron Tateisi Electronics Co Traffic signal control device
US3828307A (en) * 1971-06-29 1974-08-06 Georgia Tech Res Inst Automatic traffic control system
US3872422A (en) * 1972-06-15 1975-03-18 Siemens Ag Street traffic signalling system
US3893067A (en) * 1972-03-16 1975-07-01 Omron Tateisi Electronics Co Traffic signal control system
US4167785A (en) * 1977-10-19 1979-09-11 Trac Incorporated Traffic coordinator for arterial traffic system
USRE31044E (en) * 1977-10-19 1982-09-28 TRAC, Inc. Traffic coordinator for arterial traffic system
US6331824B1 (en) 2000-08-10 2001-12-18 Paul A. Firestone Traffic control signal with displayed time-elapse

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3072883A (en) * 1958-07-03 1963-01-08 Gamewell Co Traffic controllers employing static, logic control elements
US3090032A (en) * 1956-08-29 1963-05-14 Ass Elect Ind Manchester Ltd Automatic traffic signalling systems

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1198254B (de) 1960-09-30 1965-08-05 Siemens Ag Strassenverkehrssignalanlage

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3090032A (en) * 1956-08-29 1963-05-14 Ass Elect Ind Manchester Ltd Automatic traffic signalling systems
US3072883A (en) * 1958-07-03 1963-01-08 Gamewell Co Traffic controllers employing static, logic control elements

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3375494A (en) * 1963-09-11 1968-03-26 Siemens Ag Control units for programmed operation of traffic signals
US3363185A (en) * 1965-05-04 1968-01-09 Sperry Rand Corp Auxiliary reference signal generating means for controlling vehicular traffic flow or other moving elements
US3482208A (en) * 1966-02-21 1969-12-02 Gen Signal Corp Traffic signal control system
US3434115A (en) * 1966-07-15 1969-03-18 Ibm Timed operation sequence controller
US3579207A (en) * 1967-11-14 1971-05-18 Gulf & Western Industries Load sequencer controller
US3764973A (en) * 1970-04-14 1973-10-09 Omron Tateisi Electronics Co Traffic signal control device
US3675196A (en) * 1971-01-25 1972-07-04 Computer Systems Eng Inc Traffic signal control system
US3754210A (en) * 1971-03-30 1973-08-21 Fabrication D Instr De Mesure Traffic light control systems
US3828307A (en) * 1971-06-29 1974-08-06 Georgia Tech Res Inst Automatic traffic control system
US3893067A (en) * 1972-03-16 1975-07-01 Omron Tateisi Electronics Co Traffic signal control system
US3872422A (en) * 1972-06-15 1975-03-18 Siemens Ag Street traffic signalling system
US4167785A (en) * 1977-10-19 1979-09-11 Trac Incorporated Traffic coordinator for arterial traffic system
USRE31044E (en) * 1977-10-19 1982-09-28 TRAC, Inc. Traffic coordinator for arterial traffic system
US6331824B1 (en) 2000-08-10 2001-12-18 Paul A. Firestone Traffic control signal with displayed time-elapse
USRE40737E1 (en) 2000-08-10 2009-06-16 Firestone Paul A Traffic control signal with displayed time-elapse

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GB1041682A (en) 1966-09-07
AT258173B (de) 1967-11-10
DE1278298B (de) 1968-09-19

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