US3426185A - Accumulator for performing arithmetic operations - Google Patents

Accumulator for performing arithmetic operations Download PDF

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US3426185A
US3426185A US517563A US3426185DA US3426185A US 3426185 A US3426185 A US 3426185A US 517563 A US517563 A US 517563A US 3426185D A US3426185D A US 3426185DA US 3426185 A US3426185 A US 3426185A
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bit
accumulator
trigger
carry
circuit
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Cecil Wayne Cox
Louis M Hornung
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/498—Computations with decimal numbers radix 12 or 20. using counter-type accumulators
    • G06F7/4981—Adding; Subtracting

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  • the invention relates to accumulator circuits combining shift register operation and accumulating operation. Arithmetic factors with 1 2-4-48 weighted bit positions, and other factors, such as the corrective six and corrective ten, are applied serial-by-bit, serial-by-digit to a common trigger position, Carry (CY), and are supplied for utilization from the same trigger position (CY). Each bit interval includes a counting sub-interval and shifting sub-interval.
  • the invention is disclosed in connection with the processing of binary coded decimal (BCD) digits, but lends itself readily to arithmetic processing of numeric factors based on a variety of radices, such as radix 12 or radix 20.
  • Arithmetic processing of BCD digits usually involves consideration of corrective factors, such as the corrective 6 and corrective l0.
  • Processing of radix l2 digits entails consideration of a corrective 4 and corrective l2, while radix involves a corrective 12 and 20. Because of the wide spread use of the BCD representation, the present invention is explained in connection with the processing of BCD digits.
  • each numeric digit is represented by weighted bits according to a 1-2-4-8 format.
  • the various weighted portions of the digital 1 2-4-8 representations be taken into account, that carries resulting from the accumulation of one ordinal digit position of factors be considered properly as the next ordinal position is processed, and that various controls be established for handling operations other than addition, such as subtraction by complementing, and similar matters.
  • the representation of numbers in the binary coded decimal format provides advantages when entering information or extracting information from a data processing system.
  • an object of the present invention is to provide improved accumulator circuits for more efficient arithmetic operations.
  • Another object of the invention is to provide circuits for performing arithmetic operations in a more simplified fashion.
  • Still another object of the invention is to provide accumulator circuits for processing arithmetic factors in a serial, intermixed manner.
  • a further object of the invention is to provide circuits for arithmetically processing binary coded decimal factors with minimum operating complexities.
  • Another object of the invention is to provide binary coded decimal accumulator circuits for performing a variety of arithmetic operations, including addition and subtraction.
  • Still another object of the invention is to provide accumulator circuits wherein corrective operations are performed concurrently with the processing of numerically significant factors.
  • accumulator circuits are disclosed herein in accordance with a preferred embodiment wherein the advantages of shift register operation and accumulating operations are combined, thereby resulting in a simplified processing of arithmetic factors.
  • the accumulator circuits according to the present invention develop arithmetically correct outputs while responding to inputs representative of arithmetic factors, and other factors, such as the corrective six and corrective ten, in a completely intermixed serial by bit, serial by digit manner. Regardless of arithmetic significance, or origin, all factors involved in arithmetic operations are applied to a common trigger position in the accumulator and are supplied for utilization from the same trigger position.
  • the various trigger positions of the accumulator are assigned significant arithmetic designations, such as, Carry-one bit-two bit-four bit-eight bit, such designations are applied for convenience only, and the various trigger positions are used for storing bit representations having varying amounts of weighted significance during arithmetic operations.
  • the arithmetic processing of two binary coded decimal factors including the development of a sum during addition or a difference during subtraction, together with the consideration of necessary corrective factors, and also including the reading of factors from memory and writing a new sum or difference into memory, comprises only two digital cycles of operation. With all factors, arithmetic and corrective, applied to a common trigger input, appropriate shifting is provided for during any arithmetic operation to insure that the weighted significance of the binary coded decimal bit positions is properly accounted for, and that other significant matters, such as carry from one ordinal position to another, are also properly accounted for.
  • the accumulator circuits combine the attributes of a counting accumulator and a shift register by appropriate interconnection of trigger positions. This insures that all inter-bit carries occurring within any binary coded decimal bit time, such as one bit, two bit, four bit, or eight bit time can be accommodated, and also insures that inter-digital carries are properly shifted and retained for later use. No special handling of carries from one ordinal position to another of two numbers being processed is required.
  • FIG. 1 represents a data processing system that incorporates the accumulator circuits of the present invention.
  • FIGS. 2a and 2b are detail and block representations, respectively, of a trigger circuit that is useful in the accumulator of the present invention.
  • FIG. 3 shows suggested circuits for developing clock pulses required during operation of the accumulator circuits.
  • FIG. 4 shows the accumulator and associated arithmetic control circuits including input, output, and gating networks.
  • FIGS. 5a and 5b when joined as shown in FIG. 6, together represent two digital clock times as required for adding two binary coded decimal factors while handling corrections required.
  • FIG. l is a system for processing binary coded decimal data that incorporates the accumulator circuits of the present invention.
  • Numerical data in BCD form is stored in memory 1.
  • the numerical data is stored as words, each word comprising a number of digits having weighted bits of 1 4-8 significance.
  • An arithmetic operation involves the summation or subtraction of words that are designated as A Word and B Word. ⁇ During arithmetic operations the bits of the A Word and B Word involved are sensed alternately in increasing order of significance.
  • a memory sensing block 2 that includes a Sense Amplifier (SA) and a storage (S) trigger, shown in more detail in FIG. 4.
  • SA Sense Amplifier
  • S storage
  • Arithmetic operations are primarily under control of a clock 3 that is shown in more detail in FIG. 3.
  • Clock 3 controls memory control 4 as well as arithmetic control 5.
  • Arithmetic factors and correction factors are developed through arithmetic control 5 and applied to the shifting accumulator 6 by line 7. Outputs from shifting accumulator 6 are supplied by line 8 to memory control 4 for return to memory 1.
  • the arithmetic control circuits, shifting accumulator circuits, and output to memory gate are shown in detail in FIG. 4. The various detailed circuits referred to in other figures will be discussed in later sections.
  • FIG. 2a A trigger circuit that is useful in the shifting accumulator 6, FIG. 1, is illustrated in detail in FIG. 2a and shown in block form in FIG. 2b.
  • the trigger circuit is provided with a number of input and output terminals designated A-R with corresponding terminals being comparably designated in both FIGS. 2a and 2b.
  • the trigger circuit, FIG. 2a comprises two AOI blocks in dashed lines at 11 and 12 that include transistors 13 and 14, respectively. In the normal or zero state of the trigger circuit, transistor 13 is cut off, thereby supplying a +12 volt output at terminal A. Transistor 14 is on and the one output at terminal B is at a ground or logical Zero level.
  • the state of the trigger is changed by application of appropriate DC levels or AC signals to the various input terminals.
  • any of the DC inputs G, I or K is dropped to a zero level. This turns off transistor 14, raises terminal B to approximately +12 volts and thereby gives a one indication.
  • the trigger circuit can be reset to the zero state by DC levels applied to terminals H, I, and L.
  • Trigger cross-coupling is controlled by signals applied to inputs G and H from AOI blocks 11 and 12, respectively.
  • the state of the trigger can also be modified by application of alternating signals to AC inputs M, N, P or R, if an associated gate E, D, F or C, respectively, is conditioned.
  • a gate is conditioned when its input is at ground.
  • a negative shift to terminal M will set the trigger circuit to the one state.
  • terminal C is low, a negative shift to terminal R will also set the trigger to the one state.
  • the double AC inputs are used primarily in connection with the Carry (CY) trigger, the P1 trigger, and the P2 trigger, used in the accumulator, FIG. 4.
  • One set of AC inputs is used for shifting purposes and another set is used for counting purposes.
  • Triggers P4 and P8, FIG. 4 have only a shifting capability and, therefore, do not require the double AC inputs.
  • the clock circuit supplies various clock pulses shown in greater detail in the timing charts of FIGS. 5a and 5b.
  • the clock circuit includes an oscillator circuit that drives a number of trigger stages designated TD, TE, TF, TG, TH, and TI, and other logical circuits designated LI and WS. Reference is made to the abbreviations and symbols table lpreviously given for the symbol designations.
  • the various clock pulses are provided to access the A and B Words from memory 1, FIG. 1, and to gate the appropriate logical networks in FIG. 4 for operation of the accumulator.
  • an A word 'bit is accessed during TG clock time and a B word bit is accessed during a Not TG clock time.
  • the word single shot (WS) supplies a strobe impulse from terminal 16 that is applied to terminal 17, FIG. 4, to strobe the data from memory 1 into the sense amplifier (SA).
  • SA sense amplifier
  • the operation of the clock circuits, FIG. 3, establish a number of signicant data bit times designated T1, T2, T4, T8, A1, A2, A4, and A8, as seen in FIGS. 5a and 5b.
  • Various combinations of the clock outputs are combined in logical circuits including And (&) circuits, Or circuits, and Invert (I) circuits, FIG. 4. These include a number of special pulses as shown in the lower portion of FIGS. 5a and 5b, and indicated in the abbreviations and symbols table. A brief review of the special pulses made available in the logic of FIG. 4 may be -useful.
  • the Shift pulses (SP) are generated at junction 20, FIG. 4, from And circuits 21 and 22 and applied to all accumulator positions by line 23.
  • the accumulator triggers are arranged as a closed loop shift register, with data shifted from Carry to P8, P1 to Carry, P2 to P1, P4 to P2, and P8 to P4.
  • Arithmetic control and accumulator-FIG URE 4 The detailed logic required for the arithmetic control circuits and the accumulator circuits, briefly discussed in connection wit-h the clock circuits, are shown in FIG. 4.
  • the accumulator comprises 5 trigger positions designated Carry (CY), P1, P2, P4 and P8.
  • the various trigger positions of the accumulator are selectively reset by impulses provided on line .30.
  • all data and correction bits are supplied to the Carry trigger position Iby impulses on the data line 31.
  • Timing for the data impulses is derived from the And circuits 32.
  • Other And circuits 33, 34, 35, 36, and 37 supply appropriate gating through an Or circuit 38 for operation of the accumulator.
  • And circuit 33 provides data inputs under control of the U signals on line 27.
  • And circuit 34 provides signals representative of the 2 bit and 4 bit of the corrective six.
  • ⁇ circuit 35 provides the 2 bit of the corrective ten.
  • circuit 36- provides the 8 bit of the corrective ten, and
  • circuit 37 is operative during a subtract operation to provide an elusive one input to the accumulator.
  • All data from memory is provided on lines 4t) ⁇ and 41 to the Sense amplifier 42 under control of the Strolbe And circuit 43. Data bits are then directed rby line 25 to the Storage trigger 44.
  • Complementing circuitry designated 45 provides A word data bits through And circuit 46 and B word data -bits through And circuit 47 during an Add operation. Subtraction using the accumulator circuits disclosed yherein is performed by complementary addition. During a Subtraction operation, the A word bits represent the rninuend and the B word lbits represent the subtrahend. Only the subtrahend -bits need be complemented and this is :performed during the subtract operation under control of And circuit 48, FIG. 4.
  • the accumulator of FIG. 4 responds to the data and correction bits supplied on line 31 and at proper times provides significant data bits by line 50l to And circuit 51 that are in turn gated to memory control 4, FIG. 1, by line 8.
  • T ypcal arthemetc operation-Addilion of Carry -l- A Word B Word-FIGURES 5a and 5b In order to illustrate the simplicity of gating and overall eiciency of operation of the accumulator circuits of the present invention, a typical arithmetic operation has been depicted in FIGS. 5a and 5 b when arranged according to FIG. 6.
  • a complete addition or subtraction operation involves eight distinct time intervals designated T1, T2, T4, T8, A1, A2, A4 and A8.
  • T1, T2, T4, T8 For purposes of illustration, it .is assumed that the mode of operation involves the addition of two Words or digits, Word A and Word B, and particularly that the addition of digits in FIGS.
  • FIG. 5a and 5b involves the tens ordinal position of the A word and the B word.
  • the timing charts of FIGS. 5a and Stb assume that the units ordinal position of the two words involved has just been completed. The last portion at' A8 time for the units operation is shown at the beginning of the sequence in FIG. 5a.
  • signicant bits for the A word and B word, as well as corrective 6 signals and corrective 10 signals are all made available on the UP line.
  • the wave form line in FIG. 5a corresponds to the impulses on line 24, FIG. 4.
  • the UP levels are inverted prior to application to the accumulator on line 431, FIG. 4.
  • a Circle C carry representation is shown in connection with the T1 wave form, FIG. 5a. Testing of the Carry position of the accumulator for writing hack to memory occurs where indicated in FIG. 5 b by the Circle W symbols.
  • trigger P1 stores a carry indication. All other triggers are reset.
  • a shift pulse (SP) applied by line 23, FIG. 4 transfers the P1 carry representation to the Carry Trigger.
  • SP shift pulse
  • the l bit of the 5 of the A word is read from memory.
  • the bit is applied by line 31, FIG. 4, to the Carry trigger, resetting it and setting the P1 trigger to a state of 1.
  • the 1 fbit in the P1 trigger actually represents a count of 2 in the accumulator, that is, the carry that was stored plus the 1 bit of the A word.
  • the circle B indicates the reading of the 1 bit of the 3 of the to the P8 trigger. Therefore, the Carry trigger now stores a 2 bit representation and the P8 trigger now stores a 1 bit represnetation [for a total count of 3.
  • the bits of the two factors that is the A word and the B word involved are read in serially by bit and corrective factors are also read in at appropriate times with correction of the sum in the accumulator being dependent upon whether or not a carry is stored in the accumulator. Therefore, at the beginning of T2 time, the 2 bit of the corrective 6 factor is applied on line 31, FIG. 4, to the Carry trigger. This resets the Carry trigger 'and sets trigger P1.
  • the accumulator now has a count of 5 represented by a 4 bit in the P1 trigger and a 1 bit in the P8 trigger.
  • the A word has nov significant bit during T2 time and therefore the status of the accumulator remains unchanged.
  • the B word has a 2 bit from the factor 3 ⁇ and this is supplied to the Carry trigger by line 31, FIG. 4.
  • the status of the accumulator is now as shown in the tabulation above with the total count being equal to 7.
  • a shift pulse late in the T2 interval shifts P1 to Carry, Carry to P8, and P8 to P4.
  • the bits in the accumulator are shifted in order to prepare the accumulator for the next subsequent cycle by positioning the appropriate weighted bit in the Carry trigger in readiness for any corresponding weighted bit that may arrive on lines 31, FIG. 4. Therefore, the bits supplied throughout T1 time up until the Ashift pulse have a weighted significance of 1.
  • the bits supplied during the time interval T2 up until the time of the shift pulse have a weighted significance of 2.
  • T4 time and T8 time correspond to T4 time and T8 time.
  • the 4 bit of the corrective 6 and the 4 bit of the A word factor 5 are supplied by line 31 to the accumulator.
  • the B word has no significant bit during interval T4 and the total count in the accumulator at the end of T4 time is 15.
  • the shift pulse shifts the bits in the accumulators so that the appropriate weighted 8 bit is now in the Carry trigger in preparation for T8 time.
  • T8 time no significant bits are entered in the accumulator but the shift pulse is applied near the end of the time interval.
  • the tabulation for T8 time shows that the accumulator now stores a sum that represents the total of the carry from the units operation, the 5 in the A Word, the 3 in the B word, plus the corrective 6, for a total of 15.
  • the bit representations at the end of T8 time correspond respectively to the designations Agiven to the P triggers. That is, the 1 bit is stored in P1, the two bit is stored in P2 and so on.
  • an extra shift pulse supplied by And circuit 22, FIG. 4. moves the accumulated bits toward the Carry trigger so that the Carry trigger now contains the 1 bit of the total. This is sampled from line 50 and by Way of And circuit 51, FIG. 4, to write l bit into memory 1FIG. 1.
  • Another shift pulse occurs late in the A1 time interval with the accumulator bit configuration as indicated in the tabulation above.
  • the Carry trigger stores the 2 bit of the sum in the accumulator.
  • the Carry trigger is sample as indicated by the Circle W symbol on the carry line, FIG. 5b. Since the carry trigger was reset to 0 no data bit will be supplied to memory.
  • a shift pulse occurs and shifts the l bit representation from P8 t0 P4.
  • P4 stores the fact that there is no carry with a 0 representation.
  • the shift at the end of A2 time shifts the no carry indication from P4 to P2 by leaving P2 in the 0 status.
  • the accumulator at the present time stores a count of 1.
  • the 8 bit of the corrective l0 factor is added to the accumulator by an appropriate pulse on line 31 to the Carry trigger.
  • the P1 set gate is inhibited at this time by a signal on line 53 so that the 8 bit of the corrective l0 does not produce an inter-bit or inter-digit carry.
  • the tabulation indicates that the Carry trigger now has .a 1 with a significant weight of 8, that trigger P1 stores a 0 indicating no carry and that trigger P2 stores a l bit which has a l weighted significance.
  • the total count presently stored in the accumulator is 9 which is the correct sum.
  • the Carry tri-gger is sampled and since it is in the 1 state, an 8 bit is supplied to memory.
  • the accumulator circuits are now in readiness for processing the hundreds digits of the A word and the B word as they stream from memory with appropriate correction determined by Carry, as required.
  • Subtraction is comparable to the operation of ⁇ addition with the exception that provision is made for gating And circuit 48, FIG. 4, to complement the B ⁇ word representing the subtrahend and that the And circuit 37 is gated during the handling of the units digit of the factors to compensate for the elusive l encountered during subtraction. Also, the corrective 6 And circuit 34 is inhibited.
  • the resetting of the triggers, the provision of data impulses to the Carry trigger, the shifting of the accumulator, the addition of a corrective 10, and the sampling of the accumulator condition from the Carry trigger position by way of And circuit 51 occurs in a manner that is comparable with the operation previously discussed in connection with adding of an A word and B word.
  • circuits may be provided to add the corrective Six at A2 and A4 times, instead of during T2 and T4 times, by sensing a sum that is greater than 9.
  • the corrective l0 is not required for addition, but is still needed for subtraction.
  • Parallel outputs from the accumul-ator are available. For instance, near the end of A8 time, but prior to the reset and shift pulse the l, 2, 4, and 8 bits of a sum are available from the P2, P4, P8 and CY stages of the accumulator, respectively.
  • the A8 time ⁇ signals may be used to control a printer or other device. By temporarily inhibiting the advance of the clock by techniques well known in the art, the interval during vvhich the data is available may be extended as long as desired.
  • An accumulator circuit for performing arithmetic operations on a bit-by-bit basis with respect to two numerical digits during successive cyclic intervals of oepration, eac'h of said digits having a corresponding plurality of significant weighted bit positions arranged in comparable ordinal order, comprising:
  • clock circuit providing timing pulses durng each digital accumulating interval that define weighted bit intervals corresponding to the ordinal orders of said digits, each said bit interval including a counting sub-interval and a shifting sub-intervals;
  • counting circuit means interconnecting selected ones of said triggers for counting operation, including interbit carries occurring during each of said bit intervals;
  • shift circuit means interconnecting said triggers for closed loop operation as a shift register, said shift circuit means being operative in response to applied shift pulses to step each weighted ordinal bit representation previously processed arit'hmetically as stored in said triggers to said particular trigger just prior to the bit interval in which arithmetic consideration of said bit representation is required;
  • arithmetic control circuit means connected to and operable under control of said clock circuit means to successively supply data bit pulses representative of additional arithmetic factors and corrective factors as they are to be processed solely to said data input circuit during said counting sub-intervals, and to further supply shift pulses to said shift circuit means during said shifting sub-intervals to shift data bits stored in said triggers.
  • said digits are binary coded decimal digits with weighted bit positions designated 1-2-4-8, and wherein the successive bit representations are supplied alternately from each of said digits to said data input circuit.
  • mode control means for establishing an addition or subtraction mode of operation in said circuit, and wherein said arithmetic control means is operative during an addition operation to supply said digits to said data inputs in the bit sequence provided, and operative further during a subtraction mode of operation to complement the bit representations of one of said digits before supplying the same to said data input, and wherein said arithmetic control means includes additional circuits for supplying an elusive one bit representation during a subtraction mode of operation.
  • data output circuit means connected to said particular trigger for supplying data bit representations following arithmetic operations.
  • reset circuit means responsive to said clock circuit and connected to said triggers for resetting each of said trigger positions to a predetermined bit representing state selectively as required.
  • An accumulator circuit for performing arithmetic operations with respect to two ⁇ binary coded decimal numerical digits during successive cyclic intervals of operation, each of said digits having a corresponding plurality of significant weighted bit positions designated 1-2-48 arranged in comparable ordinal order, comprising:
  • an auxiliary trigger for storing inter-digit carry representations
  • a clock circuit said clock circuit providing timing pulses during each digital accumulating interval that define weighted -bit intervals corresponding to the ordinal orders of said digits, the timing pulses for each digit ordinal operation respectively designated T1-T2-T4-T8 and A1-A2-A4-A8, and each said bit interval including a counting sub-interval and a shifting sub-interval;
  • counting circuit means interconnecting selected ones of said triggers for counting operation, including inter-bit carries occurring during each of said bit intervals;
  • shift circuit means interconnecting said triggers for closed loop operation as a shift register, said shift circuit means being operative in response to applied shift pulses to step each weighted ordinal bit representation stored in said triggers to said particular trigger just prior to the bit interval in which arithmetic consideration of said bit representation is required;
  • said arithmetic control means supplies an extra shift pulse during said A1 time interval to position the accumulator bit representations in predetermined trigger positions -for proper timed provision to said data output circuit means.
  • data output circuit means responsive to said clock circuit and connected to said particular trigger and operative following correction to supply output signals representing data bits from said accumulator to an external storage means, and wherein said external storage means supplies data bit representations to said data input circuit means, and wherein said arithmetic control means supplies all other corrective factor -bit representations, shift pulses, reset pulses, and other gating required for arithmetic operation of said accumulator.
  • An accumulator circuit for performing arithmetic operations with respect to two binary coded decimal numerical digits during successive cyclic intervals of operation, each of said digits having a corresponding plurality of significant weighted bit positions designated 1-2-48 arranged in comparable ordinal order, comprising:
  • an auxiliary trigger for storing inter-digit carry representations
  • a clock circuit said clock circuit providing timing pulses during each digital accumulating interval that define weighted bit intervals corresponding t-o the ordinal orders of said digits, each said bit interval including a counting sub-interval and a shifting subinterval;
  • counting circuit means interconnecting said auxiliary trigger with trigger positions representing the 1 bit and 2 bit in said digits for counting operation, including inter-bit carries occurring during each of said bit intervals;
  • shift circuit means interconnecting said triggers for closed loop operation as a shift register, said shift circuit means being operative in response to applied shift pulses to step each weighted ordinal bit representation stored in said triggers to said particular trigger just prior to the ⁇ bit interval in which arithmetic consideration of said bit representation is required;
  • clock circuit providing timing pulses during each digital accumulating interval that define Weighted bit intervals correspon-ding to the ordinal orders of said digits, each said bit interval including a counting sub-interval and a shifting subinterval;
  • counting circuit means interconnecting said Carry-1 2 triggers for counting operation, including inter-bit carries yoccurring during each of said bit intervals;
  • shift circuit means interconnecting said triggers in and arithmetic control circuit means connected to and operable under control of said clock circuit means to supply data pulses to said data in-put circuit during said counting sub-intervals, and shift pulses to said shift circuit means during said shifting sub-intervals.

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US517563A 1965-12-30 1965-12-30 Accumulator for performing arithmetic operations Expired - Lifetime US3426185A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508037A (en) * 1967-01-30 1970-04-21 Sperry Rand Corp Decimal add/subtract circuitry
US3521043A (en) * 1967-09-15 1970-07-21 Ibm Ripple-free binary coded decimal accumulator forming correct result during single memory accessing cycle
US4314348A (en) * 1979-06-05 1982-02-02 Recognition Equipment Incorporated Signal processing with random address data array and charge injection output
US5002070A (en) * 1983-09-06 1991-03-26 Standard Textile Company, Inc. Launderable cloth-like product for surgical use and method of making the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2907526A (en) * 1956-11-02 1959-10-06 Ibm Electronic accumulator
US2997233A (en) * 1954-06-28 1961-08-22 Burroughs Corp Combined shift register and counter circuit
US3207888A (en) * 1961-11-24 1965-09-21 Ibm Electronic circuit for complementing binary coded decimal numbers
US3310664A (en) * 1964-02-24 1967-03-21 Honeywell Inc Selective signaling apparatus for information handling device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2997233A (en) * 1954-06-28 1961-08-22 Burroughs Corp Combined shift register and counter circuit
US2907526A (en) * 1956-11-02 1959-10-06 Ibm Electronic accumulator
US3207888A (en) * 1961-11-24 1965-09-21 Ibm Electronic circuit for complementing binary coded decimal numbers
US3310664A (en) * 1964-02-24 1967-03-21 Honeywell Inc Selective signaling apparatus for information handling device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508037A (en) * 1967-01-30 1970-04-21 Sperry Rand Corp Decimal add/subtract circuitry
US3521043A (en) * 1967-09-15 1970-07-21 Ibm Ripple-free binary coded decimal accumulator forming correct result during single memory accessing cycle
US4314348A (en) * 1979-06-05 1982-02-02 Recognition Equipment Incorporated Signal processing with random address data array and charge injection output
US5002070A (en) * 1983-09-06 1991-03-26 Standard Textile Company, Inc. Launderable cloth-like product for surgical use and method of making the same

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GB1117517A (en) 1968-06-19
FR1506084A (fr) 1967-12-15

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