US3596186A - Device for counting impulses - Google Patents

Device for counting impulses Download PDF

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Publication number
US3596186A
US3596186A US777052A US3596186DA US3596186A US 3596186 A US3596186 A US 3596186A US 777052 A US777052 A US 777052A US 3596186D A US3596186D A US 3596186DA US 3596186 A US3596186 A US 3596186A
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Prior art keywords
circuit
output
dephasing
inputs
circuit means
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US777052A
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English (en)
Inventor
Jean Claude Berney
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BERNARD GOLAY SA
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Golay Bernard Sa
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers

Definitions

  • This disclosure concerns a device for counting [51] Int. Cl impulses which has a generator of reference signals emitted Field 01 328/39 1 with a given period of repetition, at least one dephasing device 55, 5 3 1 226, 232, delivering a periodic signal with a period equal to the 295; 324/83 D reference period and whose phase is modified progressively by the im ulses to be counted which are a lied thereto and a [56] References cued compafison signal for the phase of the ref fence signal and the UNlTED STATES PATENTS phase delivered by the dephaser, the difference in phase being 2,653,248 9/ 1953 Perlow et al 328/39 X proportional to the number of impulses counted.
  • the present invention has for its object a device for counting impulses which eliminates the above mentioned disadvantages.
  • the device according to the invention is characterized by the fact that it comprises a generator of reference signals emitted with a given period of repetition, at least one dephaser'delivering a periodic signal with a period equal to the period of reference and whose phase is modified progressively by the impulses to be counted which are applied thereto, and a circuit for comparing the phase of the reference signal and the phase delivered by the dephaser, the difference in phase being proportional to the number of impulses counted.
  • the accompanying drawing represents by way of example one embodiment of the invention.
  • FIG. 1 shows a schematic block diagram of a counting device.
  • FIG. 2 is a diagram showing the operation of the device.
  • the counting device shown comprises an impulse generator G giving a reference signal of a period T and four frequency dividers D1, D2, D3 and D4 having dividing factors of TI, r2, T3, and 1'4. These dividers are fed by impulses of periods (Tl'rl (Th2), (Th3) and (Tl-r4), respectively in order that they maydeliver their output impulses having a period T.
  • the dividers are used as dephasers to obtain this dephasing, it suffices that it be possible to vary momentarily their dividing rate by plus or minus 1 by the application of an additional impulse.
  • additional impulses are constituted for the divider D1 by impulses to be counted applied to input 1 and for the following dividers by an impulse triggered by the previous divider.
  • the impulses delivered by the reference generator G and the dividers D1 are applied to a first and gate 1 whose output signal is applied to a bistable circuit B whose output signal is applied on the one hand to divider D2 and on the other hand to a second gate 2 to which is also applied the output of the divider D2.
  • the signal delivered by gate 2 is applied on the one hand to divider D3 and on the other hand to a third gate 3 whose output signal is itself applied to divider D4 and a fourth gate 4.
  • Generator G and divider D1 deliver impulses represented in FIG. 2, impulses which are generally dephased. These signals are therefore not simultaneously applied to gate 1 which remains closed.
  • bistable circuit B flipping of bistable circuit B from zero to I. It should be mentioned in effect that it is not the continuous state I of the bistable which is applied to gate 2, which would have no sense, but an impulse obtained by a monostable circuit or an intermediate derivative circuit The counting obtained is independent of period T In effect, if the condition of coincidences on gate 1 is expressed algebraically:
  • Dividers D1 to D4 can be constituted by binary circuits or impulse accumulators.
  • dephasers of known type to which there would be applied on the one hand a reference signal and on the other hand the impulses to be counted to modify by any known means the dephasing introduced by the dephaser.
  • a device for counting impulses comprising generator means having an output for producing reference signals having a first repetitive period; first dephasing circuit means having input means for receiving input pulses to be counted and a second repetitive signal, and having output means for producing a second periodic signal at the same rate as said first repetitive period and for progressively modifying the phase of said second periodic signal in response to reception of said pulses to be counted; and comparison circuit means having two inputs connected respectively to said generator output and said output means of said dephasing circuit means and having an output for producing a comparison pulse when signals are received simultaneously at said two inputs to said comparison circuit means, whereby the phase difference at said two inputs to said comparison circuit means is proportional to the number of said pulses to be counted which are received by said dephasing circuit means.
  • said dephasing circuit means comprises a frequency divider, and in which said second repetitive signal has a frequency equal to a submultiple of said reference period, said submultiple corresponding to the dividing rate of said frequency divider.
  • a device wherein said compauson circuit means comprises a first AND circuit.
  • a device comprising of a second said dephasing circuit means and a second said AND circuit, said second AND circuit having two inputs and an output, and said second dephasing circuit means having input means for receiving a third repetitive signal and being coupled to said output of said first AND circuit, and said second AND circuit having one of its said inputs coupled to said output means of said second dephasing circuit means, and the other of its said inputs coupled to said output of said first AND circuit.
  • a device further comprising a bistable flip-flop circuit having two inputs and one output, means coupling said pulses to be counted to one of said flip-flop inputs, the other said flip-flop input being connected to said output of saidfrrst AND circuit, and said flip-flop output being

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
US777052A 1967-11-28 1968-11-19 Device for counting impulses Expired - Lifetime US3596186A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1671067A CH486171A (fr) 1967-11-28 1967-11-28 Dispositif de comptage d'impulsions

Publications (1)

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US3596186A true US3596186A (en) 1971-07-27

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US777052A Expired - Lifetime US3596186A (en) 1967-11-28 1968-11-19 Device for counting impulses

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US (1) US3596186A (fr)
CH (1) CH486171A (fr)
DE (1) DE1808901A1 (fr)
FR (1) FR1593019A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4521898A (en) * 1982-12-28 1985-06-04 Motorola, Inc. Ripple counter circuit having reduced propagation delay

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4521898A (en) * 1982-12-28 1985-06-04 Motorola, Inc. Ripple counter circuit having reduced propagation delay

Also Published As

Publication number Publication date
CH486171A (fr) 1970-02-15
DE1808901A1 (de) 1969-06-12
FR1593019A (fr) 1970-05-25

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