US3609747A - Solid-state display circuit with inherent memory - Google Patents

Solid-state display circuit with inherent memory Download PDF

Info

Publication number
US3609747A
US3609747A US781534A US3609747DA US3609747A US 3609747 A US3609747 A US 3609747A US 781534 A US781534 A US 781534A US 3609747D A US3609747D A US 3609747DA US 3609747 A US3609747 A US 3609747A
Authority
US
United States
Prior art keywords
display
light
switch
diode
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US781534A
Other languages
English (en)
Inventor
Dinh-Tuan Ngo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Inc
Original Assignee
Bell Telephone Laboratories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bell Telephone Laboratories Inc filed Critical Bell Telephone Laboratories Inc
Application granted granted Critical
Publication of US3609747A publication Critical patent/US3609747A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/088—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements using a non-linear two-terminal element

Definitions

  • the bilateral switch and storage ele- UNITED STATES PATENTS ment function as inherent memory for the light-emitting 3,041,490 6/1962 Rajchman et al. 315/169 X diode, operating in conjunction with an AC bias voltage to 3,3 37,683 8/1967 Sliker 315/169 X maintain the diode lighted upon application ofa write pulse.
  • This invention relates to display systems and, more particularly, to display systems upon which images are generated by the selective energization of independent display cells or elements.
  • Display systems are typically used for generating patterns of information, or images, in a two-dimensional raster for information display media, computer input/output terminals, telemetered data, instrumentation, high-speed printing, and the like.
  • the principal types of display systems currently available include matrix arrangements of light bulbs and various forms of cathode-ray tube presentations, both of which suffer from well-known disadvantages related to size, cost, ruggedness and power requirements.
  • the need for a display system which would overcome these disadvantages has been apparent for some time and considerable effort has been expended toward achieving such a display system.
  • the solution was thought initially to lie in phosphor-type electroluminescent panels which, however, present problems related to rather high voltage requirements and to the need for an audiofrequency poser supply for operation.
  • Solid-state semiconductor displays eliminate the need for high operating voltages and are compatible with semiconductor switching circuitry, but they suffer from certain limitations in that they require external memory storage and associated circuitry to regenerate the display image. This substantially increases the cost and complexity of such solid-state display systems.
  • a display circuit comprising a coordinate array of display cells, each cell including the serially connected combination of a light-emitting electroluminescent diode, a charge storage element, and a bilateral switch.
  • the bilateral switch and charge storage element provide the inherent memory for the display cell, operating in conjunction with an alternating current bias voltage, to maintain the cell diode "lighted upon application of a write pulse.
  • the alternating current bias voltage is continually applied across each display cell of the array.
  • a particular cell is turned ON, i.e., is lighted, by a write pulse applied to the particular cell row and column conductors, the write pulse being sufficient to switch the cell bilateral switch to a conducting state.
  • the resulting current flow charges the cell storage element and energizes the electroluminescent diode for light emission.
  • the stored charge in combination with the bias voltage, causes periodic operation of the bilateral switch to permit sufi'lcient current flow to maintain the electroluminescent diode lighted.
  • the display cell is turned OFF by an erase pulse applied to the cell row and column conductors to operate the bilateral switch to a conducting state at a time when the bias voltage is near zero, thereby removing the charge from the storage element and preventing the recharging thereof.
  • a display circuit in accordance with my invention, is compact, rugged, and reliable and is inexpensive to manufacture, being susceptible to integrated circuit manufacturing techniques. Further, it has low operating power requirements, simple addressing circuit requirements, and may be operated directly by high-speed digital signals of the amplitude generated by integrated circuits, thereby eliminating the need for interface or buffer circuitry.
  • FIG. 1 is a diagram of an illustrative embodiment of a solidstate display circuit with inherent memory in accordance with the principles of my invention
  • FIG. 2 A -2C are time charts useful in describing the opera tion of the illustrative embodiment of FIG. I;
  • FIG. 3 depicts an alternative illustrative embodiment of a display circuit with inherent memory in accordance with the principles of my invention.
  • FIG. 4 depicts a typical voltage-current characteristicfor an illustrative bilateral switch employed in the embodiments of FIGS. 1 and 3.
  • FIG. 1 of the drawing an illustrative embodiment of the invention comprising an n times m display matrix 50 is shown for generating images by the selective energization of individual ones of display cells 100.
  • matrix 50 may comprise a conventional 5 X7 array for generating characters of the ASCII alphanumeric code.
  • display cells 100 may be employed individually or in combination in any form of array desired for particular display system applications.
  • Each display cell I00 includes the serially connected combination of a light-emitting electroluminescent diode I16, a charge storage element 113, and a bilateral breakdown switch 112 extending between a particular row and column conductor of matrix 50.
  • a diode 114 is connected in parallel with electroluminescent diode 116 and is poled opposite thereto.
  • Electroluminescent diodes 116 may, for example, be red lightemitting gallium-aresnide-phosphide diodes, green lightemitting gallium-phosphide diodes, or any other of the known types of light-emitting diodes.
  • Charge storage element "3 may comprise a capacitor as shown illustratively in FIG. I, and bilateral switch 112 may comprise, for example, a silicon PNPN breakdown diode, an Ovonic threshold switch, or the like, having the typical voltage-current characteristic shown in FIG. 4.
  • switch 112 breaks down to a low impedance conducting state.
  • Switch 112 remains in the low impedance conducting state until the voltage across the switch falls below the sustaining voltage level vsp or V at which point switch 112 returns to its quiescent high impedance non conducting state.
  • the breakdown voltage may be on the order of :8 volts and the sustaining voltage level on the order of 1-0.5 volts.
  • Alternating current bias voltage provided by source 20 which may be either sinusoidal or pulsed, is extended by control circuit across each display cell via row conductors R1 through Rm and column conductors C1 through Cn.
  • bias voltage extended by source 20 across each cell 100 is of a magnitude les than the breakdown voltage level for switch 112 but advantageously is greater than the sustaining voltage level therefor.
  • the bias voltage provided by source 20 may be on the order of 5 or 6 volts 0 to peak with a frequency on the order of 10 kHz., for example.
  • Addressing of a selected display cell 100 is effected by application of coincident signals to the particular row and column conductors connected to the display cell under control of control circuit 80.
  • the voltage thus extended across the selected display cell by the coincident row and column signals, in conjunction with the bias voltage applied to the row and column conductors, is sufficient to effect breakdown of switch 112 at the selected cell.
  • the volt age extended across the other display cells connected to the addressed row conductor and to the addressed column conductor is insufficient to effect breakdown of the bilateral switches at these other cells.
  • the addressing signals are applied to the row and column conductors of matrix 50 through respective row drivers 40 and column drivers 30, illustratively shown in FIG. 1 as pulse transformers.
  • source is connected to each column conductor C 1 through Cn via the secondary winding 302 of a respective column driver and to each row conductor R1 through Rm via the secondary winding 402 of a respective row driver 40.
  • Column conductors C1 through Cn are addressed selectively by signals from write-erase circuitry 81 on leads X 1 through Xn, respectively connected to the primary windings 301 of respective column drivers 30.
  • row conductors R1 through Rm are addressed selectively by signals from write-erase circuitry 82 on leads Y1 through Ym, respectively connected to primary windings 401 of respective row drivers 40.
  • the write pulse is extended over row conductor R1 and column conductor C1 to the selected display cell via coincident signals applied on leads Y1 and X1 from write-erase circuitry 82 and 81, which signals are reflected through the corresponding row and column drivers.
  • the write pulse is applied to the selected display cell under control of control circuit 80 near a peak of the bias voltage, as shown at time t,,,, by way of example, in FIG. 2A.
  • the write pulse is shown in FIG. 2A as applied to the right side of the peak of the bias voltage to minimize loading of the write pulse circuitry, which is particularly important in the case of integrated write pulse circuitry.
  • the write pulse can be applied at the peak or to the left of the peak of the bias voltage, as will be apparent from the description below other cells of matrix 50 which are ON will be operating during this interval to break down the respective switches thereat. Any such ON cells connected to row conductor R1 or column conductor C1, therefore, will tend to provide low impedance shunt paths for the write pulse during the interval to the left of the bias voltage peak.
  • the other cells of matrix 50 will present a high impedance state to the write pulse, and thus will minimize loading of the write pulse circuitry.
  • the write pulse applied to row conductor R1 and column conductor Cl causes momentary breakdown of switch 1 12 at the selected display cell, permitting current flow therethrough to charge storage element 1 l3 and to energize electroluminescent diode 116.
  • the resulting current flow through the display cell during breakdown of switch 1 12 is in the form of a current pulse, shown as pulse 201 in FIG. 2C, which may illustratively be on the order of ma. magnitude with a duration on the order of several hundred nanoseconds.
  • the current flow through the display cell charges storage element 113, as depicted in FIG. 28, to a level V, determined principally by the net voltage across switch 112 during breakdown.
  • V the charge on storage element 113 adds to the bias voltage, as shown in FIG. 2A.
  • the combined voltage exceeds the breakdown voltage V 83 of switch 112, momentarily switching switch 112 to a low impedance conducting state.
  • the resulting negative current pulse 202 through diode 114 discharges storage element 113 and charges element 1 13 in a reverse direction, as indicated in FIG. 28.
  • the reverse charge on storage element 113 adds to the bias voltage, as shown in FIG. 2A, reaching a level sufficient to break down switch 112 again at time t,.
  • the positive current pulse 203 resulting therefrom through electroluminescent diode 116 reverses the charge on element 113 and lights diode 116.
  • the charge stored on element 113 in combination with the bias voltage, causes periodic breakdown of switch 112 to permit sufficient current flow to maintain electroluminescent diode 116 lighted.
  • electroluminescent diode 116 occurs only during the positive current pulses, such as current pulses 201 and 203 in FIG. 2C.
  • diode 116 is advantageously energized for light emission only briefly during each cycle of bias voltage from source 20; however, diode 116 appears to an observer to emit light continuously at a steady level during the period the display cell is ON.
  • diode 114 may also be a light-emitting electroluminescent diode if desired for a particular application, diode 114 then being energized by the negative current pulses such as current pulses 202 and 204 in FIG. 2C.
  • Additional ones of display cells in matrix 50 are turned ON in a similar manner by application of a write pulse to the particular row and column conductors to which the additional cells are connected.
  • a selected display cell is turned OFF by applying an erase pulse to the row and column conductors to which the selected cell is connected such that the erase pulse removes or erases the charge stored at the selected cell.
  • This is efi'ected advantageously by applying an erase pulse to the particular row and column conductors of sufficient magnitude to break down switch 112 at a point when the instantaneous magnitude of the bias voltage applied to the row and column conductors is at or near zero. During the resulting momentary breakdown of switch 112, therefore, no significant charge is stored on element 113. Accordingly, when switch 112 returns to its high impedance state the net voltage across the display cell is approximately equal to the bias voltage and is thus insufficient to cause subsequent break down of switch 1 12.
  • Row conductor R1 and column conductor C1 are addressed via coincident signals applied on leads Y1 and X1 in the form of an erase pulse at a time when the instantaneous value of the bias voltage is near zero, as shown at time 1,, by way of example, in FIG. 2A.
  • the erase pulse is assumed to be sufficient in magnitude to cause momentary breakdown of switch 1 12 at the selected display cell.
  • the resulting current flow depicted in FIG. 2C by current pulse 210, discharges charge storage element 113, as shown in FIG. 2B, and energizes electroluminescent diode 116.
  • the instantaneous value of bias voltage across the cell at time t e is approximately zero, no significant charge builds up on storage element 113 during the momentary breakdown of switch 112.
  • diode 116 is deenergized and remains so until another write pulse is applied to the particular display cell.
  • FIG. 3 An alternative display cell embodiment is shown in FIG. 3 comprising the serially connected combination of bilateral switch 312, electroluminescent diode 316, and charge storage diode 315 poled opposite to electroluminescent diode 316.
  • the operation of the display cell embodiment of FIG. 3 is substantially the same as that described above for the embodiment of FIG. 1, except that charge storage is provided by back-to-back diodes 315 and 316 rather than by a capacitor.
  • the display cell is turned ON by the application of a write pulse across the cell, advantageously near a peak of the bias voltage, and the cell is turned OFF by application of an erase pulse when the bias voltage is at or near zero.
  • diode 316 is energized and diode 315 is charged.
  • diode 315 is discharged and diode 316 is charged in the reverse direction.
  • charge storage diode 315 also may be an electroluminescent diode poled opposite to diode 316, diode 315 thereby providing a charge storage function for one polarity current and a light emission function for the other polarity current, while diode 316 emits light for the one polarity current and provides a charge storage function for the other polarity current.
  • the use of a pair of back-to-back electroluminescent diodes for diodes 315 and 316 in FIG. 3 further advantageously facilitates fabrication of the display cell since the two diodes in each cell can then be manufactured as a single unit, without the need for subsequent electrical interconnection or for affixing electrical leads to the diode light emission surfaces.
  • the write pulses and the erase pulses may be applied consecutively to the display cells one cell at a time, as described above; or they may be applied to a plurality of cells concurrently, such as to a row or a column of cells, as may be desired for high-speed display applications.
  • a narrow write or erase pulse illustratively on the order of nanoseconds in duration, is applied across a display cell in accordance with my invention, very little current is drawn from the pulsing circuitry due to the slight delay inherent in the bilateral switch switching from a high impedance state to a low impedance state.
  • the narrow write or erase pulse sees a high impedance and the cell storage element is charged by the bias voltage, after termination of the pulse, while the bilateral switch is momentarily in a low impedance state. Accordingly, a plurality of display cells advantageously can be addressed concurrently with substantially little loading of the write or erase pulse circuitry.
  • a two-terminal display cell comprising the serially connected combination of a bilateral breakdown switch, a lightemitting semiconductor device and charge storage means.
  • a display circuit comprising an array of display cells individually including the serially connected combination of light-emitting semiconductor device means and bilateral switch means, said light-emitting means including a pair of serially connected light-emitting diodes poled opposite to one another.
  • a display circuit comprising an array of display cells individually including the serially connected combination of light-emitting semiconductor device means, bilateral switch means and charge storage means connected in circuit with said switch means.
  • a display circuit comprising an array of display cells individually including the serially connected combination of light-emitting semiconductor device means and bilateral switch means, said switch means being normally nonconducting and being operable to a conducting state; means for selectively addressing individual ones of said display cells to initially operate said switch means thereat; and bias means connected to each of said display cells and operative upon the initial operation of individual ones of said switch means for thereafter periodically operating said individual switch means.
  • bias means comprises an alternating signal source connected to each of said display cells and of a magnitude insufficient to initially operate said switch means at said cells.
  • a display circuit in accordance with claim 9 wherein said display cells are arranged in a coordinate array and said addressing means comprises respective pulse transformers having secondary windings connected to the individual rows and columns of said coordinate array, each said transformer having a primary winding connected to a respective address signal input lead and wherein said bias means comprises an alternating signal source connected to the secondary windings of each of said pulse transformers.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Semiconductor Memories (AREA)
  • Electronic Switches (AREA)
US781534A 1968-12-05 1968-12-05 Solid-state display circuit with inherent memory Expired - Lifetime US3609747A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US78153468A 1968-12-05 1968-12-05

Publications (1)

Publication Number Publication Date
US3609747A true US3609747A (en) 1971-09-28

Family

ID=25123048

Family Applications (1)

Application Number Title Priority Date Filing Date
US781534A Expired - Lifetime US3609747A (en) 1968-12-05 1968-12-05 Solid-state display circuit with inherent memory

Country Status (10)

Country Link
US (1) US3609747A (de)
JP (1) JPS4831719B1 (de)
BE (1) BE742453A (de)
CH (1) CH506853A (de)
DE (1) DE1960251B2 (de)
ES (1) ES374519A1 (de)
FR (1) FR2025427A1 (de)
GB (1) GB1282055A (de)
NL (1) NL6918238A (de)
SE (1) SE351937B (de)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3696393A (en) * 1971-05-10 1972-10-03 Hughes Aircraft Co Analog display using light emitting diodes
US3733435A (en) * 1971-02-26 1973-05-15 Zenith Radio Corp Integral memory image display or information storage system
US3743773A (en) * 1972-03-31 1973-07-03 Zenith Radio Corp Image display panel
US3765011A (en) * 1971-06-10 1973-10-09 Zenith Radio Corp Flat panel image display
US3774196A (en) * 1969-05-16 1973-11-20 Energy Conversion Devices Inc Electroluminescent circuit or the like
US3872464A (en) * 1972-11-01 1975-03-18 Oki Electric Ind Co Ltd Cold cathode discharge type display apparatus with integral memory
US4028692A (en) * 1975-09-15 1977-06-07 Bell Telephone Laboratories, Incorporated Liquid crystal display device
US4092637A (en) * 1975-09-30 1978-05-30 International Business Machines Corporation Liquid electrolyte type electrochromic display device
US4115832A (en) * 1975-12-16 1978-09-19 Sharp Kabushiki Kaisha Igniter utilizing a negative resistance light emitting diode
US4129861A (en) * 1976-01-27 1978-12-12 American Cyanamid Company Multiplex addressing of electrochromic displays
US4134132A (en) * 1976-06-29 1979-01-09 Villamos Berendezes Es Keszulek Muvek Circuit arrangement for display boards having luminous elements arranged in a matrix
US4295137A (en) * 1980-01-07 1981-10-13 Gte Laboratories Incorporated Electroluminescent display driver system for thin-film electroluminescent devices requiring electric field reversal
FR2584520A1 (fr) * 1985-07-03 1987-01-09 Sayag Electronic Dispositif d'affichage comportant un reseau matriciel de sources lumineuses
US4914045A (en) * 1985-12-19 1990-04-03 Teccor Electronics, Inc. Method of fabricating packaged TRIAC and trigger switch

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4642620A (en) * 1982-09-27 1987-02-10 Citizen Watch Company Limited Matrix display device
AT384916B (de) * 1986-01-17 1988-01-25 Siemens Ag Oesterreich Zusatzschaltung fuer in serie liegende infrarotdioden

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3774196A (en) * 1969-05-16 1973-11-20 Energy Conversion Devices Inc Electroluminescent circuit or the like
US3733435A (en) * 1971-02-26 1973-05-15 Zenith Radio Corp Integral memory image display or information storage system
US3696393A (en) * 1971-05-10 1972-10-03 Hughes Aircraft Co Analog display using light emitting diodes
US3765011A (en) * 1971-06-10 1973-10-09 Zenith Radio Corp Flat panel image display
US3743773A (en) * 1972-03-31 1973-07-03 Zenith Radio Corp Image display panel
US3872464A (en) * 1972-11-01 1975-03-18 Oki Electric Ind Co Ltd Cold cathode discharge type display apparatus with integral memory
US4028692A (en) * 1975-09-15 1977-06-07 Bell Telephone Laboratories, Incorporated Liquid crystal display device
US4092637A (en) * 1975-09-30 1978-05-30 International Business Machines Corporation Liquid electrolyte type electrochromic display device
US4115832A (en) * 1975-12-16 1978-09-19 Sharp Kabushiki Kaisha Igniter utilizing a negative resistance light emitting diode
US4129861A (en) * 1976-01-27 1978-12-12 American Cyanamid Company Multiplex addressing of electrochromic displays
US4134132A (en) * 1976-06-29 1979-01-09 Villamos Berendezes Es Keszulek Muvek Circuit arrangement for display boards having luminous elements arranged in a matrix
US4295137A (en) * 1980-01-07 1981-10-13 Gte Laboratories Incorporated Electroluminescent display driver system for thin-film electroluminescent devices requiring electric field reversal
FR2584520A1 (fr) * 1985-07-03 1987-01-09 Sayag Electronic Dispositif d'affichage comportant un reseau matriciel de sources lumineuses
EP0210898A1 (de) * 1985-07-03 1987-02-04 Sayagvision Anzeigegerät mit einer Matrix von lumineszierenden Lichtquellen
US4914045A (en) * 1985-12-19 1990-04-03 Teccor Electronics, Inc. Method of fabricating packaged TRIAC and trigger switch

Also Published As

Publication number Publication date
NL6918238A (de) 1970-06-09
DE1960251C3 (de) 1973-11-15
CH506853A (de) 1971-04-30
BE742453A (de) 1970-05-14
GB1282055A (en) 1972-07-19
DE1960251A1 (de) 1970-06-18
ES374519A1 (es) 1972-04-01
SE351937B (de) 1972-12-11
FR2025427A1 (de) 1970-09-11
JPS4831719B1 (de) 1973-10-01
DE1960251B2 (de) 1973-04-26

Similar Documents

Publication Publication Date Title
US3651509A (en) Light pen for display having inherent memory
US3972040A (en) Display systems
US3765011A (en) Flat panel image display
US3686661A (en) Glow discharge matrix display with improved addressing means
US3654606A (en) Alternating voltage excitation of liquid crystal display matrix
US4554539A (en) Driver circuit for an electroluminescent matrix-addressed display
US3037189A (en) Visual display system
US4349816A (en) Drive circuit for matrix displays
US3689912A (en) Gaseous display driver circuits
US3947842A (en) Electro-optic matrix-type display panel incorporating optoelectronic addressing switches
US3715607A (en) Electroluminescent circuit or the like
GB1274639A (en) Display apparatus incorporating a gas discharge panel
EP0004700A2 (de) Gasentladungsanzeigevorrichtung
GB1282055A (en) Display cells
US3671938A (en) Gaseous display device
EP0128238A2 (de) Anzeigeeinrichtung
US3400388A (en) Binary to alpha-numeric translator
US3811124A (en) Solid state gas panel display circuits with non-inductive solid state isolation between low level logic and high level drive signal functions
US3280341A (en) Electroluminescent switching circuit
US4200822A (en) MOS Circuit for generating a square wave form
US3522473A (en) Electroluminescent display utilizing voltage breakdown diodes
US3754230A (en) Plasma display system
US3628088A (en) High-voltage interface address circuit and method for gas discharge panel
US3651493A (en) Solid state traveling display circuit
US3739371A (en) Cross addressed bistable display panel with selectable bilevel sustaining bias circuit