US3632883A - Telecommunication exchange with time division multiplex - Google Patents

Telecommunication exchange with time division multiplex Download PDF

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US3632883A
US3632883A US838463A US3632883DA US3632883A US 3632883 A US3632883 A US 3632883A US 838463 A US838463 A US 838463A US 3632883D A US3632883D A US 3632883DA US 3632883 A US3632883 A US 3632883A
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channel
cycle
cyclic
storage
channel time
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Einar Andreas Aagaard
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US Philips Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Definitions

  • the information from all channels is sequentially stored in a cyclic storage register in fixed relationships with cyclic code numbers generated by a local clock generator.
  • a clock instant detennined by the address of an output channel the address of an input channel is serially introduced into a second cyclic register.
  • the output of the second cyclic register is decoded and used to switch the output of the first cyclic register corresponding to the selected input channel to an output line.
  • EINAR A AAGAARD PATENTEB JAN 4 I972 SHEET 6 0F 6 INVENTOR.
  • the invention relates to a telecommunication exchange with time-division multiplex, which comprises incoming timedivision multiplex trunks to which incoming trunk circuits are connected and outgoing time-division multiplex trunks to which outgoing trunk circuits are connected, in which each time-division multiplex trunk is provided with time-division channels to each of which is allotted a particular channel time interval within a cycle of channel time intervals.
  • Such a telecommunication exchange is known from British Pat. No. 932,612.
  • the incoming trunk circuits are provided with random access line stores adapted to receive an information in a first-channel time interval and to transmit it in a second channel time interval.
  • Random access stores are comparatively complicated devices. It is therefore a first object of the invention to provide a telecommunication exchange in which the incoming trunk circuits are provided with simpler stores.
  • This first object of the invention includes particularly the use of line stores adapted to be manufactured in mass production, for example, glass delay lines of the type employed in color television receivers for the PAL and SECAM color television systems.
  • the telecommunication exchange in accordance with the objects of the invention is characterized in that, the incoming trunk circuits are each provided with a cyclid storage device having a storage cycle time equal to one channel time interval and a storage capacity which is at least sufficient for storing the information received in one cycle of channel time intervals through the incoming time-division multiplex trunk, each channel time interval being divided into a number of equal subtime intervals, said number being at least equal to the number of time-division channels of a time-division multiplex trunk each incoming trunk circuit being provided with means for storing the information received through the incoming time-division channels in the cyclic storage device in subtime intervals individually allotted to the time-division channels, means being provided which the establishment of a time-division connection between an incoming channel of an incoming time-division multiplex trunk and an outgoing channel of an outgoing time-division trunk, transmit the information appearing in the subtime interval allotted to the incoming channel of a given channel time interval in
  • FIG. 1 is a simplified block diagram of a time-division multiplex telecommunication exchange in accordance with the invention
  • FIGS. 2a to 2k and 2m to 2! show the symbols used in the further Figures and FIGS. 3, 4 and 5 show a more detailed block diagram of the part of the telecommunication exchange surrounded in FIG. 1 by a broken line.
  • FIG. 1 shows a simplified block diagram of a telecommunication exchange based on the time'division principle.
  • the reference numerals 100 and 101 designate incoming timedivision multiplex trunks through each of which the signals from n telecommunication channels are received and the reference numerals 102 and 103 designate outgoing time-division multiplex trunks through each of which the signals of n telecommunication channels are transmitted.
  • the incoming time-division multiplex trunks to 101 are connected through the receiving devices 104 to 105, to the line stores 106 and 107, which are controlled by the line store control device 108.
  • the line stores 106 to 107 are connected to the inputs of a space-division switching stage 109, the outputs of which are connected to the word selectors 110 to 111.
  • the word selectors are connected to the transmitting devices 112 to 113 of the outgoing time-division multiplex trunks 102 to 103.
  • the telecommunication exchange is furthermore provided with a central control device 114 for controlling the switching stage 109 and the word selectors 110 to 111, said central control device being provided with the control stores 115 to 116, individually allotted to the outgoing time-division multiplex trunks.
  • the receiving device 104 and the line store 106 are together termed the incoming trunk circuit and the same applies to and 107; the word selector and the transmitting device 112 are together termed the outgoing trunk circuit and the same applies to 111 and 113.
  • Number of channels of a trunk n 32, corresponding to a channel time interval of 3.9 asec.
  • the local clock of the telecommunication exchange (not shown in the Figures) having a cycle time T supplies during each cycle in order of succession the channel time interval signals to t which divide the clock cycle into n equal channel time intervals.
  • the transmitting devices 112 to 113 transmit code words through the outgoing trunks during the channel interval signals t, to 1,, of the local clock, which thus determines the time scale of the outgoing trunks.
  • the number of an outgoing channel is then equal to the number of the channel time interval within the clock cycle in which the code words are transmitted through the channel.
  • the code words are transmitted in serial form through the outgoing trunks, in which serial form the bits of the word are transmitted consecutively in corresponding bit intervals.
  • the binary digit 1 is characterized by the presence of a pulse in the corresponding bit interval and the binary digit 0 by the absence of a pulse in the corresponding bit interval.
  • each telecommunication exchange is controlled by clock signals supplied by the relevant local clock, the time scale of the incoming trunks 100 to 101 will deviate from the time scale of the local clock of the exchange on which these trunks terminate.
  • Devices for adapting the time scale of an incoming trunk to the time scale of the local clock are known and do not form the subject matter of the present invention. These devices form parts of the receiving devices 104 to 105. In these devices the incoming code words are transferred to the channel time intervals of the local clock and the fluctuations between the time scales of the incoming trunk and of the local clock are neutralized.
  • the operation of these time-matching devices is not essential and it may be supposed that the receiving member 104 to 105 transmit the incoming code words through the lines 117 to 118 to the line stores during the channel time interval signals 1 to t of the local clock, i.e. the code words of the incoming channel 1 during the channel time interval signal t, the code words of the incoming channel 2 during the channel time interval signal t, etc. or with a given shift between the channel numbers and the numbers of the channel time interval signals.
  • the incoming code words are usually transferred from the serial form to the parallel form and it is therefore supposed that'the line stores 106 to 107 receive the code words from the receiving devices 104 to 105 in the parallel form.
  • the transmitting devices 112 to 113 are known devices whose operation is not essential for a good understanding of the invention.
  • Known transmitting members receive the code words to be transmitted in the parallel form. It is supposed that the transmitting devices are adapted to receive a code word in the parallel form during each channel time interval signal I, to
  • the channel time interval signals t, to t,.,, supplied by the local clock in each clock cycle in order of succession, are enumerated in each cycle from the origin thereof by 1 to n.
  • the numbers of the channel time intervals are indicated by binary code words At to A1,, of v bits, which represent the decimal digits I to n.
  • the channel time interval signals 1, to t, have the form of pulse code groups appearing in parallel form and representing the binary code words Ar, to At so that each channel time interval is identified by the code word generated in the relevant channel time interval by the local clock.
  • the clock supplies consecutively the subtime interval signals W, to w,,, which divide each channel time interval into n equal subtime intervals.
  • the subtime interval signals w to w also have the form of pulse code groups, representing the binary code words Aw, to Aw,,, which represent the numbers I to n of the subtime intervals.
  • the clock supplies consecutively the sub-subtime interval signals e to e, which divide each subtime interval w into j equal sub-subtime intervals.
  • the sub-subtime interval signals 2 to e have each the form of a pulse appearing at a separate conductor.
  • the clock supplies consecutively two shift signals a and b, each having the form of a pulse appearing at a separate conductor.
  • the clock supplies consecutively the subtime interval signals s to n, which divide each channel time interval into i equal subtime intervals s.
  • the subtime interval signals .9 to s have each the form of a pulse appearing at a separate conductor.
  • the clock supplies consecutively two shift pulses c and d at separate conductors.
  • the subtime interval signals s, to s, and the shift pulses c and d are only employed in the central control member 114 for controlling the internal information processing.
  • the clock supplies channel pulses t of short duration, which coincide with the shift pulses a in the sub-subtime intervals e, of the subtime intervals Aw
  • Code words representing channel information are transmitted in the serial form through the switching stage 109 in the subtime intervals Aw with the j bits in the j consecutive subsubtime intervals e, to e,.
  • Code words representing control information are stored in the control stores in the channel time intervals At in the serial form with the i bits in the i consecutive subtime intervals s to 8;.
  • FIG. 2 shows the symbols of the logic circuits used in the drawing. These symbols will be explained hereinafter. It will be assumed that the binary digit 1 is represented by a high voltage and the binary digit by a low voltage and that a clock pulse brings the voltage of a conductor to the level of the binary digit l.
  • FIG. 2a shows the symbol of an AND-gate.
  • the voltage of the output 203 is only high when the voltages of the two inputs 201 and 202 are simultaneously high.
  • FIG. 2b shows the symbol of a group of parallel conductors.
  • the number or the symbol indicates the number of conductors, in this case eight.
  • FIG. 2c shows a group of equivalent devices, only the first (204) and the last (205) of which are shown.
  • FIG. 2d shows a group of AND-gates and FIG. 2e the relevant symbol.
  • the symbol for the corresponding group of conductors is replaced by the symbol for a single conductor.
  • FIG. 2f shows the symbol for a not element.
  • the voltage at the input 206 is high, the voltage at the output 207 is low and conversely.
  • FIG. 23 shows the symbol of a bistable trigger.
  • a voltage variation from a low to a high value at the input 208 moves the flip-flop into the O-state or leaves it in this state.
  • a voltage variation from a low value to a high value at the input 209 moves the flip-flop into the l-state, when previously a voltage variation from a low to a high value has taken place at the input 208, or the flip-flop is left in the l-state.
  • Voltage variations from a high to a low value do not affect the state of the flip-flop. In the O-state the voltage at the output 210 is high and that at the output 211 is low and in the l-state the voltage at the output 210 is low and that at the output 211 is high.
  • FIG. 2h shows a register stage and FIG. 2i the relevant symbol.
  • the register stage comprises a flip-flop 212, two AND- gates 213 and 214 and a not element 215.
  • the voltage at the input 216 is low, the voltage at the output of the not element 215 is high and the voltage at one of the inputs of the AND-gate 213 is then high, so that when the voltage at the clock input 217 becomes high, the flip-flop is changed over to the O-state.
  • the voltage at the input 216 is high, the voltage at one of the inputs of the AND-gate 214 is high so that when the voltage at the clock input 217 becomes high, the flip-flop is changed over to the l-state.
  • FIG. 2j shows a register comprising the register stages 219, 220, 221, whose individual clock inputs are connected to a common clock input 222.
  • FIG. 2k shows the symbol used for the register.
  • FIG. 2m shows the symbol for a decoder.
  • FIG. 2n shows the symbol for a comparator for comparing code words supplied through the groups of parallel conductors 226 and 227.
  • the voltage at the output 228 increases to the level of the binary digit l.
  • the voltage at the output 228 remains high as long as there is a correspondence, so that the duration of the pulse at the output 228 is equal to the duration of the code word having the shortest time duration.
  • FIG. 20 shows a parallel-series converter and FIG. 2p the relevant symbol.
  • the parallel-series converter comprises a register 233 and the AND-gates 230 to 231.
  • a code word of j bits supplied through the group of conductors 229 in the parallel form in a channel time interval is stored during the channel pulse t of the next channel time interval in the register 233, whose outputs are connected to the AND-gates 230 to 231.
  • To these AND-gates are supplied the sub-subtime interval signals e to e,, which render the AND-gates conducting in order of succession, so that the bits of the code word are applied in order of succession in the sub-subtime intervals e to e, to the output 232.
  • FIG. 2q shows a series-parallel converter and FIG. 2r the relevant symbol.
  • the series-parallel converter serves for converting into the parallel form code words that are applied each in a subtime interval Aw in the serial form, with the bits in the consecutive sub-subtime intervals e; to e,, to the input 239.
  • the series-parallel converter comprises the register stages 234 to 233, a register 236 and the AND-gates 237 to 230, connected to the clock inputs of the register stages.
  • To the AND- gates are applied the sub-subtime interval signals e, to e, which render the AND-gates conducting in order of succession for the shift signal b applied to the input 241.
  • the latter signal is applied in each channel time interval At only once during one subtime interval Aw.
  • the bit applied to the input 239 in the sub-subtime interval e of the subtime interval Aw is stored during the shift pulse b in the register stage 234 and the bit applied in the sub-subtime interval 2 is stored during the shift pulse b in the next register stage and so on for the other bits.
  • FIG. 2s shows a shift register and FIG. 2t the relevant symbol.
  • the shift register comprises the register stages 242, 243, 244, and 245, which are connected into a chain.
  • the clock inputs of the odd register stages 242 and 244 are connected to the common clock input 246 to which the shift pulse b is applied.
  • the clock inputs of the even register stages 243 and 245 are connected to the common clock input 247, to which the shift signal a is applied.
  • the bit applied in a sub-subtime interval e to the input 240 is stored during the shift pulse b in the register stage 242 and then shifted during the next shift pulse a to the register stage 243 and presented to the output thereof during the next sub-subtime interval so that two register stages together provide a delay of one sub-subtime interval.
  • the number of bits that can be stored simultaneously in the shift register is equal to half the number of register stages.
  • the number of register stages is always an even number, but may otherwise be chosen arbitrarily in dependence upon the wanted storage capacity.
  • FIGS. 3, 4 and 5 show in more detail the part of the telecommunication exchange surrounded by the broken line in FIG. 1.
  • the binary code words of j bits of n communication channels are supplied in the channel time intervals At to At,.
  • Each code word is stored during the channel pulse t' of the next channel time interval in the register of the parallel-series converter 300 and applied to the sub-subtime intervals 2, to e, in serial form to the AND- gate 301.
  • This transmission of a code word to the AND-gate 301 is performed in each subtime interval Aw, to Aw so that each received code word is transmitted n times in the serial form to the AND-gate 301.
  • the AND-gate 301 is connected to the input of a shift register 302 of the type shown in FIG. 2s, having 2j.n. register stages controlled by the shift signals a and b.
  • the delay time of the shift register is j.n sub-subtime intervals e or one channel time interval.
  • the output of shift re gister 302 is coupled through the AND-gate 303 with the input.
  • the AND-gate 303 is normally open and the AND-gate 301 is normally closed under the control of the line store control device 100.
  • a bit appearing at the output of the shift re gister during a shift pulse a is normally transmitted through the gate 303 to the input and during the next shift pulse b it is stored in the first stage of the shift register.
  • a bit and in fact the whole stored contents of the shift register comprising n code words continues circulating through the shift register as long as the gate 303 is open. Since the delay time of the shift register is equal to one channel time interval, it will be obvious that all n stored code words are applied once in each channel time interval to the output.
  • the line store control device 100 comprises a comparator 304, which compares the code words At and Aw applied by the local clock of the telecommunication exchange to the groups of parallel conductors 306 and 307.
  • the feedback shift register included in an incoming trunk circuit is typical for a cyclic store having a delay time of one channel time interval and a storing capacity of j.n bits. It will be obvious that in general any type of cyclic store having the same delay time and the same storage capacity may be employed in the incoming main line members. This applies particularly to cyclic stores adapted to be manufactured by mass production, for example, glass delay lines, employed in given types of color television receivers.
  • the outputs of the shift registers of the line stores 106 to 107 are connected to the horizontal lines 400 to 401 of the switching stage 109 (FIG. 4).
  • the vertical lines 402 to 403 of the switching stage 109 are connected to the word selectors 110 to 111.
  • the cross points of the horizontal lines 400 to 401 with the vertical line 402 are provided with the cross-point gates 404 to 405.
  • An input of each AND-gate is connected to the corresponding horizontal line and a second input of each AND-gate is connected to a corresponding output of a decoder, which is allotted to the corresponding vertical line.
  • the outputs of the ANDgates are connected to the corresponding vertical line.
  • the number of a time multiplex trunk is represented by a code word of 14 bits, which is indicated] for an incoming trunk by A0! and for an outgoing trunk by AMI.
  • the number of a channel is represented by a code word of v bits, which is indicated for an incoming channel by Auk and for an outgoing channel by Auk.
  • the binary code words Aak and Auk represent the decimal digits 1 to n in the same manner as the code words At and Aw that are generated by the local clock.
  • the number Aak of an incoming channel is given by the number of the channel time interval used by the incoming channel on the group of conductors 117 or 110.
  • the number Auk of an outgoing channel is given by the number of the channel time interval used by the outgoing channel on the outgoing trunk.
  • the central control device 114 does not use the code words Aak and Auk but it uses the code words A'ak and A'uk derived therefrom.
  • the code word A A' In order to establish a connection between an incoming channel and an outgoing channel (FIG. the code word A A', is stored in the register of the parallel-series converter 500 of the central control device 114 and the code word Aul-A'uk is stored in the register 501, after which during one cycle of the local clock through the conductor 502 a l-signal is applied to the AND-gate 503, which is thus opened.
  • the code word AuI stored in the register 501 is applied to a decoder 507, which decodes the same and supplies a l-signal at an output corresponding to said code word.
  • a comparator 504 compares the code word Auk stored in the register 501 with the code words A, supplied by the local clock.
  • the comparator 504 supplies a l-signal during the relevant channel time interval AFA'uk, said signal being applied through the AND-gate 503 to the AND-gates 505 to 506, which are connected to the outputs of the decoder 507, said AND-gates being thus opened.
  • the l-signal appearing at one of the outputs of the decoder 507 is applied through one of the opened AND-gates 505 to 506 to one of the control stores 115 to 1 16. It will be assumed that the code word Aul indicates the control store 115 allotted to the outgoing trunk 102.
  • the 1- signal of the decoder 507 is then applied through the AND- gate 505 to the control store 115.
  • the parallel-series converter 500 transmits in the serial form the code word Aal-Aak in the subtime intervals s to s, to the inputs of the control stores 115, 116, which transmission is repeated in each channel time interval At of the relevant cycle.
  • the control store 115 comprises an AND-gate 508, connected to the input and normally closed under the control of the O-signal of the AN D-gate 505.
  • the output of the AND-gate 508 is connected to the input of a shift register 509 having 2.i.n register stages, controlled by the shift signals c and d.
  • the delay time is i.n subtime intervals s or one clock cycle and the storage capacity is n code words of i bits.
  • the output of the shift register 509 is coupled through the AND-gate 510 with the input.
  • the AND-gate 510 is normally open under the control of the l-signal of the not element 511.
  • the stored contents of the shift register 509 normally circulate via the opened AND-gate 510 through the shift register and in every clock cycle all n stored code words are once applied to the output.
  • the decoder 507 applies a l-signal through the AND-gate 505 to the AND-gate 508, which is thus opened and via the not element 511 a O-signal is applied to the AND-gate 510, which is thus closed.
  • the bit applied to the AND-gate 508 by the parallel-series converter 500 in the subtime interval s is stored in the first stage of the shift register 509 during the shift pulse d and during the next shift pulse c it is stored in the second register stage and so on for the further bits of the code word Aal-Aak.
  • the gate 503 is closed so that in the next clock cycles the gates 505 to 506 are closed.
  • the contents of the register of the parallel-series converter 500 and of the register 501 may then be varied for establishing a connection between two other channels.
  • the code word AaI-Aak appearing at output of the shift register 509 in the channel time interval AFA'u/t is transferred by the series-parallel converter 512 to the parallel form and stored in the register thereof during the channel pulse t of the next channel time interval.
  • the code word AaI stored in the register of the series-parallel converter 512 is applied through the group of parallel conductors 513 to the decoder 406 of the switching stage 109, which decoder subsequently supplies a l-signal at the output, which corresponds to the code word Aal.
  • the code word Aal represents the address of the incoming multiplex trunk so that the decoding member 406 supplies a l-signal to the AND-gate 404, which is thus opened.
  • the word selector 110 comprises a parallel-series converter 408 of the type shown in FIGS. 2q and Zr, the input of which is connected to the vertical line 402 of the switching stage 109.
  • the parallel-series converter 408 comprises, in the manner as shown in FIG. 2r, the group of AND-gates 408-l, the common input of which is connected to the output of the AND-gate 407.
  • the AND-gate 407 which is normally closed under the control of the 0-signal of the conductor 516, receives the shift signal b. Since the gate 407 is normally closed, the group of AND-gates 408-1 are also normally closed.
  • the l-signal of the comparator 514 opens the gate 407 of the word selector 110, so that the shift signal b is applied in the subtime interval fl ti i'itlip thesha tn lnm inter fl i r! t the mmon input of the group of AND-gates 408-1 of the seriesparallel converter 408.
  • This channel time interval corresponds to the incoming channel Aak so that the transmission of a code word of the incoming channel Aak of the incoming trunk 100 to the outgoing channel Auk of the outgoing trunk 102 is carried out.
  • the central processor When a connection has to be established from a given channel Aak of a given incoming trunk Aal to any channel of a given outgoing trunk the central processor will first search for a free channel on the relevant outgoing trunk.
  • the chan nel time interval Auk-2 On the horizontal line of the switching stage 109, where the incoming trunk circuit is connected, the chan nel time interval Auk-2 may be occupied already for a further connection.
  • Time-division telecommunication exchanges having a great number of trunks can be realized in a simple manner by dividing the trunks in groups and by using, instead of the switching stage 109, a multistage space division switching network and by connecting each group of incoming trunks to inputs of a separate matrix switch of the first stage and each group of outgoing trunks to outputs of a separate matrix switch of the last stage.
  • the property of nonblocking of the telecommunication exchange can be maintained by using a nonblocking switching network.
  • An arrangement for a telecommunication exchange comprising a first line member connected to a first multiplex line through which are transmitted in the incoming direction of transmission channel information originating from a plurality of first transmission channels each comprising a plurality of words in timedivision multiplex in first-channel time intervals individually associated with said first transmission channels of ill a repetitive first cycle of channel time intervals and comprising a second line member connected to a second multiplex line through which are transmitted in the outgoing direction words of channel information intended for a plurality of second transmission channels in time-division multiplex in second-channel time intervals individually associated with said second transmission channels of a.
  • the cycle time of the second cycle of channel time intervals being equal to that of said first cycle, and furthermore comprising an internal transmission path within the arrangement connecting said first line member to said second line member and including at least one switching gate, the first line member comprising a cyclic storage member having a storage cycle time equal to the duration ofa cycle of second-channel time intervals, and comprising for every word of said first transmission channels a storage location in which a word of channel information can be stored,.
  • said arrangement comprising furthermore first control means for storing words of channel information from every transmission channel in a storage location of the cyclic storage member individually associated with said first transmission channel, said first line member comprising means for supplying, during each storage cycle, the words of channel information stored in the cyclic storage member to said internal transmission path, characterized in that, the arrangement comprises second control means for controlling said switching gate into the conductive state during and for the duration of a selected second-channel time interval of every said second cycle of channel time intervals, third control means to supply the address of a selected storage location of said cyclic storage member to said second line member at a time associated with said selected second-channel time interval, and the second line member comprises selection means for selecting, during the said selected second-channel time interval the word of the channel information originating from: the storage location identified by said address.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Error Detection And Correction (AREA)
  • Time-Division Multiplex Systems (AREA)
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NL6809491.A NL157481B (nl) 1968-07-05 1968-07-05 Inrichting voor een telecommunicatiecentrale voor het tot stand brengen van verbindingen tussen n inkomende tijdmultiplexlijnen en n uitgaande tijdmultiplexlijnen.

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US4959830A (en) * 1988-07-12 1990-09-25 Telefonaktiebolaget L M. Ericsson Method and apparatus for through-connecting a wideband connection in a digital time switch
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US20010053160A1 (en) * 2000-04-11 2001-12-20 Velio Communications, Inc. San Jose, Ca Multistage digital cross connect with synchronized configuration switching
US20030058848A1 (en) * 2000-04-11 2003-03-27 Velio Communications, Inc. Scheduling clos networks
US20030214944A1 (en) * 2002-05-17 2003-11-20 Velio Communications, Inc. Scheduling connections in a multi-stage switch to retain non-blocking properties of constituent switching elements
US20040114586A1 (en) * 2002-12-11 2004-06-17 Velio Communications, Inc. Grooming switch hardware scheduler
US6870838B2 (en) 2000-04-11 2005-03-22 Lsi Logic Corporation Multistage digital cross connect with integral frame timing
US7260092B2 (en) 2000-04-11 2007-08-21 Lsi Corporation Time slot interchanger
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US3872256A (en) * 1972-05-26 1975-03-18 Siemens Ag PCM time-division multiplex switching procedure
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US3927267A (en) * 1973-04-06 1975-12-16 Paul Voyer Time division switching system of the {37 time-space-time{38 {0 type
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US4312063A (en) * 1979-09-27 1982-01-19 Communications Satellite Corporation TDM Data reorganization apparatus
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EP0453129A1 (de) * 1990-04-10 1991-10-23 AT&T Corp. Zeitmultiplex-Vermittlungssystem mit hoher Geschwindigkeit
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US7260092B2 (en) 2000-04-11 2007-08-21 Lsi Corporation Time slot interchanger
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US7301941B2 (en) 2000-04-11 2007-11-27 Lsi Corporation Multistage digital cross connect with synchronized configuration switching
US20030214944A1 (en) * 2002-05-17 2003-11-20 Velio Communications, Inc. Scheduling connections in a multi-stage switch to retain non-blocking properties of constituent switching elements
US7346049B2 (en) 2002-05-17 2008-03-18 Brian Patrick Towles Scheduling connections in a multi-stage switch to retain non-blocking properties of constituent switching elements
US20040114586A1 (en) * 2002-12-11 2004-06-17 Velio Communications, Inc. Grooming switch hardware scheduler
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US11295069B2 (en) * 2016-04-22 2022-04-05 Sony Group Corporation Speech to text enhanced media editing

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BE735695A (de) 1970-01-05
DK125260B (da) 1973-01-22
CH508329A (de) 1971-05-31
FR2012392A1 (de) 1970-03-20
GB1276156A (en) 1972-06-01
DE1930426B2 (de) 1977-04-28
NL157481B (nl) 1978-07-17
SE360961B (de) 1973-10-08
NL6809491A (de) 1970-01-07
AT303834B (de) 1972-12-11
DE1930426A1 (de) 1970-01-15

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