US3673579A - Drawingboard ii, a graphical input-output device for a computer - Google Patents

Drawingboard ii, a graphical input-output device for a computer Download PDF

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US3673579A
US3673579A US70626A US3673579DA US3673579A US 3673579 A US3673579 A US 3673579A US 70626 A US70626 A US 70626A US 3673579D A US3673579D A US 3673579DA US 3673579 A US3673579 A US 3673579A
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computer
input
output
output device
register
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Robert Michael Graven
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
    • G06F3/0354—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor with detection of two-dimensional [2D] relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
    • G06F3/03542—Light pens for emitting or receiving light
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/048—Interaction techniques based on graphical user interfaces [GUI]
    • G06F3/0484—Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
    • G06F3/04845—Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range for image manipulation, e.g. dragging, rotation, expansion or change of colour

Definitions

  • Tipton ABSTRACT A two-dimensional matrix of semi-conductors is arranged in ordered array as a flat, light emitting and light sensing device activated both electrically and by radiant energy from a penlight to achieve a graphical input and output display by the active or inactive condition of the light emitter with circuitry for control of flow of graphical data into and out of the device for use in conjunction with a digital computer.
  • Cathode ray tube displays have been used with a light pen having a photo sensitive cell directed at the display on the surface of the tube to pick out or place a point in the display.
  • Still other devices use photosensitive materials for receiving information but do not display information back from the same plane of the device after it is entered or processed by the computenFew of the graphical input-output devices of the prior art provide circuitry which can control the flow of graphical information into and out of the device which is separate and apart from the computer.
  • the device of the present invention is a flat graphical inputoutput device for a computer using light sensors to receive information, with light emitters juxtaposed adjacent corresponding sensors to display information.
  • a penlight i.e., a pen or light emitting writing instrument, is held inthe hand of the operator and is used to activate the light sensors.
  • a processor unit is used to control the flow of information into and out of the device for operation with a computer.
  • the processor unit circuitry provides for activating, deactivating and determining the status of each emitter in accordance with either a coded or uncoded signal.
  • the processor unit also is arranged to activate rows, columns and blocks of emitters as desired.
  • FIG. 1 is an isometric view of the graphical input-output device of the present invention
  • FIG. 2 is a plan and elevational view of a typical emittersensor pair
  • FIG. 3 is a logic diagram of a typical point defined by a light emitter-sensor pair
  • FIG. 3A is a more detailed circuit diagram of a typical point
  • FIG. 4 is a symbol list defining some of the symbols used in the drawings.
  • FIGS. 5A and 5B is a single line block diagram of the circuitry of the present invention showing the interconnection of the various control units used to operate the device,
  • FIG. 6 is a circuit diagram showing the connection of primary input register, operations decoder, B. AND and C AND gates, local memory, F AND and G OR gates, and memory OR gates,
  • FIG. 7 is a circuit diagram of control registers SR( 0) through SR(3) of the drawingboard processor unit
  • FIG. 8 is a circuit diagram of control registers SR( 4) through SR( 6) of drawingboard processor unit,
  • FIG. 9 is a circuit diagram of the W control gates of the drawingboard processor unit.
  • FIG. 10 is a circuit of the X-input, X-output and X-parts registers as connected to the drawingboard,
  • FIG. 11 is a circuit diagram of the Y-output register and the XY-, Z'-, and the Z-registers for transmitting the graphical information to the computer,
  • FIG. 12 is an elevational view of a typical penlight used to place infon'nation into and erase information from the graphical device of FIG. 1 along with details of circuitry for connecting it to the device,
  • FIG. 13 is a circuit diagram of the input character gates register of the drawingboard processor unit
  • FIG. 14 is a circuit diagram of an instruction logic device used to measure incremental variations in the graphical disp y.
  • FIG. 14A is a circuit diagram of a typical timing chain device used in FIG. 14,
  • FIG. 14B is a circuit diagram of a device to direct X- and Y- adders to add or subtract one binary digit from the address
  • FIG. 15 is a diagram of typical pulse wave forms of the timing device of FIGS. 14, 14A and 14B.
  • FIG. 16 is a circuit diagram of a comer of the array showing a typical point and its interface with peripheral circuitry to the board.
  • FIG. 17 is a circuit diagram showing the X-decoder in greater detail
  • FIG. 18 is a circuit diagram showing the Y-decoder in greater detail
  • FIG. 19 is a circuit diagram showing the X-encoder in greater detail
  • FIG. 20 is a circuit diagram showing the Y-encoder in greater detail.
  • the graphical input-output device of the present invention comprises, basically, a write and display board 20, i.e., input-output drawingboard 20, which is mounted on an electronic and power supply cabinet 21 having a control panel 22 on the front thereof.
  • a penlight 23 is electronically connected to board 20 by two or more conductors 86 and 86', 24 and 25 for control of the light output of the penlight as will be described below, and for control of information placed in the board.
  • Board 20 further comprises modular emitter-sensor circuit units or points 26 shown typically in FIGS. 2 and 3 arranged in an array 35 (FIG. 1) of horizontal and vertical rows and columns respectively.
  • a modular emitter-sensor pair or point 26 is shown in plan and elevation and comprises a compartment in block 27 containing local circuitry, on the top surface of which is mounted a light emitter 28 and a light sensor 29 along with other light sensors further described below.
  • Light emitters 28 may be any light emitting means such as an incandescent or neon glow lamp, however, the present device is arranged to utilize a semi-conductor device such as a light emitting diode common in the art.
  • Light sensor 29 is, as used in the present embodiment, a semi-conductor device sensitive to electromagnetic radiation.
  • a transparent surface 30 is disposed over the entire surface of array 35.
  • FIG. 3 illustrates a simplified logic diagram for a typical point i.e., emitter-sensor pair circuit 26.
  • a point 26 comprises an X-sense diode 31 connected on its anode side to X-conductor 32 and a Y-sense diode 33 connected on its anode side to Y-conductor 34.
  • the cathode sides of X- and Y- sensediodes 31 and 32 are connected in common to the output of AND gate 36 and the output of light sensor 29 through pointing circuit 50.
  • Light emitting diode 28 and one of the inputs to AND gate 36 are connected to the output of memory circuit 37.
  • the other input of AND gate 36 is connected to READ conductor 38 while the two inputs to memory circuit 37 are connected to WRITE conductor 39 and ERASE conductor 40.
  • FIG. 3A a more detailed circuit diagram of a typical point 26 is shown.
  • Table 2 is a listing of the values for resistors 172 and 173 necessary to change the state of the bi-stable circuit of FIG. 3A.
  • the sensitivity range is generally descriptive. The measured values would range from about 100 foot-candles for an intenselight to about 0.5 foot-candles for shadow light.
  • WRITE conductor 39 enters circuit 26 through transistor 160 while ERASE conductor 40 enters the circuit through transistor 161 for computer control of the WRITE-ERASE function.
  • the same function can be performed using penlight 23 by activating light sensor 162 to write or light sensor 163 to erase.
  • Memory is achieved through bi-stable transistors 164 and 165 which lock in the on or ofi' status ofthe point, i.e., whether or not a current is flowing through light emitting diode 28.
  • penlight 23 is pointed at light sensing transistor 162 and light sources 88 (FIG. 12) are energized to shine on sensor 162 causing a current to flow through the transistor, applying a voltage to one side of light emitting diode 28 causing a current to flow therethrough.
  • penlight 23 is pointed at light sensing transistor 163 and light sources 88 are energized to shine on sensor 163 reducing its resistance to a value sufficient to lower the voltage across light emitting diode-28 to limit the current therethrough sufiicient to turn diode 28 off.
  • FIG. 4 defines the symbols used in the drawings.
  • OR gate 41 of FIG. 4 is a semi-conductor device having two or more inputs and one output. A signal, i.e., a voltage pulse, on either of the inputs on the left will appear on the output (right) side of the device.
  • AND gate 42 of FIG. 4 is a semiconductor device having two inputs, both of which must be activated, i.e., have a voltage on the input conductors, for a signal to appear on the output side.
  • Dtype flip-flop 43 is a bi-stable semi-conductor device having a signal input 44 and a clock" input 45, a reset input 46 and two logical complimentary out-put conductors 47 and 48.
  • reset input 46 causes all flip-flops 43 to return to a logical zero or ofi"position.
  • Inverting amplifier 49 is a device common in the art for producing the logical compliment of a digital signal.
  • FIGS. 5A and 58 shown on two sheets, is a single line block diagram showing theinterconnection of the basic electronic switching units which serve to control the How of information into drawingboard 20 and also to and from the computer (not shown )through drawingboard 20 for the manipulation of the data contained therein.
  • the computer that is used in conjunction with the device of the present invention can be any digital computer common in the art which can receive, manipulate and transmit informationcoded in a manner to identify individual bits of information, for example, in the form of voltage pulses on various combinations of conductors or lines leading into and out of the present device.
  • FIGS. 5A and SB represent switching circuits which comprise basically combinations of ANDand ORgates and flip-flop devices with the exception of local memory 106 which may be any type of device common in the art which can temporarily store information.
  • local memory 106 which may be any type of device common in the art which can temporarily store information.
  • a magnetic core memory common in the art would be one example.
  • FIG. 5A there is illustrated the circuits associated with drawingboard 20 used to place information into the board and read information stored in the board.
  • drawingboard 20 comprises a 16 by l6 array 35 of points" 26 having sixteen X-conductors 32 (FIG. 3 and 3A) arranged parallel and equally spaced in a common plane with sixteen Y-conductors 34 arranged parallel and equally spaced normal to X-conductors 32 in said common plane.
  • a point26 is connected at the intersection of each X- and Y-conductor 32 and 34, respectively.
  • Array 35 therefore, comprises 256 "points" 26 arranged in 16 horizontal and 16 vertical rows and columns, with each point" 26 comprising the elements of the circuit of FIG. 3A.
  • FIG. 16 shows array 35 comprising read, write and erase gate registers 154, and 156, respectively, whose outputs are connected to conductors 38, 39 and 40 through read, write and erase point AND gates 157, 158, and 159, respectively.
  • an individual point" 26 may be read, written or erased by appropriate photoactivation of transistors 29, 162 or 163, respectively.
  • the input circuitry for the device of the present invention comprises, for the X-sense (x-coordinate), X-input register 56 whose output is connected to X-input side 53X, X-input parts register 57 whose output is connected to the input side of X-input register 56 and whose various inputs are connected to drawingboard processor unit 100 (FIG. 5B).
  • X-address decoder 58 The output of X-address decoder 58 is connected to the input of X-input parts register 57 while the input side of X-address decoder 58 is connected through XCD gates 115 to drawing board processor unit 100 (FIG. 5B).
  • the output side of Y-input register 60 is connected to input side 53Y of array 35 while the input side of register 60 is connected to the output side of Y-input parts register 61.
  • the output of Y-address decoder 62 is connected to the input side of Y-input parts register 61 while the inputs of both Y-address decoder 62 (through YDC gates 120) and Y-input parts register 61 are connected to drawingboard proccessor unit 100.
  • the output circuitry for the device of the present invention comprises, for the X-sense (X-coordinate), X-output register 64 whose input is connected to X-output side 54X, X-output parts register 65 whose input is connected to the output of X- output register 64.
  • X-output register 64 is also connected to the input of X-address encoder 66 whose output is connected both to multiple input OR gate XOOR 150 and XEC gates register 81 (FIG. 17).
  • the input side of Y-output register 68 is connected to Y-output side 54Y, while its output side is connected to the input side of Y- output pans register 69.
  • Y-output register 68 is connected to the input of Y-address encoder 70 whose output is connected both to multiple input OR gate YOOR 151 and YEC gates register 124 (FIG. 18).
  • Both X- and Y-output parts registers 65 and 69 are connected to drawingboard output register 73 whose output is connected to the computer (not shown).
  • FIG. 5B shows the interconnection of the various block circuits contained in the drawingboard processor unit 100.
  • drawing board processor unit 100 comprises a primary input register 101, whose outputis variously connected to operations decoder 102, C AND gates register 103, B ANDgates register 104 and instruction logic circuit 152.
  • Operations decoder 102 is variously connected to local memory 106, F AND gates register 107, address code status register SR() 108, input part status register 812(1) 109, output parts status register SR(2)110, read status status register SR(3)111, labels" status register SR(4) 112, location storagestatus register SR()113, and memory bufferstatus register SR(6) 114 and instruction logic circuit 152.
  • Drawingboard processor unit 100 further comprises, input character gates register 116, W gates register 117, 6" OR gates register 118, and memory OR gates register MOR 1 19.
  • Athrough Z are used to identify the lines or circuitsinterconnecting the various circuit units or blocks.
  • line A( 1) designates line “1 of circuit "A”
  • X(07) designateslines 0 (zero)through "7 of circuit X.
  • the arrows which are incorporated into the circuit lines represent the flow of information or data through drawingboard 20 and processor unit in accordance with the direction of the arrow.
  • drawingboard processor unit 100 To describe in detail the individual circuit units of drawingboard processor unit 100, reference is made to FIG. 6 and beginning in particular to primary input register 101.
  • Primary input register 101 comprises a plurality, sixteen in the present embodiment, of flip-flop circuit units 121 having outputs A(0) through A( 15).
  • the input signal enters register 101 in a manner such that the fust five bits," A(0) through A(4) of information are an encoded command signal; the next three bits, A(5), A(6), and A(7) are an encoded instructional signal also identified as lines [(0), I( 1) and K2), respectively; and the remaining eight bits are an encoded X-Y address signal for a particular point" 26, four bitsfor the X-address and four bits for the Y-address.
  • Operations decoder 102 comprises a set of input OR gates 122, a decoder unit common in the art which converts the on or ofFstatus of either lines A(0-4) or E(0-4) to a pulse or signal on any one of 00 to 37 (octal) outputs on 32 lines (decimal).
  • B AND gates register 104 is used to bypass coded adderess information around local memory 106 while C AND gates register 103 is used to place coded address information into local memory 106.
  • lines A(7) also identified as line I(2)
  • A'(7) of the instructional coded section of primary input register 101 are used to gate the flow of information through C and B"gates registers 103 and 104 respectively.
  • the signal on line A'(7) is the logical compliment of the signal on line A(7 Local memory 106 can be any memory unit common in the art for storing bits" of information such as a magnetic core matrix and the like common in the art.
  • Local memory OR gates register MOR 119 comprises eight OR gates which control the flow of information from memory 106, instruction logic circuit 152 and B AND gates register 104into lines X'(0-3) and Y'(0-3).
  • F AND gates register 107 comprises all AND gates 134 and G OR gates register 118 comprising all OR gates 135 are used to control the flow of information into memory buffer" status register SR(6) 1 14 (FIG. 5B).
  • FIGS. 7 and 8 there is shown the detailed circuit diagram for status registers SR(0) through SR(6) reference numerals 108 through 1 14, respectively.
  • each status register comprises a column of bi-stable flip-flop devices and a column of AND gates 126.
  • command lines 127 and 128 are connected to flip-flop devices 125.
  • Line 127 is connected in common to the clock input terminals of each flip-flop device 125 for the purpose of transferring the status of the signal input lines into the register, and the other command line 128 is connected in common to the reset input of flip-flop devices 125 to reset all flip-flop devices to a logical zero orofl" status.
  • AND gates 126 are used to gate information out of thestatus registers upon appropriate activation of lines RSW(-7) of status register SR(3) 1 11.
  • Status registers SR(0-6), reference numerals 108 through 1 14, are identified as shown in Table 3 as follows:
  • Register 116 converts the coded address of a typical point26.. on lines X'(0-3) and Y(03) to activation of lines X(0-15) and Y(015) by appropriate activation of lines XIC(O-l and YIC(0-l For example, concurrent activation of lines Y(2) and XIC( 1) will causeline X(l4) to be activated.
  • FIG. 9 illustrates a detailed circuit diagram of W gates register-117 which coi'nprises eight lower OR gates 132 and eight upper OR gates 133.
  • the lower OR gates 132 have input and output lines as tabulated in Table 4.
  • the upper OR gates 133 have input and output lines as tabulated in Table 5.
  • FIG. 10 is a logic diagram of the input andoutput register circuits for drawingboard 20.
  • the input and output register circuits in the Y- direction are identical to those in the X-direction and, therefore, are not repeated in the drawing. Discussion of the X- input and output circuitry applies as well to the Y-input and output circuitry.
  • FIG. 11 is a circuit diagram of drawing board 8 output register 73 as well as a circuit diagram of Y-output register 68 and Y-output parts register 69.
  • X-input parts gate register 57 comprises a set of sixteen X-parts ANDgates 75 and a set of six- 1 teen X-parts OR gates 76.
  • One side of the input to AND gates 75 is connected consecutively in groups of four, to lines X'(O-3).
  • the other side of the input to AND gates75 is connected in common, in groups of four, to lines XIP(0-3). It can be seen, using this arrangement, that by selective activation of lines X'(0-3) and XIP(0-3), only one line or a combination of lines X(0-'l5) can be activated. Thus, combined with the Y-direction, one point or combination of points will be activated.
  • Input register 56 comprises sixteen bi-stable flip-flop devices 77 which act to control the flow of the information on the output lines 78 of input parts register 57 into array 35.
  • Command lines *01 and *02 for the X- and Y-coordinates are used to control the flow of such information.
  • Command lines *10 and *11 are used to reset X-input register 56 and Y-input register 60,.respectively, to a logical zero of ofi'"status.
  • X-output register 64 similar to X-input register 56 comprises sixteen bi-stable flip-flop devices 79 which act to control the flow of information out of array 35.
  • Line ROR to X- and Y-output registers 64 and 68 from OR gate 145 (FIG. 12) is used to control the flow of output information.
  • Command lines *13 and *14 (FIG. 5A) are used to reset X-output register 64 and Y-output register 68, respectively, to a logical zero or off" status.
  • X-output pans gate register 65 comprises all AND gates 80. It will be noted that one side of the input to AND gates 80 is connected in common, in groups of four, to lines XOP(0-3). Thus by appropriate activation of lines XOP(03), information is gated out of X-output register 64 into drawingboard output register 73 (FIG. 1 1
  • drawingboard output register 73 comprises XY OR gates register 82, Z-OR gates register 83 and Z- output register 84 which is connected to Y-output parts gate register 69 and X-output parts gate register 65 at the input side of XY OR gate register 82.
  • Z-output register 84 comprises sixteen bi-stable flip-flop devices 85 used to transfer information from its input side to the computer (not shown).
  • Command line *06 is used to con.- trol the flow of the information to the computer while command line *15 is used to reset all the bits of output register 84 to a logical zero or ofi state.
  • the circuitry for these devices is common in the art and comprises AND gates Y DC 120, XDC 1 I5, YEC 124 and XEC 81 and inverting amplifiers such that the "on and off status combination of four input lines intoaddress decoders 58 and 62 causes activation of only one of 16 output lines of the decoder, and for encoder 66 or 70, activation on one of 16 input lines causes a particular combination of on-off states of four output lines of the encoder.
  • X-address decoder 58 connected to XDC gates register 115.
  • XDC gates register comprises four AND gates 59 whose outputs are connected to X-address decoder 58.
  • One input side of AND gates 59 is connected individually to line X(0-3) while the other side is connected in common to line XDC from status register SR(0) 108.
  • FIG. 20 shows Y-address decoder 62 connected to YDC gates register 120.
  • YDC gates register also comprises four ANDgates 63 whose outputs are connected to Y-address decoder 62.
  • ANDgates 63 One input side of ANDgates 63 is connected individually to lines Y'(0-3) while the other side is connected in common to line YDC from status register SR(0)108.
  • FIG. 17 X-address encoder 66 with output connected to multiple input OR gate XQOR and AND gates register XEC 81 comprising all AND gates 67.It

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US5073770A (en) * 1985-04-19 1991-12-17 Lowbner Hugh G Brightpen/pad II
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US5216755A (en) * 1980-12-04 1993-06-01 Quantel Limited Video image creation system which proportionally mixes previously created image pixel data with currently created data
US5289566A (en) * 1980-12-04 1994-02-22 Quantel, Ltd. Video image creation
US5302948A (en) * 1991-10-03 1994-04-12 Lau Clifford B Object pointer computer input apparatus
USRE36455E (en) * 1985-04-19 1999-12-21 Loebner; Hugh Brightpen/pad II
US20040174698A1 (en) * 2002-05-08 2004-09-09 Fuji Photo Optical Co., Ltd. Light pen and presentation system having the same
US20060176288A1 (en) * 1998-08-18 2006-08-10 Arkady Pittel Electronic pen holding
US20070154116A1 (en) * 2005-12-30 2007-07-05 Kelvin Shieh Video-based handwriting input method and apparatus

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Publication number Priority date Publication date Assignee Title
US3760373A (en) * 1971-12-20 1973-09-18 Ibm Optical data entry and display system
US3768073A (en) * 1972-01-03 1973-10-23 Searle Medidata Inc Entry confirming input terminal
US3947842A (en) * 1973-05-23 1976-03-30 Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland Electro-optic matrix-type display panel incorporating optoelectronic addressing switches
US3911423A (en) * 1974-05-08 1975-10-07 Northern Electric Co Electrical luminescent displays
US4301449A (en) * 1978-12-07 1981-11-17 Fitzgerald Engineering Company, Inc. Control panel
US5289566A (en) * 1980-12-04 1994-02-22 Quantel, Ltd. Video image creation
US5216755A (en) * 1980-12-04 1993-06-01 Quantel Limited Video image creation system which proportionally mixes previously created image pixel data with currently created data
USD289291S (en) 1984-04-06 1987-04-14 International Business Machines Corp. Interactive graphics data terminal
US4672558A (en) * 1984-09-25 1987-06-09 Aquila Technologies Group, Inc. Touch-sensitive data input device
US4949079A (en) * 1985-04-19 1990-08-14 Hugh Loebner Brightpen/pad graphic device for computer inputs and the like
US5073770A (en) * 1985-04-19 1991-12-17 Lowbner Hugh G Brightpen/pad II
US5159322A (en) * 1985-04-19 1992-10-27 Loebner Hugh G Apparatus to digitize graphic and scenic information and to determine the position of a stylus for input into a computer or the like
USRE36455E (en) * 1985-04-19 1999-12-21 Loebner; Hugh Brightpen/pad II
US4713535A (en) * 1985-09-04 1987-12-15 Rhoades Randy L Optical keyboard
DE3635687A1 (de) * 1986-10-21 1988-05-05 Messerschmitt Boelkow Blohm Bildaufnahmesensor
DE8703309U1 (de) * 1986-11-20 1987-04-23 Edding AG, 2070 Ahrensburg Bausatz für ein Planungsgerät
US4864411A (en) * 1988-06-06 1989-09-05 Ncr Corporation Electronic copy board system
WO1991018383A1 (fr) * 1990-05-23 1991-11-28 Mann Brian M Systeme de conception assistee par ordinateur utilisant une image de grande surface
WO1993003474A1 (fr) * 1991-08-02 1993-02-18 Hugh Loebner Dispositif servant a digitaliser une information graphique et scenique et a determiner la position d'un stylet
US5302948A (en) * 1991-10-03 1994-04-12 Lau Clifford B Object pointer computer input apparatus
US20060176288A1 (en) * 1998-08-18 2006-08-10 Arkady Pittel Electronic pen holding
US20060176287A1 (en) * 1998-08-18 2006-08-10 Arkady Pittel Light sources for digital pen
US20070030258A1 (en) * 1998-08-18 2007-02-08 Arkady Pittel Capturing handwriting
US7773076B2 (en) 1998-08-18 2010-08-10 CandleDragon Inc. Electronic pen holding
US20040174698A1 (en) * 2002-05-08 2004-09-09 Fuji Photo Optical Co., Ltd. Light pen and presentation system having the same
US20070154116A1 (en) * 2005-12-30 2007-07-05 Kelvin Shieh Video-based handwriting input method and apparatus
US7889928B2 (en) * 2005-12-30 2011-02-15 International Business Machines Corporation Video-based handwriting input

Also Published As

Publication number Publication date
FR2105996A5 (fr) 1972-04-28
DE2142366C3 (de) 1981-05-07
NL7109823A (fr) 1972-02-29
CA932050A (en) 1973-08-14
JPS554310B1 (fr) 1980-01-29
DE2142366B2 (de) 1980-09-11
GB1351506A (en) 1974-05-01
DE2142366A1 (de) 1972-03-02

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