US3825697A - Phase-lock-loop fm-stereo decoder including stereophonic/monophonic blend system for reducing audio distortion - Google Patents

Phase-lock-loop fm-stereo decoder including stereophonic/monophonic blend system for reducing audio distortion Download PDF

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US3825697A
US3825697A US00383243A US38324373A US3825697A US 3825697 A US3825697 A US 3825697A US 00383243 A US00383243 A US 00383243A US 38324373 A US38324373 A US 38324373A US 3825697 A US3825697 A US 3825697A
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signal
audio
full
khz
stereophonic
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T Cornell
W Smith
L Wilkinson
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Motors Liquidation Co
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General Motors Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/22—Homodyne or synchrodyne circuits
    • H03D1/2209—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders
    • H03D1/2236—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders using a phase locked loop

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  • the separation between the Land R output channels is substantially instantaneously decreased to less than full channel separation thereby to rapidly shift toward full monophonic operation for reducing the discernible audio distortion resulting from the distorted reception.
  • the separation between the L and R output channels is. relatively gradually increased to full channel separation thereby to slowly shift to full stereophonic operation for reducing the discernible audio disruption resulting from the shift to full stereophonic operation.
  • a phase-lock-loop In a known FM-stereo decoder, a phase-lock-loop generates a local 38 KHz de'modulating signal in phase synchronization with the 19 KHZ pilot signal. Further, an audio decoder demodulates the L R signal and the L R modulated 38 KHZ suppressed subcarrier signal in response to the local 38- KHz demodulating signal to provide an L audio signal on an L output channel and an R audio signal on an R output channel.
  • the phase-lock-loop includes a phase detector which provides an error voltage having an amplitude which is proportional to the phase difference betweenthe received 19 KHz pilot signal and the local 38 KHz demodulating signal.
  • the separation between the L' and R output channels of the audio decoder is substantially instantaneously defined at less than full channel separation in response to a predetermined increase in the amplitude of the phase-lock-loop error voltage due to the initiation of distorted reception, whether multipath reception or a form of overload reception.
  • This fast attack feature of the invention is desirable in order to shift from full stereophonic opera tion toward full monophonic operation'in time to re turn the discernible audio distortion resulting fromthe distorted reception.
  • the separation between the L and R output channels of the audio de coder is relatively graduallyrestored to full channel separation in response to a predetermined decrease in the amplitude of the phase-lock-loop error voltage due to the termination of distorted reception.
  • This slow retreat feature of the invention is desirable in order to KHz suppressed subcarrier signal, and a 19 KHZ pilot reduce the discernible audio disruption resulting from the return to full stereophonic operation following the excursion toward full monophonic operation.
  • acoupling network including an electronic switch is connected across the L and R output channels of the audio decoder for establishing full channel sepa- 6 ration when the electronic switch rs turned off and for establishing less than full channel separation when the electronic switch is turned on.
  • a level detector is responsive to an initial increase in the amplitude of the error voltage due to the initiation of distorted reception to substantially instantaneously turn on the electronic switch.
  • the level detector includes a timing network which is responsive to a subsequent decrease in the amplitude of the error voltage due to the termination of distorted reception to relatively gradually turn off the electronic switch.
  • the electronic switch is a field-effect transistor.
  • theminimum separation between the L and R output channels of the audio decoder during distorted reception is defined at an intermediate channel separation located between full channel separation and zero channel separation. This feature of the invention is desirable in order to reduce the discernible audio disruption resulting from the sudden shift from full stereophonic operation toward full monophonic operation.
  • the coupling network includes at least one resistive. element connected with the electronic switch for defining the intermediate channel separation in proportion to the resistance of the resistive element when the electronic switch is turned on.
  • the separation between the L and R output channels of the audio decoder. is varied during distorted reception from full channel separation to less than full channel separation in direct proportion to the frequency of the L and R audio signals such that channel separation decreases with increases in audio frequency. Since the greatest portion of the L and R audio signals is composed of lower frequency components while the major portion of the audio distortion of the L and R audio signals results from higher frequency components, this feature of the invention is desirable in order to maximize total stereophonic operation and yet minimize overall audio distortion.
  • the coupling network includes at least one reactive element connected with the electronic switch for defining the separation between the L and R output channels of the audio decoder in proportion to the reactance of the reactive element as defined in proportion to the frequency of the L and R audio signals when the electronic switch is turned on.
  • the reactive element is a capacitor.
  • FIG. 1 is a block diagram of an FM-stereo decoder including an inventive stereophonic/monophonic blend system incorporating one embodiment of a unique coupling network.
  • FIG. 2 is a graphic diagram of the operating eharacteristic of the embodiment of the coupling network illustrated in FIG. 1.
  • FIG. 3 is a schematic diagram of an embodiment of a level detector incorporated within the inventive stereophonic/monophonic blend system illustrated in FIG. 1.
  • FIGS. 4, 6, and 8 are schematic diagrams of other embodiments of the coupling network incorporated within the inventive stereophonic/monophonic blend system illustrated in FIG. 1.
  • FIGS. 5, 7, and 9 are graphic diagrams of the operating characteristics of the various embodiments of the coupling network illustrated in FIGS. 4, 6, and 8.
  • an FM-stereo radio receiver includes an FM detector 10 for developing a standard composite stereo signal including a 19 KHZ pilot signal, an L R signal and an L Rmodulated 38 KHz suppressed subcarrier signal at a junction 12.
  • An FM- stereo decoder 14 includes a phase-lock-loop 16 and an audio decoder 18. The phase-lock-loop 16 is connected to the junction 12 for developing a 38 KHZ demodulating signal or subcarrier signal at a junction 20 in phase synchronization with the 19 KHz pilot signal.
  • the audio decoder 18 is connected to the junctions l2 and 20 for demodulating the L R signal and the L R modulated 38 KHz signal in response to the 38 KHz demodulating signal to provide an L audio signal on an L output channel 22 and an R audio signal on an R outputchannel 24.
  • a pair of audio amplifiers 26 and 28 are connected to the L and R output channels 22 and 24, respectively, for amplifying and applying the .L and R audio signals to L and R stereo speakers 30 and 32, respectively.
  • the phase-lock-loop 16 includes a voltage controlled oscillator 34 for producing a 76 KHz reference signal having a phase defined in proportion to the amplitude of a differential error voltage appearing between a pair of junctions 36 and 38.
  • a first frequency divider 40 is connected to the oscillator 34 for dividing the 76 KHz reference signal by a factor of (2) to provide the 38 KHz'demodulating signal at the junction 20 in phase with the 76 KHz reference signal.
  • a second frequency divider 42 is connected to the junction 20 for dividing the 38 KHz demodulating signal by a factor of (2) to provide a 19 KHz reference signal in quadrature to the 38 KHz demodulating signal.
  • a phase detector 44 is connected to the junction 12 and to the second frequency divider 42 for developing the differential error voltage between the junctions 36 and 38 such that the amplitude of the error voltage is defined in proportion to the difference between the phase of the 19 KHz pilot signal and the phase of the 19 KHz reference signal as determined by the phase of the 38 KHz demodulating signal.
  • the FM-stereo decoder 14 may be provided by a Fairchild uA758 FM-stereo decoder which is commercially available as a monolithic integrated circuit from Fairchild Semiconductor Corporation.
  • a more detailed description of the uA758 FM-s tereo decoder may be obtained by reference to The uA75 8, A Phase Locked Loop FM Stereo Multiplex Decoder by Larry Blaser and Bill Cocke, as published in application Note 319, June, 1972, Fairchild SemiconductorCorporation.
  • a similar FM-stereo decoder is described in A Monolithic Phase-Lock-Loop Stereo Decoder, by Michael J. Gay, as published in I.E.E.E. Transactions on Broadcast and TV Receivers, November, 1971.
  • Multipath reception occurs when two identical signals emanating from the same transmitting antenna arrive at the same receiving antenna out of phase after traveling over different propagation paths. Ordinarily, one of the signals is received directly from the transmitting antenna while the other of the signals is received indirectly after reflection from an object disposed between the transmitting and receiving antennas. At the receiving antenna, the direct and reflected signals vectorily add to form a resultant signal which is phase distorted.
  • Overload distortion may take a number of forms, but in general, it may be characterized as occurring when at least two unwanted signals mix together to provide a beat signal having.
  • the ultimate phase distortion of the composite stereophonic signal is manifested by a corresponding amplitude distortion of the L and R audio signals which, in turn, produces a derivative audible distortion from the stereo speakers 30 and 32.
  • the signal-to-noise ratio of monophonic operation is inherently greater than the signal-to-noise ratio of stereophonic operation.
  • the resulting audio distortion is less discernible to a listener during monophonic operation than during stereophonic operation. Therefore, it is desirable to shift from full stereophonic operation toward full monophonic operation during distorted reception.
  • the phase of the 19 KHz pilot signal is initially shifted in response to the onset of distorted reception, the amplitude of the error voltage appearing between the junctions 36 and 38 of the phase-lock-loop 16 increases sharply.
  • the present invention provides a stereophonic/monophonic blend system 46 for reducing the separation between the L and R output channels 22 and 24 of the audio decoder 18 in response to an increase in the amplitude of the error voltage indicative of distorted reception thereby to shift from full stereophonic operation toward full monophonic operation so as to reduce the discernible audio distortion resulting from the distorted reception.
  • the stereophonic/monophonic blend system 46 includes a DC amplifier 48, a I
  • the DC amplifier 48 is responsive to the error voltage appearing between junctions 36 and 38 to provide anamplified replica of the error voltage between a pair of lines 54 and 56.
  • the DC amplifier 48 may be provided by a Westinghouse WC-l 15-P differential amplifier which is commercially available as a monolithic integrated circuit from Westinghouse Electric Corporation.
  • the FM-stereo decoder 14 is provided by a Fairchild uA 8 FM-stereo decoder
  • the DC amplifier 48 may be provided by a DC amplifier which is internal to the voltage controlled oscillator 34 of the uA758 integrated circuit.
  • the coupling stage 52 is connected across the L and R output channels 22 and 24 of the audio decoder 18.
  • the coupling stage 52 includes an electronic switch 58 provided by a field-effect transistor having gate, source and drain electrodes.
  • an impedance device 60 is connected between the source electrode of the transistor 58 and the L output channel 22 of the audio decoder 18.
  • the drain electrode of the transistor 52 is connected directly to the R output channel 24 of the audio decoder 18.
  • the field-effect transistor 52 is a bilateral device, the source and drain electrodes are interchangeable.
  • the fieldeffect transistor 58 may be replaced by any suitable electronic switch such as a junction bipolar transistor and that the impedance device 60 may or may not be present within the coupling network 52 as will become more apparent hereinafter.
  • the level detector 50 is connected between the gate electrode of the field-effect transistor 58 and the lines 54 and 56 emanating from the DC amplifier 48.
  • the level detector 50 applies a bias voltage to the gate electrode of the field-effect transistor 58 to render the transistor 58 fully conductive.
  • the level detector 50 withdraws the bias voltage from the gate electrode of the field-effect transistor 58 to render the transistor 58 fully nonconductive.
  • the separation between the L and R output channels 22 and 24 of the audio decoder 18 is defined at substantially full channel separation thereby to provide full stereophonic operation.
  • the separation between the L and R output channels 22 and 24 of the audio decoder 18 is defined at less than full channel separation thereby to provide less than full stereo phonic operation for reducing the discernible audio distortion resulting from the distorted reception.
  • the separation between the L and R output channels 22 and 24 is defined at substantially zero channel. separation when the transistor 58 is turned on.
  • FIG. 2 illustrates the operating characteristic (i.e. a graph of channel separation versus audio frequency) of the coupling stage 52 where the impedance device 60 is absent and the transistor 58 turned on.
  • the level detector 50 In order to shift from full stereophonic operation toward full monophonic operation in time to reduce discernible distortion resultingfrom distorted reception, it is necessary that the level detector 50 have a fast attack capability; that is, the level detector 50 must be responsive to an initial increase in the amplitude of the error voltage due to the initiation of distorted reception to substantially instantaneously turn on the transistor 58 to decrease the separation between the L and R output channels 22 and 24 of the audio decoder 18 thereby to rapidly shift to less than full stereophonic operation.
  • FIG. 3 illustrates an'embodiment of the level detector 50 which possesses the desired fast attack and slow retreat features, and which is suitable for fabrication within a monolithic integrated circuit.
  • the level detector 50 includes a high potential line 62 and a low potential line 64 across which a direct current supply voltage is applied.
  • the low potential line 64 is grounded.
  • the FM-stereo decoder 14 is provided by a Fairchild uA758-stereo decoder
  • the DC supply voltage may be derived from a power supply internal to the uA758 integrated circuit.
  • the level detector 50 may be fabricated upon the same semiconductor chip as the uA 8 FM-stereo decoder.
  • the level detector 50 includes a level sensor 66, a timing network 68 and a buffer stage 70.
  • the level sensor 66 includes a differential voltage switch provided by a'pair of voltage switching transistors 72 and 74 of the NPN junction type and a complementary current switch provided by a pair of current switching transistors 76 and 78 of the PNP and NPN junction type, respectively.
  • the base electrodes of the transistors 72 and 74 are connected directly to the lines 54 and 56, respectively, emanating from the DC amplifier 48.
  • the emitter electrodes of the transistors 72 and 74 are connected together at a junction 80..
  • the collector electrode of the transistor 72 is connected directly to a junction 82.
  • the collector electrode of the transistor 74 is connected directly to the high potential line 62.
  • a bias diode 84 is connected between the high -potential line 62 and the junction 82.
  • the base electrode of the transistor 76 is connected directly to the junction 82.
  • the emitter electrode of the transistor 76 is connected directly to the high potential line 62.
  • the collector electrode of the transistor 76 is connected directly to a junction 92.
  • a bias resistor 86 is: connected between the junction and a junction 88.
  • a bias diode 90 is connected between the junction 88 and the low potential line 64.
  • the base electrode of the transistor 78 is connected directly to the junction 88.
  • the emitter electrode of the transistor 78 is connected directly to the low potential line 64.
  • the collector electrode of the transistor 76 is connected directly to the junction 92.
  • the timing network 68 includes a timing capacitor 94 across which a timing voltage V, is developed.
  • the timing capacitor 94 is connected between a junction 96 and the low potential line 64.
  • a Darlington switch is provided by a pair of transistors 98 and 100 of the NPN junction type. Specifically, the base electrode of the transistor 98 is connected directly to the junction 92. The collector electrode of the transistor 98 and the collector electrode of the transistor 100 are connected together to the junction 96. The emitter electrode of the transistor 98 is connected directly to the base electrode of the transistor 100. The emitter electrode of the transistor 100 is connected directly to the low potential line 64.
  • a pair of bias resistors 102 and 104 are connected in series between the high potential line 68 and the junction 96 such that a junction 106 is defined between the resistors 102 and 104.
  • the buffer stage 70 includes a buffer switch formed by a pair of transistors 108 and 110 of the PNP and NPN junction type, respectively.
  • the base electrode of the transistor 108 is connected directly to the junction 106.
  • the emitter electrode of the transistor 108 and the collector electrode of the transistor 110 are connected together to the high potential line 62.
  • the collector electrode of the transistor 108 is connected directly to the base electrode of the transistor 110.
  • the emitter electrode of the transistor 110 is connected directly to a junction 112.
  • a bias resistor 114 is connected between the junction 112 and the low potential line 64. Further, the gate electrode of the field-effect transistor 58 in the coupling network 52 is connected directly to the junction 112.
  • the base-emitter junction area of the transistor 74 is greater than the base-emitter junction area of the transistor 72 by a factor of (3).
  • the amplitude of the error voltage defined between lines 54 and 56 is substantially zero (i.e., the base electrode of the transistor 72 is essentially shorted to the base electrode of the transistor 74)
  • a current 1 flows through the transistor 72 and the diode 84 and a current 1 approximately equal to (3) I flows through the transistor 74.
  • a current 1 approximately equal to the summation of the currents I and 1 or (4) I flows through the resistor 86 and the diode 90.
  • the anode-cathode junction area of the diode 90 is greater than the base-emitter junction area of the transistor 78 by a factor of (2).
  • I a current 1 approximately equal to (2) l flows through the transistor 78 out of the junction 92.
  • the anode-cathode junction area of the diode 84 is the same as the base-emitter junction area of the transistor 76.
  • a current 1 which is approximately equal to the current 1 flowing through the diode 84, flows through the transistor 76 into the junction 92.
  • the current I, flowing through the transistor 72 is approximately equal to the current 1 flowing through the transistor 74.
  • the current 1;, flowing through the diode 90 is equal to (2) l and the current 1 flowing through the transistor 78 is equal to 1,.
  • the current i flowing through the transistor 76 is equal to 1,. Therefore, the current 1 flowing into the junction 92 out of transistor 76 is approximately equal to the current I, flowing out of junction 92 into the transistor 78.
  • the current 1 flowing through the transistor 76 into the junction 92 exceeds the current 1 flowing through the transistor 78 out of the junction 92.
  • the current 1 flowing through the transistor 78 out of the junction 92 exceeds the current 1 flowing through the transistor 78 into the junction 92.
  • the Darlington-switch formed by the transistors 98 and 100 is rendered fully nonconductive.
  • the capacitor 94 is maintained fully charged through the resistors 102 and 104 so that the amplitude of the timing voltage V, developed across the capacitor 94 is at a maximum voltage level.
  • the timing voltage V at a maximum voltage level
  • the potential at the junction 106 is held at a relatively high voltage level by the voltage divider action of the resistors 102 and 104.
  • the buffer switch formed by the'transistors 108 and 110 is rendered fully nonconductive.
  • the transistors 108 and 110 With the transistors 108 and 110 turned off, bias voltage is withheld from across the resistor 114 at the junction 112 so that the field-effect transistor 58 is rendered fully nonconductive. With the transistor 58 turned off, the separation between the L and R output channels 22 and 24 of the stereo decoder 18 is defined at substantially full channel separation thereby to provide full stereophonic operation.
  • the timing capacitor 94 is substantially instantaneously discharged to rapidly decrease the amplitude of the timing voltage V, to a minimum voltage level defined just above the voltage level on the low potential line 64 by an amount equal to the saturation voltage drop of the transistors 98 and 100.
  • the potential at the junction 106 is dropped to a relatively low voltage level defined by the voltage divider action of the resistors 102 and 104.
  • the buffer switch formed by the transistors 108 and is rendered fully conductive.
  • a bias voltage is applied across the resistor 114 at the junction 112 to substantially instantaneously render the transistor 58 fully conductive.
  • the separation between the L and R output channels 22 and 24 of the audio decoder 18 is substantially instantaneously decreased to less than full channel separation thereby to shift toward full monophonic operation so as to reduce the audio distortion resulting from the distorted reception.
  • the Darlington switch formed by the transistors 98 and 100 is rendered fully nonconductive. With the transistors 98 and 100 turned off, the timing capacitor 94 charges through the resistors 102 and 104 to relatively gradually increase the amplitude of the timing voltage V, from the minimum voltage level back to the maximum voltage level in accordance with the RC time constant provided by the resistance of the resistors 102 and 104 and the capacitance of the capacitor 94.
  • the potential at the junction 106 likewise increases to slowly render the buffer switch formed by the transistors 108 and 110 fully nonconductive.
  • the bias voltage applied across the resistor 114 at the junction 112 is withdrawn to relatively gradually turn off the field-effect transistor 58.
  • the separation between the L and R output channels 22 of the audio decoder 18 is relatively gradually increased back to full channel separation thereby to slowly shift to full stereophonic operation so as to reduce the audio distortion resulting from the transition from less than full stereophonic operation back to full stereophonic operation.
  • FIG. 4 illustrates an embodiment of the impedance device 60 for reducing the discernible audio disruption resulting fromm the shift to less than full stereophonic operation from full stereophonic operation.
  • the impedance device 60 comprises a resistor 116 which is connected in series with the field-effect transistor 58 between the L and Routput channels 22 and 24 of the audio decoder 18.
  • the separation between the L and R output channels 22 and 24 is established at an intermediate channel separation defined below full channel separation and above zero channel separation.
  • the intermediate channel separation is defined below full channel separation in inverse proportion to the resistance of the resistor 116, or alternately, is defined above zero channel separation in direct proportion to the resistance of the resistor 116.
  • the resistor 116 provides blended stereophonic/- monophonic operation for reducing the discernible audio disruption resulting from the rapid shift toward full monophonic operation from full stereophonic operation.
  • FIG. 5 illustrates the operating characteristic of the coupling network 52 where the impedance device 60 includes the resistor 116 and the transistor 58 is turned'on.
  • FIG. 6 illustrates an embodiment of the impedance device 60 for maximizing the amount of stereophonic operation over the lower frequencies of the L and R audio signals thereby to enhance the total stereophonic effect while maximizing the amount of monophonic operation over the high frequencies of the L and R audio signals thereby to reduce the resulting audio distortion.
  • the impedance device 60 comprises a reactive element provided by a capacitor 118 which isconnected in series with the field-effect transistor 58 between the L and R output channels 22 and 24 of the audio decoder 18.
  • the separation between the L and R output channels 22 and 24 is variably defined between full channel separation and zero channel separation in direct proportion to the frequency of the L and R audio signals. More specifically, the separation between the L and R output channels 22 and 24 is variably established in inverse proportion to the reactance of the capacitor 118 which, in turn, is determined in inverse proportion to the frequency of the L and R audio signals.
  • FIG.-7 illustrates the operating characteristic of the coupling network 52 where the impedance device 60 comprises the capacitor 118 and where the transistor 58 is turned on.
  • FIG. 8 illustrates an embodiment of the impedance device 60 which is a combination of the embodiments shown in FIGS. 4 and 6 for providing all of the advantages of the embodiments shown in FIGS. 4 and 6.
  • the impedance device 60 comprises the series connection of the resistor 116 and the capacitor 118 with the field-effect transistor 58 across the L and R output channels 22 and 24 of the audio decoder 18. When the transistor 58 is turned on, a minimum separation between the L and R. output channels 22 and 24 is established atan intermediate channel separation located below full channel separation and above zero channel separation as determined by the resistance of the resistor 116.
  • FIG. 9 illustrates the operating characteristic of the coupling network 52 where the impedance device 60 comprises the series combination of the resistor 116 and the capacitor 118 and where the transistor 58 is turned on.
  • an FM-stereo decoder for demodulating a standard composite stereophonic signal including an L R signal, an L R modulated 38 KHz suppressed subcarrier signal, and a 19 KHz pilot signal; the combination comprising: means including a phase-lock-loop for generating a 38 KHz demodulating signal in phase synchronization with the 19 KHz pilot signal, the phaselockloop including a phase detector for producing an error voltage having an amplitude defined as a function of the phase difference between the 19 KHZ pilot signal and the 38 KHz demodulating signal such that the amplitude of the error signal increases in response to shifts in the phase of the 19 KHz pilot signal caused by distorted reception; means including an audio decoder having L and R output channels for demodulating the L R signal and the L R modulated 38 KHz sup pressed subcarrier signal in response to the 38 KHZ demodulating signal to provide an L audio signal on the L output channel and an R audio signal on the R output channel; a coupling network including an electronic switch connected
  • the level detector responsive to an initial predetermined increase in the amplitude of the error voltage due to the initiation of distorted reception to substantially instantaneously-turn on the electronic switch thereby to rapidly shift toward full monophonic operation for reducing the discernible audio distortion resulting from the distorted reception, the level detector including a timing network responsive to a subsequent predetermined decrease in the amplitude of the error voltage due to the termination of distorted reception to relatively gradually turn off the electronic switch thereby to slowly shift to full stereophonic operation for reducing the discernible audio disruption resulting from the shift back to full stereophonic operation.
  • an F M-stereo decoder for demodulating a standard composite stereophonic signal including an L +R signal, an L R modulated 38 KHz suppressed subcarrier signal, and a 19 KHZ pilot signal; the combination comprising: means including a phase-lock-loop for generating a 38 KHz demodulating signal in phase synchronization with the 19 KHZ pilot signal, the phase-lockloop including a phase detector for producing an error voltage having an amplitude defined as a function of the phase difference between the 19 KHZ pilot signal and the 38 KHZ demodulating signal such that the amplitude of the error signal increases in response to shifts in the phase of the 19 KHZ pilot signal caused by distorted reception; means including an audio decoder having L and R output channels for demodulating the L R signal and the L R modulated 38 KHZ suppressed subcarrier signal in response to the 38 KHZ demodulating signal.
  • a coupling network including an electronic switch connected across the L and R output channels of the audio decoder for establishing the separation between the L and R output channels at substantially full channel separation when the electronic switch is turned off and for establishing the separation between the L and R output channels at less than full channel separation when the electronic switch is turned on; and a level detector responsive to an initial predetermined increase in the amplitude of the error voltage due to the initiation of distorted reception to substantially instantaneously turn on the electronic switch thereby to rapidly shift toward full monophonic operation for reducing discernible audio distortion resulting from the distorted reception, the level detector including a timing network responsive to a subsequent predetermined decrease in the amplitude of the error voltage due to the termination of distorted reception to relatively gradually turn off the electronic switch thereby to slowly shift to full stereophonic operation for reducing the discernible audio disruption resulting from the shift to full stereophonic operation; the coupling network including a resistive element for establishing a minimum separation between the L
  • an F M-stereo decoder for demodulating a standard composite stereophonic signal including an L R signal, an L -R modulated 38 KHZ suppressed subcarrier signal, and a 19 KHZ pilot signal; the combination comprising: means including a phase-lock-loop for generating a 38 KHZ demodulating signal in phase synchronization with the 19 KHZ pilot signal, the phase-lockloop including a phase detector portion for producing an error voltage having an amplitude defined as a function of the phase difference between the 19 KHZ pilot signal and the 38 KHZ demodulating signal such that the amplitude of the error signal increases in response to shifts in the phase of the 19 KHz pilot signal caused by distorted reception; means including an audio decoder having L and R output channels for demodulating the L R signal and the L R modulated 38 KHZ suppressed subcarrier signal in response to the 38 KHZ demodulating signal to provide an L audio signal on the L output channel and an R audio signal on the R output channel;
  • an FM-stereo decoder for demodulating a standard composite stereophonic signal including an L R signal, an L R modulated 38 Z suppressed subcarrier signal, and a 19 KHZ pilot signal; the combination comprising: means including a phase-lock-loop for generating a 38 KHz demodulating signal in phase synchronization with the 19 KHZ pilot signal, the phase-lockloop including a phase detector for producing an error voltage having an amplitude defined as a function of the phase difference between the l9 KHZ pilot signal and the 38 KHZ demodulating signal such that the amplitude of the error signal increases in response to shifts in the phase of the l9 KHZ pilot signal caused by distorted reception; means including an audio decoder having L and R output channels for demodulating the L R signal and the L R modulated 38 KHz suppressed subcarrier signal in response to the 38 KHz demodulating signal to provide an L audio signal on the L output channel and an R audio signal on the R output channel; a coupling network

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US00383243A 1973-07-27 1973-07-27 Phase-lock-loop fm-stereo decoder including stereophonic/monophonic blend system for reducing audio distortion Expired - Lifetime US3825697A (en)

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CA205,714A CA1029097A (fr) 1973-07-27 1974-07-26 Decodeur fm stereophonique a boucle d'asservissement de phase comprenant un systeme melangeur stereophonique-monophonique destine a reduire la distorsion audio

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Cited By (13)

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US3911231A (en) * 1973-05-25 1975-10-07 Matsushita Electric Industrial Co Ltd Four-channel stereophonic reproducing system
US3931482A (en) * 1973-04-25 1976-01-06 Matsushita Electric Industrial Co., Ltd. Four-channel stereophonic reproducing system for reproducing discrete four-channel stereophonic discs
JPS51144551A (en) * 1975-06-06 1976-12-11 Sony Corp Amplifier
US4029906A (en) * 1975-04-18 1977-06-14 Sansui Electric Co., Ltd. Automatic noise reduction system of FM stereo receiver
US4037057A (en) * 1974-08-01 1977-07-19 Nippon Gakki Seizo Kabushiki Kaisha Noise-cancelling apparatus for FM stereo receiver
US4107463A (en) * 1977-07-06 1978-08-15 Pearson Edward E Stereophonic noise suppression system
US4146747A (en) * 1975-10-01 1979-03-27 Pioneer Electronic Corporation Fm stereo demodulating device
FR2415924A1 (fr) * 1978-01-25 1979-08-24 Philips Nv Circuit reducteur de bruit pour signaux stereo
US4466115A (en) * 1978-12-25 1984-08-14 Tokyo Shibaura Denki Kabushiki Kaisha FM Stereo signal demodulator
US5408685A (en) * 1992-04-06 1995-04-18 Ford Motor Company Multipath detector using phase comparison of stereo pilot signal
US20080231122A1 (en) * 2007-03-19 2008-09-25 Siemens Aktiengesellschaft Facility and method for the automatic recognition and differentiation of single-channel or dual-channel electronic sensors connected to a dual-channel safety combination
US20080242248A1 (en) * 2004-02-12 2008-10-02 Kabushiki Kaisha Toyota Jidoshokki Fm Receiver
US20080240469A1 (en) * 2007-04-02 2008-10-02 Funai Electric Co., Ltd. Flat-panel television and audio equipment

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US3673342A (en) * 1969-08-02 1972-06-27 Braun Ag Circuit arrangement for improving the signal-to-noise ratio of a stereo decoder
US3711652A (en) * 1971-03-10 1973-01-16 Gen Electric Monolithic stereo decoder with balanced decoder operation
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US3584154A (en) * 1968-06-17 1971-06-08 Clarence Hunter Mcshan Stereo multiplex decoding system with a phase locked loop switching signal control
US3673342A (en) * 1969-08-02 1972-06-27 Braun Ag Circuit arrangement for improving the signal-to-noise ratio of a stereo decoder
US3711652A (en) * 1971-03-10 1973-01-16 Gen Electric Monolithic stereo decoder with balanced decoder operation
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Cited By (16)

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US3931482A (en) * 1973-04-25 1976-01-06 Matsushita Electric Industrial Co., Ltd. Four-channel stereophonic reproducing system for reproducing discrete four-channel stereophonic discs
US3911231A (en) * 1973-05-25 1975-10-07 Matsushita Electric Industrial Co Ltd Four-channel stereophonic reproducing system
US4037057A (en) * 1974-08-01 1977-07-19 Nippon Gakki Seizo Kabushiki Kaisha Noise-cancelling apparatus for FM stereo receiver
US4029906A (en) * 1975-04-18 1977-06-14 Sansui Electric Co., Ltd. Automatic noise reduction system of FM stereo receiver
JPS51144551A (en) * 1975-06-06 1976-12-11 Sony Corp Amplifier
US4146747A (en) * 1975-10-01 1979-03-27 Pioneer Electronic Corporation Fm stereo demodulating device
US4107463A (en) * 1977-07-06 1978-08-15 Pearson Edward E Stereophonic noise suppression system
US4221928A (en) * 1978-01-25 1980-09-09 U.S. Philips Corporation Noise reduction circuit for stereo signals
FR2415924A1 (fr) * 1978-01-25 1979-08-24 Philips Nv Circuit reducteur de bruit pour signaux stereo
US4466115A (en) * 1978-12-25 1984-08-14 Tokyo Shibaura Denki Kabushiki Kaisha FM Stereo signal demodulator
US5408685A (en) * 1992-04-06 1995-04-18 Ford Motor Company Multipath detector using phase comparison of stereo pilot signal
US20080242248A1 (en) * 2004-02-12 2008-10-02 Kabushiki Kaisha Toyota Jidoshokki Fm Receiver
US20080231122A1 (en) * 2007-03-19 2008-09-25 Siemens Aktiengesellschaft Facility and method for the automatic recognition and differentiation of single-channel or dual-channel electronic sensors connected to a dual-channel safety combination
US7781922B2 (en) * 2007-03-19 2010-08-24 Siemens Aktiengesellschaft Facility and method for the automatic recognition and differentiation of single-channel or dual-channel electronic sensors connected to a dual-channel safety combination
US20080240469A1 (en) * 2007-04-02 2008-10-02 Funai Electric Co., Ltd. Flat-panel television and audio equipment
US8243968B2 (en) * 2007-04-02 2012-08-14 Funai Electric Co., Ltd. Flat-panel television and audio equipment

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