US4041533A - Delay circuitry - Google Patents

Delay circuitry Download PDF

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Publication number
US4041533A
US4041533A US05/615,084 US61508475A US4041533A US 4041533 A US4041533 A US 4041533A US 61508475 A US61508475 A US 61508475A US 4041533 A US4041533 A US 4041533A
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United States
Prior art keywords
signal
carrier signal
circuit
phase
delayed
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Expired - Lifetime
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US05/615,084
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English (en)
Inventor
Katsuhiko Yamamoto
Kunihiko Hontani
Hiromu Kitaura
Michio Nakamura
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority claimed from JP49112177A external-priority patent/JPS5138828A/ja
Priority claimed from JP1974155701U external-priority patent/JPS5728455Y2/ja
Priority claimed from JP15570074U external-priority patent/JPS5636220Y2/ja
Priority claimed from JP2272775U external-priority patent/JPS5611476Y2/ja
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
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Publication of US4041533A publication Critical patent/US4041533A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region

Definitions

  • This invention relates to a delay circuitry and more particularly to a delay circuitry employing a delay line, such as a supersonic delay line, a delay time of which is unstable due to the conditions around the delay line.
  • a delay line such as a supersonic delay line
  • a delay circuitry employing a supersonic delay line is used, for example, in a vertical aperture correction apparatus.
  • a carrier signal generated in a carrier signal generator is modulated by an amplitude modulator with a video input signal and the modulated carrier signal is delayed through the supersonic delay line by one horizontal scanning period.
  • the delayed video signal is obtained by detecting the modulated and delayed carrier signal with the carrier signal from the carrier generator in a synchronous detector.
  • the supersonic delay line Since the delay time of the supersonic delay line is not stable, but changes especially in accordance with the temperature therearound, the supersonic delay line should be soaked in a constant temperature oven to prevent any change of the delay time, if it is required to stabilize the gain of the delay circuitry.
  • This method is effective if the carrier signal frequency is not very high. But with an increase of the carrier signal frequency, the gain becomes less stable, even if the temperature change is limited by the constant temperature oven.
  • the video signal has a bandwidth of about 30 MHz and a carrier frequency of about 100 MHz is required
  • such a delay circuitry utilizing the constant temperature oven according to the prior art cannot be used as the 1H-delay line for the vertical aperture correction apparatus because of the reduced stability of the gain of the delayed video signal.
  • such a delay circuitry requires the space for the constant temperature oven.
  • An object of the invention is, therefore, to provide a delay circuitry which is adapted for delaying a broad-band video signal.
  • Another object of the invention is to provide a delay circuitry the gain of which is stable irrespective of the change of the temperature therearound which causes drift and fluctuation of the delay time of the delay line employed therein.
  • a further object of the invention is to provide a delay circuitry which does not require a bulky constant temperature oven.
  • the carrier signal is amplitude-modulated with the input video signal and delayed through the delay line such as a supersonic delay line.
  • the delayed video signal is obtained by demodulating the modulated and delayed carrier signal by a synchronous detector with a reference signal, the phase of which is adjusted to be in phase with the modulated carrier signal by detecting the phase difference between the modulated carrier signal and the reference signal, so that the gain of the delayed video signal will not be affected by the drift and the fluctuation of the delay time of the delay line.
  • the reference signal is produced from the carrier signal generated in the carrier signal generator through a variable phase shifter which shifts the phase of the carrier signal properly in accordance with a detection voltage representing the phase difference between the modulated and delayed carrier signal and the reference signal so that they are always in phase.
  • the carrier signal is shifted in accordance with the detection voltage and then modulated by the video signal and delayed.
  • the modulated and delayed carrier signal is demodulated by the synchronous detector with the reference signal which is produced from the carrier signal and is in phase with the delayed modulated carrier signal.
  • a reference pulse signal is superposed upon the video signal in the horizontal blanking period.
  • the carrier signal is amplitude-modulated with the superposed video signal and delayed, and then demodulated by a synchronous detector with a reference signal.
  • the reference pulse signal is extracted from the demodulated video signal, then its amplitude is detected to produce the detection voltage with which the phase of the reference signal or the carrier signal is adjusted properly so that the gain of the pulse signal will always be constant.
  • FIG. 1 is a block diagram of the first embodiment of a delay circuitry according to this invention.
  • FIG. 2A and FIG. 2B are diagrams of a video signal and an amplitude-modulated carrier signal in the delay circuitry of FIG. 1;
  • FIG. 3 is a circuit diagram showing the principal part of the delay circuitry of FIG. 1;
  • FIG. 4 is a diagram for showing the characteristic of a variable capacitor diode employed in the variable phase shifter in FIG. 1;
  • FIG. 5 is a diagram for showing the characteristic of the variable phase shifter in FIG. 1;
  • FIG. 6 is a circuit diagram showing the principal part of a second embodiment of a delay circuitry according to this invention.
  • FIG. 7A and FIG. 7B are diagrams of the other examples of wave shapes of the modulated carrier signal
  • FIG. 8 is a block diagram of a third embodiment of a delay circuitry according to this invention.
  • FIG. 9 is a block diagram of a fourth embodiment of this invention.
  • FIG. 10 is a vector diagram for showing the operation of the delay circuitry of FIG. 9;
  • FIG. 11 is a block diagram of a fifth embodiment of this invention.
  • FIG. 12 is a block diagram of a further embodiment of the delay circuitry of the invention.
  • FIG. 13A and FIG. 13B are diagrams showing modulated carriers in a video signal period and in a reference pulse signal period which are superposed together in the circuitry of FIG. 12.
  • a video input signal which is to be delayed and upon which a reference pulse signal has been superposed in the blanking period thereof as shown in FIG. 2A is supplied through an input terminal 1 to an amplitude modulator 2, such as a balanced modulator, where a carrier signal generated in a carrier signal generator 7 is amplitude-modulated with the video signal.
  • the modulated carrier signal as shown in FIG. 2B, is amplified in an amplifier 3, delayed through a supersonic delay line (1H-delay line) 4 by one horizontal period in this case and amplified by an amplifier 5, and then demodulated by a synchronous detector 6 with a reference signal to produce a 1H-delayed video signal which is derived through an output terminal 13.
  • phase comparator 9 One part of the modulated and delayed carrier signal which is modulated with the reference pulse signal is extracted by a gate circuit 8 and provided to one input terminal of a phase comparator 9.
  • the carrier signal from the carrier signal generator 7 has its phase properly set by a variable phase shifter 11 in accordance with a control voltage from the phase comparator 9, then provided to another input terminal of the phase comparator 9.
  • the control voltage representing the phase difference between the modulated and delayed carrier signal and the reference signal is obtained there by comparing the phases thereof and is used to shift the phase of the carrier signal from by the carrier signal generator 7, so that the shifted carrier will always lag by 90° in comparison with the modulated carrier.
  • a sampling hold circuit 10 is utilized to maintain the desirable shifting condition throughout the scanning period of the video signal.
  • the phase adjusted carrier signal then has its phase advanced by 90° through a phase shifter 12 to produce the phase tracked reference signal which is always in phase with the modulated and delayed carrier signal, so that the gain of the synchronous detector 6 will always be a maximum.
  • FIG. 3 is a schematic circuit diagram showing an example of a phase control circuit loop in the delay circuitry of FIG. 1.
  • the delayed carrier signal modulated with the reference pulse signal is extracted from the modulated and delayed signal by the gate circuit 8 constituted by a conventional diode bridge circuit activated by positive and negative pulses 101 and 102 which are synchronized with the input video signal.
  • the extracted carrier signal such as shown at 103 is amplified by a transistor 14 in the phase comparator 9 and provided to a primary winding of a transformer 15, a center tap of the secondary winding of which is grounded, to generate two carrier waves having the same amplitude but opposite polarities to each other at the opposite ends of the secondary winding.
  • the phase comparator 9 can be constituted by a conventional phase detector comprising the transformer 15, resistances 18 and 19 and two diodes 16 and 17 to the connection point of which the carrier signal from the variable phase shift 11 is supplied.
  • the detected output is set so as to be zero when the phase relationship of the modulated carrier signal to the delayed carrier signal is 90° ahead, and to be positive and negative in response to any increment or decrement from such a phase relationship.
  • the detected output such as shown at 104 is amplified by an operation amplifier 20 and converted to a DC voltage through a high input impedance amplifier 21 and capacitor 22. When a gate pulse 105 appears, a switch S w is closed and the capacitor 22 is charged with the output voltage of the amplifier 20.
  • This voltage is held until the next detection pulse is provided after the gate pulse 105 goes to zero and the switch is opened, because of the high input impedance of the amplifier 21. Since the gate pulse 105 appears simultaneously with the aforesaid gate pulses 101 and 102 and the pulse width thereof is slightly shorter than those of pulses 101 and 102, only the peak voltage of the detection output 104 is derived as the output 106 of the amplifier 21.
  • the DC output voltage 106 is then amplified by the DC amplifier 23 and the variable range thereof is shifted suitably by a zener diode 24, a resistance 25 and a DC voltage source +B 2 , to produce a control voltage for the variable phase shifter 11.
  • the DC amplifier 23 may have a variable range of about -V B1 to +V B1 , where -V B1 and +V B1 indicate the negative and positive DC voltage of the voltage sources, -B 1 and +B 1 , respectively.
  • the voltage range of the control voltage becomes almost (V B1 - V Z ) to (V B1 + V Z ), where V Z is the voltage between the two electrodes of the zener diode 24.
  • the carrier signal from the carrier signal generator 7 is supplied to the emitter follower 27 and delayed through a derived m-type delay line 28, the delay time of which is adjusted suitably by controlling the capacitance of the respective capacitor diodes 29(a), 29(b), 29(c)--, each of which has characteristic such as shown in FIG. 4, in accordance with the control voltage from the zener diode 24. Resistances 30 and 31 are for impedance matching of the delay line 28.
  • the delayed carrier signal is amplified by an amplifier 32 and derived through a transformer 33. It is supplied to the phase comparator 9, and to the 90° -- phase shifter 12 as well to produce the phase tracked reference signal utilized to demodulate the 1H-delayed video signal.
  • phase relationship between the modulated carrier signal from the gate circuit 8 and the phase adjusted carrier signal from the variable phase shifter 11 is adjusted to be a 90° phase difference by setting a variable resistance 26 in the DC amplifier 23 at the standard state.
  • the phase of the reference signal is adjusted by the phase shifter 12, so that it will be substantially in phase with that of the modulated carrier signal.
  • phase of the modulated carrier signal is ahead more than 90° in comparison with that of the shifted carrier signal, for instance, because of a change in the temperature of the 1H-delay line 4, positive pulses appear as the detected output 104 and the higher the control voltage becomes.
  • the increase of the control voltage results in the decrease of the capacitance of each variable capacitor diode which has a characteristic as shown in FIG. 4, and therefore a reduction of the delay time of the variable phase shifter 11. Consequently, the carrier signal is caused to advance until the phase difference returns to 90°. On the contrary, if the phase of the modulated carrier lags, negative pulses appear as the detected output. This results in a decrease of the control voltage, and therefore an increase of the delay time. The carrier signal is delayed until the phase difference becomes 90°.
  • the phase difference between the modulated carrier signal and the shifted carrier signal from the variable phase shifter 11 is maintained always 90° in such a manner, the phase relationship between the modulated carrier signal and the reference signal is kept in phase, and the 1H-delayed video signal, that is the output of the synchronous detector 6 is stable independantly of the drift and the fluctuation of the delay time of the 1H-delay line 4.
  • ⁇ 2 ⁇ f ⁇ L C V3/2. Therefore, the gross phase delay ⁇ throughout the variable phase shifter 11 is such as shown in FIG. 5.
  • Vs and ⁇ s in FIG. 5 indicate the control voltage and the gross phase delay which provide the aforesaid phase relationship between the modulated carrier signal and the delayed carrier signal at the standard state
  • ⁇ max and V min indicate the maximum and minimum phase delay according to the minimum and maximum control voltage Vmin and Vmax, repsectively
  • ⁇ and ⁇ V indicate the gross phase shift from ⁇ s and the voltage shift of the control voltage from Vs which are required to maintain such a phase relationship in a certain condition.
  • FIG. 6 shows another phase control circuit loop having a sufficient wide shift range, e.g. more than one period of the video signal, to maintain the desired phase relationship difference of 90°.
  • the phase control circuit loop of FIG. 6 includes a reset circuit 34 in addition to the circuit loop of FIG. 3, which resets the former control voltage when it tends to exceed Vmin or Vmax in FIG. 5 to hold the phase shift through the variable phase shifter 11 always within the controllable shift range, that is ( ⁇ max- ⁇ min)>360°.
  • the control voltage from the sampling hold circuit 10 is provided to the first input terminal of each operation amplifier 37 or 38 through a resistance 35 or 36.
  • a reference voltage V 1 which is determined by a variable resistance 39 connected between a positive voltage source +B 3 and a negative voltage source -B 3 .
  • a reference voltage V 4 is provided, which is determined by a variable resistance 40 connected between the same voltage sources +B 3 and -B 3 .
  • the reference voltage V 1 is selected so as to be higher than the minimum control voltage Vmin, and the reference voltage V 4 is selected to be lower than the maximum control voltage Vmax as shown in FIG. 5.
  • the output terminals of the operation amplifiers 37 and 38 are connected to the first input terminals of AND gates 45 and 46, and also to the second input terminals of the respective amplifiers through feedback resistances 43 and 44, respectively.
  • a periodic pulse 107 such as a vertical drive pulse for synchronizing a vertical deflection of the video signal reproducing system.
  • the operation amplifiers 37 and 38 have hysteresis characteristics such that the positive output voltages thereof are reset in accordance with the control voltages such as V 2 and V 3 which are higher than V 1 and lower than V 4 , respectively, by a few volts.
  • the output voltages of the operation amplifier 37 and 38 are fed back to the second input terminals of the amplifiers through the resistances 43 and 44, respectively. Accordingly, even if the control voltage changes slowly near the threshold voltage of the operation amplifiers 37 and 38, they operate much more accurately than those without such hysteresis characteristics.
  • the possible shift range of the variable phase shifter 11 without such resetting of the control voltage is ( ⁇ 1 - ⁇ 4 ) > 360°, where ⁇ 1 and ⁇ 4 are the gross phase delays corresponding to the control voltages V 1 and V 4 , respectively.
  • the phase relationship between the modulated carrier signal and the adjacent carrier signal from the carrier signal generator 7 after such resetting of the former control voltage is controlled firstly in accordance with the clamp voltage V L or V H , and then adjusted to be the desired phase relationship that is 90° phase difference.
  • the wave shape of the modulated carrier signal from the amplitude modulator 2 is not restricted to that shown in FIG. 2B, that is of 100%-modulation. Under-modulation and over-modulation methods can be also used, the wave shapes for which are shown in FIG. 7A and FIG. 7B, respectively. With either method, the superposition of the reference pulse signal upon the input video signal is not required. Moreover, if the under-modulation method is used, the gate circuit 8 may be replaced by a limiter for deriving a continuous modulated carrier signal of constant amplitude, and the sampling hold circuit 10 may be omitted because the control voltage is derived directly from the output of the phase comparator such as 9.
  • FIG. 8 shows a third embodiment of this invention having a voltage controlled oscillator for generating a phase tracked reference signal by which the delayed video signal is detected.
  • the constitutions of the circuits designated by 1 ⁇ 6, 8, 10 and 12 are same as the corresponding circuits of FIG. 1.
  • the carrier signal generated in a carrier signal generator 55 is amplitude-modulated with the input video signal in the same way as in the delay circuitry of FIG. 1.
  • the modulated carrier signal is extracted by the gate circuit 8 at the reference pulse signal portion and its phase is compared with that of a carrier signal generated by a conventional voltage controlled oscillator 57 in a phase comparator 56 which has the same construction as the phase comparator 9 of FIG.
  • the carrier signal from the voltage controlled oscilator 57 is supplied to the connection point of the two diodes 16 and 17 instead of the carrier signal from the variable phase shifter 11.
  • the control voltage is produced in the sampling hold circuit 10 from the detected output from the comparator 56, and it is utilized to control the voltage controlled oscillator 57.
  • the phase of the carrier signal from the voltage controlled oscillator 57 which is adjusted with the control voltage so as to lag by 90° the modulated and delayed carrier signal, then has the phase thereof advanced by 90° by the 90°-phase shifter 12 to produce the reference signal. Since the reference signal is always in phase with the modulated and delayed carrier signal from the amplifier 5, the delayed video signal which is obtained as the output of the synchronous detector 6 is stable irrespective of the drift and fluctuation of the delay time of the 1H-delay line 4.
  • variable phase shifter such as 11 in FIG. 1 should be connected between the carrier signal generator 7 and the amplitude modulator 2, to which variable phase shifter 11 the control voltage is supplied, and the reference signal utilized to detect the modulated carrier signal should be produced from the carrier signal generator 7 through the 90°-phase shifter 12.
  • the fourth embodiment shown in FIG. 9, provides a delay circuitry in which only one carrier signal generator is employed and the phase tracked reference signal the phase of which is adjusted so as to be always in phase with that of the modulated and delayed carrier signal is derived from the carrier signal generated in the carrier signal generator without the variable phase shifter such as 11 in FIG. 1.
  • the carrier signal from the carrier signal generator 55 is amplitude-modulated with the input video signal by under-modulation such as shown in FIG. 7A, and the modulated and delayed carrier signal 108 is supplied to a limiter 58 to produce a continuous signal 109 which has the same phase and the same frequency as the modulated carrier signal 108.
  • the carrier signal from the carrier generator 55 is also supplied to a balanced modulator 60 and to another balanced modulator 61 through a 90°-phase shifter 59 to modulate detected outputs V 63 and V 64 of phase detectors 63 and 64, respectively.
  • the two output terminals of the balanced modulators 60 and 61 are connected together to produce a mixed signal.
  • the phase detectors 63 and 64 detect the continuous signal from the limiter 58 with the mixed signal and the output of a 90° phase shifter 62, respectively.
  • the phase tracked reference signal is obtained from the mixed signal and used to demodulate the delayed video signal in the synchronous detector 6.
  • a switch 65 is closed to provide a DC voltage Es to both balanced modulators 60 and 61.
  • the outputs of the balanced modulators 60 and 61 designated as vectors V 60 and V 61 , appear when the switch 65 is closed, the output V 60 being in phase with the carrier signal, designated as vector V 55 , from the carrier signal generator 55, and the output V 61 lagging the carrier V 55 by 90°, but having the same amplitude as the output V 60 as shown in the vector diagram of FIG. 10. Since the output terminals of the balanced modulators 60 and 61 are connected together, the mixed signal V 66 which appears at the connection point 66 is the sum of the vector V 60 and the vector V 61 as shown in FIG. 10.
  • the continuous signal V 58 from the limiter 58 is detected by the mixed signal V 66 and the 90°-phase-shifted mixed signal V 62 in the phase detectors 63 and 64 to generate the DC detection voltages V 63 and V 64 , respectively.
  • cos ( ⁇ - 45°) and V 64
  • the carrier signal V 55 and the 90°-phase-shifted carrier V 59 are modulated with these two detection voltages V 63 and V 64 in the balanced modulators 60 and 61, respectively.
  • the mixed signal V 66 that is the reference signal
  • the phase thereof is the same as that of the continuous signal 109 or the modulated carrier signal 108. Since the reference signal is given as the vector summation, the desired phase relationship between the reference signal and the modulated carrier signal 108, that is an in phase relationship, is retained despite any fluctuation or change of phase in the modulated carrier signal 108 which originates in the change of the delay time of the 1H-delay line 4 even if it is more than one period of the video signal.
  • FIG. 11 shows a fifth embodiment of the invention, where the phase difference between the modulated and delayed carrier signal and the reference signal is detected by detecting the demodulated level of a reference pulse signal which is inserted in the blanking period of the input video signal such as shown in FIG. 2A.
  • the reference pulse signal from a pulse generator 67 is superposed upon the input video signal in an adding circuit 68, and the carrier signal from the carrier signal generator 69 is modulated with the output of the adding circuit 68 in the same way as in the aforementioned embodiments.
  • the carrier signal which is delayed through the supersonic 1H-delay line 4 is demodulated in the synchronous detector 6 with the reference signal produced from the carrier signal from the carrier signal generator 69 through a variable phase shifter 70, such as 11 in FIG. 1.
  • the reference pulse signal is extracted from the output of the synchronous detector 6 with the reference pulse signal from the pulse generator 67 through a gate circuit 71 and then detected by a conventional amplitude detector 72 to produce a control voltage the amplitude of which is proportional to the amplitude of the reference pulse signal and, therefore, is inversely proportional to the phase difference between the modulated carrier signal and the reference signal. Then the delay time of the variable phase shifter 70 is adjusted so that the amplitude of the reference pulse signal is a maximum to maintain the gain of the synchronous detector 6 at a maximum.
  • the phase comparator 9 or 56 in FIG. 1 or FIG. 8 is unnecessary to detect the phase difference, because the amplitude of the reference signal extracted by the gate circuit 71 from the output of the synchronous detector 6 represents such phase difference.
  • the variable phase shifter 70 should function such that the delay time thereof only increase (or decrease) in response to the decrement (or increment) of the control voltage from the amplitude detector 72, which results in a slow response.
  • the carrier signal generated in the carrier signal generator 73 is gated with the reference pulse signal from the pulse generator 76 in the gate circuit 74 and has the phase thereof advanced by 90° as shown in FIG. 13B in the 90°-phase shifter 75, and then is, mixed in the adding circuit 77 with the modulated carrier signal which is shown in FIG. 13A.
  • the reference signal is obtained from the carrier signal through the variable phase shifter 70 in the same manner as in the above-described embodiments.
  • the reference pulse signal Since the phase of the carrier signal is varied by 90° between the reference pulse signal period and the video signal period, the reference pulse signal should be always zero when the reference signal and the modulated carrier signal in the video signal period are in phase with each other. Therefore, the delay time of the variable phase shifter 70 is controlled so that the reference pulse signal will be zero to produce the delayed video signal the gain of which is always maximum irrespective of the drift of the delay time of the delay line 4.
  • the gate circuit 71 has the same constitution as the gate circuit 8 in FIG. 3, and the amplitude detector 72 can be constituted by the common integrating circuit, the DC amplifier and voltage range shifter such as shown in FIG. 3.
  • this circuitry does not utilize a phase comparator or phase detector for detecting the phase difference between the modulated carrier and the reference signal, it operates is substantially in the same manner as the circuitry in FIG. 1 or FIG. 3 because such a phase difference is detected in the synchronous detector 6.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Television Signal Processing For Recording (AREA)
US05/615,084 1974-09-28 1975-09-19 Delay circuitry Expired - Lifetime US4041533A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP49112177A JPS5138828A (fr) 1974-09-28 1974-09-28
JP1974155701U JPS5728455Y2 (fr) 1974-12-19 1974-12-19
JA49-155700[U]JA 1974-12-19
JP15570074U JPS5636220Y2 (fr) 1974-12-19 1974-12-19
JP2272775U JPS5611476Y2 (fr) 1975-02-18 1975-02-18

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CA (1) CA1034251A (fr)
DE (1) DE2543113C3 (fr)
GB (1) GB1515408A (fr)

Cited By (9)

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Publication number Priority date Publication date Assignee Title
US4371839A (en) * 1980-04-03 1983-02-01 Ford Aerospace & Communications Corporation Differentially coherent signal detector
DE3225831A1 (de) * 1981-07-09 1983-02-10 Sony Corp., Tokyo Videosignal-verarbeitungsschaltung
US4379266A (en) * 1980-04-03 1983-04-05 Ford Aerospace & Communications Corporation PSK Demodulator with automatic compensation of delay induced phase shifts
US4475088A (en) * 1981-06-04 1984-10-02 Westinghouse Electric Corp. Gain imbalance corrected quadrature phase detector
US4808936A (en) * 1988-03-25 1989-02-28 Tektronix, Inc. Continuously variable clock delay circuit
US5285122A (en) * 1991-06-28 1994-02-08 Sanyo Electric Co., Ltd. Variable delay device
US5384919A (en) * 1993-12-16 1995-01-31 Smith; W. Fred Toilet seat supported bidet
US6433830B1 (en) * 1999-06-14 2002-08-13 General Instrument Corporation Off-air phase lock technique
US20090304053A1 (en) * 2008-06-10 2009-12-10 Advantest Corporation Digital modulator, digital modulating method, digital transceiver system, and testing apparatus

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Publication number Priority date Publication date Assignee Title
US4831444A (en) * 1986-11-06 1989-05-16 Olympus Optical Co., Ltd. Video camera device with separate camera head and signal processing circuit
DE3819930A1 (de) * 1988-06-11 1989-12-21 Thomson Brandt Gmbh Schaltungsanordnung zur einstellung der phasenlage eines signals
JPH06253234A (ja) * 1993-02-23 1994-09-09 Toshiba Corp 信号復調装置

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US2957042A (en) * 1956-05-25 1960-10-18 Rca Corp Video signal compensation
US3705952A (en) * 1970-09-15 1972-12-12 Gen Electric Vertical aperture correction circuit
US3843930A (en) * 1972-03-02 1974-10-22 Hughes Aircraft Co Time delay controller circuit for reducing time jitter between signal groups
US3925608A (en) * 1972-07-08 1975-12-09 Philips Corp Arrangement for signal delay, particularly for use in a vertical aperture corrector for television

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2957042A (en) * 1956-05-25 1960-10-18 Rca Corp Video signal compensation
US3705952A (en) * 1970-09-15 1972-12-12 Gen Electric Vertical aperture correction circuit
US3843930A (en) * 1972-03-02 1974-10-22 Hughes Aircraft Co Time delay controller circuit for reducing time jitter between signal groups
US3925608A (en) * 1972-07-08 1975-12-09 Philips Corp Arrangement for signal delay, particularly for use in a vertical aperture corrector for television

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4371839A (en) * 1980-04-03 1983-02-01 Ford Aerospace & Communications Corporation Differentially coherent signal detector
US4379266A (en) * 1980-04-03 1983-04-05 Ford Aerospace & Communications Corporation PSK Demodulator with automatic compensation of delay induced phase shifts
US4475088A (en) * 1981-06-04 1984-10-02 Westinghouse Electric Corp. Gain imbalance corrected quadrature phase detector
DE3225831A1 (de) * 1981-07-09 1983-02-10 Sony Corp., Tokyo Videosignal-verarbeitungsschaltung
DE3225831C2 (de) * 1981-07-09 1991-09-12 Sony Corp Videosignal-verarbeitungsschaltung
US4808936A (en) * 1988-03-25 1989-02-28 Tektronix, Inc. Continuously variable clock delay circuit
US5285122A (en) * 1991-06-28 1994-02-08 Sanyo Electric Co., Ltd. Variable delay device
US5384919A (en) * 1993-12-16 1995-01-31 Smith; W. Fred Toilet seat supported bidet
US6433830B1 (en) * 1999-06-14 2002-08-13 General Instrument Corporation Off-air phase lock technique
US20090304053A1 (en) * 2008-06-10 2009-12-10 Advantest Corporation Digital modulator, digital modulating method, digital transceiver system, and testing apparatus
US8014465B2 (en) * 2008-06-10 2011-09-06 Advantest Corporation Digital modulator, digital modulating method, digital transceiver system, and testing apparatus

Also Published As

Publication number Publication date
GB1515408A (en) 1978-06-21
DE2543113B2 (de) 1978-11-23
DE2543113A1 (de) 1976-04-15
DE2543113C3 (de) 1979-07-26
CA1034251A (fr) 1978-07-04

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