US4374410A - Data processing system - Google Patents

Data processing system Download PDF

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Publication number
US4374410A
US4374410A US06/064,725 US6472579A US4374410A US 4374410 A US4374410 A US 4374410A US 6472579 A US6472579 A US 6472579A US 4374410 A US4374410 A US 4374410A
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Prior art keywords
address
bits
order
block
processing unit
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Expired - Lifetime
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US06/064,725
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English (en)
Inventor
Toshihiro Sakai
Tetsuji Kuhara
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Fujitsu Ltd
Usac Electronic Ind Co Ltd
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Fujitsu Ltd
Usac Electronic Ind Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

Definitions

  • This invention relates to a data processing system which has an address bus whose bus width is smaller than the number of bits of an address register of a central processing unit.
  • microcomputers in which central processing units are each formed with a one-chip LSI.
  • the number of input/output pins is limited; for example, the number of address pins is usually limited to about sixteen.
  • a logical address of the virtual memory system is such as, for example, shown in FIG. 1A; that is; the 0th to 14th bits indicate a page number in virtual memory, and the 15th to 23rd bits an address in page, and the real memory capacity is, for instance, 128K bytes.
  • the 0th to 7th bits indicate a page number or a leading address of the page in real memory, and the 8th to 16th bits an address in page.
  • a central processing unit cannot at one time send out such a 24-bit logical address as shown in FIG. 1A.
  • the central processing unit is required to transfer such a 17-bit real address, as is shown in FIG. 1B, to a main memory without address conversion.
  • the number of address pins is 16, as mentioned above, it is impossible to send out at one time the 17-bit real address.
  • 8-bit registers R 1 , R 2 and R 3 are provided in a central processing unit 1, as shown in FIG. 2, and, in the case of delivering a logical address, address information of the 0th to 15 th bits is first sent out on an address bus 4, and then address information of the 16th to 23rd bits is sent out on the address bus 4.
  • the bus width of the address bus 4 is 16-bit.
  • the page number in virtual memory comprising the 0th to 14th bits (of the address information which is totally delivered in two transmissions), is converted into a page number in real memory (0th to 7th bits in FIG. 1B) by means of a dynamic address conversion part 2 shown in FIG. 3.
  • the page number of the real address is thus provided by the dynamic address conversion part 2, the 15th bit of the logical address page number being retained unconverted, and the address in page (15th to 23rd bits) being transferred subsequently.
  • a real address is formed, which real address is provided to a main memory (not shown in FIG. 3) for access thereto.
  • such real address information of the 17-bit configuration shown in FIG. 1B is stored in the registers R 1 , R 2 and R 3 which make up an address register 1a.
  • the information is stored with the 16th bit lying at the right-most end.
  • the address information of the 0th to 8th bits is provided on the address bus 4 and stored in a register 3.
  • the address information of the 9th to 16th bits is provided on the address bus 4 to form, with the address information previously stored in the register 3, address information of a 17-bit configuration, and this address information is transferred to the main memory.
  • the address information is divided into two portions and transferred in two transmissions so as not to overlap each other.
  • the address information transferred second is 8-bit in size, so that in the case of the 24-bit configuration the address information corresponding to the full bus width of 16 bits is transferred first, whereas in the case of the 17-bit configuration the 9-bit address information is transferred first.
  • address information or data is transmitted and received in two stages due to the limitation imposed on the number of input/output pins.
  • the address information or data is usually transmitted and received half at a time.
  • a real address having a number of bits smaller than M is set in the low order positions of an address register.
  • the number of bits of this real address is usually larger than M/2, so that in the system of the type transferring address information half at a time, as referred to above, it is necessary to retain some of the first transferred bits.
  • An object of this invention is to provide a data processing system which enables addressing without increasing the amount of hardware used.
  • Another object of this invention is to provide a data processing system which is designed to transfer, by two transfer operations, address information having a larger number of bits than the bus width of an address bus, so as to maintain the access operation speed unchanged, even in the case of requiring address conversion, and to minimize bit retention hardware, even in the case of retaining some of the bits transferred.
  • FIGS. 1A and 1B are diagrams explanatory of a logical address and a real address, respectively;
  • FIG. 2 is a block diagram showing a conventional address information transmitting part
  • FIG. 3 is a block diagram illustrating the principal part of a conventional data processing system of a virtual memory system
  • FIG. 4 is a block diagram showing the principal part of an embodiment of this invention.
  • FIGS. 5A and 5B are diagrams explanatory of the transmission of a logical address
  • FIG. 6 is a block diagram illustrating the principal part of an address information transmitting part of the embodiment of this invention.
  • FIG. 7 is a detailed block diagram of the embodiment of this invention.
  • FIG. 8 is a timing chart explanatory of the operation of the present invention.
  • FIG. 9 is a detailed logic block diagram of the multiplexer 40.
  • FIG. 10 is a flowchart of the conversion of a logical address to a real address.
  • FIG. 4 illustrates in block form the principal part of an embodiment of this invention.
  • Reference numberal 5 indicates a central processing unit; 6 designates a page table address register; 7 identifies a page table; 8 denotes a multiplexer; 9 represents a main memory; 10 and 12 show address decoders; and 11 refers to an address bus. The following description will be given on the assumption that the address bus 11 has a bus width of 16 bits.
  • the page table 7 is formed, for example, with a random access memory and, in the case of the logical memory capacity being 1 M byte, the page table 7 has 0th to 2047th addresses, each having a one-to-one correspondence to respective page numbers of a logical address. Further, each address has written therein a change bit C, an invalid bit I, a reference bit R, and a leading address of a page in real memory, that is, the page number in real memory.
  • FIGS. 5A and 5B are explanatory of the operation of an address information transmitting part of the central processing unit.
  • the address information transmitting part first sends out address information of 0th to 15th bits, as shown in FIG. 5A, and then sends out address information of 8th to 23rd bits, as shown in FIG. 5B.
  • FIG. 6 illustrates in block form the principal part of the address information transmitting part of the central processing unit 5.
  • Reference numerals 13-0 through 13-3 indicate registers forming an address register 13, the registers 13-1 through 13-3 respectively corresponding to the registers R 1 through R 3 shown in FIG. 2.
  • Reference numeral 14 designates a multiplexer, and numeral 15 identifies a memory. Address information is stored in the memory 15, and is then read out therefrom, 16 bits at a time, for input to the address register 13. Where the logical address in a virtual memory system has a 24-bit configuration, the 0th to 23rd bits are set, by two readout operations from the memory 15, in the registers 13-1 through 13-3.
  • the 0th to 16th bits of the real address information are set in 7th to 23rd bits, respectively, of the registers 13-1 through 13-3.
  • the page number of the 0th to 14th bits of the logical address and the 15th bit of the address in page, totalling 16 bits in all are first sent out on the address bus 11, as shown in FIG. 5A.
  • the page number in virtual memory is set in the page table address register 6 and is decoded by the decoder 12 so as to access the page table 7.
  • the page number in real memory is provided as an output.
  • address information of the 8th through 23rd bits is sent out on the address bus 11 and is combined with the page number read out of the page table 7 to form a real address.
  • FIG. 7 which shows a specific operative example of this invention
  • FIG. 8 which shows a timing chart
  • the logical address in a virtual memory system has a 24-bit configuration
  • the page number and the address in page are 15-bit and 9-bit, respectively, that the real address in the case of a system other than a virtual memory system has a 17-bit configuration, and that the address bus has a 16-bit bus width.
  • the 15-bit initial page number in virtual memory is to be converted to an 8-bit real page number in real memory.
  • the logical address is set in an address register 101 composed of registers 13-0 through 13-3 in a central processing unit 100, as previously described above with reference to FIG. 6.
  • the logical address is set at times T1 through T3, and (further referring to both FIG. 7 and FIG. 8) a gate 102 is opened by a gate timing signal t1 so as to send out address information of the 0th to 15th bits to an address bus 20 via an OR gate 104.
  • timing diagram AD 00 ⁇ 15 in FIG. 8 shows the hatched part between times T1 and T2 represents effective information.
  • a timing signal t2 the 0th to 14th bits are set in an address register 202 of an address conversion part 200. This is shown by timing diagram ACR in FIG. 8.
  • the information of the 0th to 14th bits, indicating the page number of the logical address set in the address register 202, is decoded by a decoder 202 to permit access of page table 201 by means of which the page number in real memory is read out therefrom, as described above, and is set in a register 204.
  • the page number of the 8-bit configuration, thus set in the register 204, is transferred to a multiplexer 40.
  • multiplexer 40 is provided with an input MODE which takes on a value of 0 when the data processing system is being operated as a virtual memory system, and takes on a value of 1 when the data processing system is being operated as a real memory system.
  • Multiplexer 40 responds to this condition by passing the 8-bit page number in real memory to address register 302 in main memory 300. Further details of the multiplexer 40 are provided below.
  • a gate 103 is opened so as to send out the information of the 8th to 23rd bits of the address register 101 on the address bus 20 through OR gate 104.
  • This is represented by timing diagram AD 08 ⁇ 23 in FIG. 8.
  • the 15th to 23rd bits of this address information are, by means of timing signal t4, applied directly to the address register 302 (in main memory 300), where they are combined with the address information (real page number) previously provided via multiplexer 40 by the address conversion part 200 and set by timing signal t4 in address register 302 of main memory 300.
  • timing diagram MAR in FIG. 8.
  • the address information in real memory set in the address register 302 is a combination of the 8-bit page number in real memory provided by the address conversion part 200 and the address in page of the 15th to 23rd bits from the 8th to 23rd bits sent out on the address bus 20 during time t3.
  • This real address information is decoded by a decoder 303 so as to permit access to memory 301, and information read out therefrom is set in a register 304, thereafter being transferred via a data bus 30 to central processing unit 100.
  • the page number of the logical address can be immediately converted into a page number in real memory, and, by combining the page number in real memory with the second address information, the main memory can be accessed without employment of a bit retention technique or means.
  • a real address is set in the 7th to 23rd bits of the address register 101 of the central processing unit 100.
  • the address information initially sent out by the gate timing signal t1 covers the 0th to 15th bits, and the address information subsequently sent out by the gate timing signal t3 ranges from the 8th to 23rd bits.
  • the 7th bit (one bit of the real address information of the 17-bit configuration) sent out first is latched by the timing signal t2 in a flip-flop 50.
  • the 8th to 14th bits are provided to multiplexer 40, while the 15th to 23rd bits are provided directly to register 302.
  • the 7th bit is combined, by the multiplexer 40, with the 8th to 14th bits sent out during time t3, and the combination is provided during time t4 to register 302, the 15th to 23rd bits sent out during time t3 being provided directly to register 302 during time t4, whereby to access the main memory 300.
  • the 1-bit flip-flop, or the like comprises a bit retaining means.
  • the real address has a 16-bit configuration
  • a bit retaining means such as the flip-flop 50 is unnecessary. That is, the real address information is set in the 8th to 23rd bits of the address register 101, so that the address information subsequently sent out may be set, as it is, in the address register 302 of the main memory 300.
  • FIG. 9 is a detailed logic block diagram of the multiplexer 40.
  • Multiplexer 40 basically comprises AND gates 900 through 915, inverter 916, and OR gates 920 through 927.
  • multiplexer 40 receives a MODE input which, as previously explained, has the value 0 for a virtual memory system and 1 for a real memory system.
  • a virtual memory system AND gates 900 through 907 are disabled, so that the seven bits received from gate 104 are blocked, while AND gates 908 through 915 are enabled so that the eight bits from register 204 are not blocked.
  • the page number in real memory as provided by address conversion part 200 (FIG. 7) is provided via OR gates 920 through 927 as an output of multiplexer 40 to register 302.
  • AND gates 900 through 907 are enabled so as to pass the one bit from flip-flop 50 and the seven bits from gate 104 through multiplexer 40 to register 302; conversely, AND gates 908 through 915 are disabled, thus inhibiting passage of the eight bits from register 204 through multiplexer 40 to register 302.
  • multiplexer 40 passes the 8-bit page number in real memory (from register 204) to address register 302, where it is combined with the address in page (15th through 23rd bits) provided directly to address register 302 by gate 104, the 8th through 14th bits from gate 104 being blocked by disabled AND gates 900 through 907 of multiplexer 40.
  • multiplexer 40 blocks--via AND gates 908 through 915--any output from register 204 from passing therethrough, but passes--via enabled AND gates 900 through 907--the 7th bit from flip-flop 50 and the 8th through 14th bits from gate 104 to the register 302, where they are combined with the 15th through 23rd bits from gate 104 (again provided directly to register 302).
  • FIG. 10 shows a flowchart for the operation of converting a logical address to a real address.
  • the page number of the logical address is set in a page table address register, and a page table is accessed so as to read out a page corresponding to the page number. If the invalid bit of the page is ON, that is, a logic "1", it indicates that the page does not exist in real memory, so that a page fault interrupt occurs, by which the corresponding page is written in real memory from an external memory; at the same time, the page table is updated. When the invalid bit is OFF or a logic "0", the output from the page table and the address in page subsequently sent out are combined to form a real address.
  • a data processing unit using address information larger than the bus width of an address bus it is possible to achieve addressing by making effective use of the address bus and, in this case, means for temporarily holding or retaining a part of the address information need not always be provided. However, if such is provided, it may be of a very small capacity, as described above.
  • the cost of the data processing system can be reduced by omitting the address conversion part and by operating the system only in the real address mode. In that instance, it is sufficient that a mode designating signal is set in a semi-fixed manner by a manual switch, or the like. If the virtual memory system is not to be used in the future, the multiplexer 40 can also be dispensed with.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Executing Machine-Instructions (AREA)
US06/064,725 1977-10-08 1979-08-08 Data processing system Expired - Lifetime US4374410A (en)

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JP12115477A JPS5454536A (en) 1977-10-08 1977-10-08 Data processor
JP52-121154 1977-10-08

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Cited By (24)

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US4541045A (en) * 1981-09-21 1985-09-10 Racal-Milgo, Inc. Microprocessor architecture employing efficient operand and instruction addressing
US4580214A (en) * 1982-03-02 1986-04-01 Hitachi, Ltd. Memory control system
US4602368A (en) * 1983-04-15 1986-07-22 Honeywell Information Systems Inc. Dual validity bit arrays
US4608632A (en) * 1983-08-12 1986-08-26 International Business Machines Corporation Memory paging system in a microcomputer
US4616311A (en) * 1980-10-03 1986-10-07 Tokyo Shibaura Denki Kabushiki Kaisha Data processing system
US4636942A (en) * 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
US4675808A (en) * 1983-08-08 1987-06-23 American Telephone And Telegraph Company At&T Bell Laboratories Multiplexed-address interface for addressing memories of various sizes
US4714993A (en) * 1983-10-18 1987-12-22 International Business Machines Corporation Apparatus and method for effecting dynamic address translation in a microprocessor implemented data processing system
US4745545A (en) * 1985-06-28 1988-05-17 Cray Research, Inc. Memory reference control in a multiprocessor
US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers
US4779191A (en) * 1985-04-12 1988-10-18 Gigamos Systems, Inc. Method and apparatus for expanding the address space of computers
US4901230A (en) * 1983-04-25 1990-02-13 Cray Research, Inc. Computer vector multiprocessing control with multiple access memory and priority conflict resolution method
US5119498A (en) * 1989-06-12 1992-06-02 International Business Machines Corporation Feature board with automatic adjustment to one of two bus widths based on sensing power level at one connection contact
US5142638A (en) * 1989-02-07 1992-08-25 Cray Research, Inc. Apparatus for sharing memory in a multiprocessor system
US5148539A (en) * 1987-10-16 1992-09-15 Hitachi, Ltd. Address bus control apparatus
US5251307A (en) * 1988-07-26 1993-10-05 Kabushiki Kaisha Toshiba Channel apparatus with a function for converting virtual address to real address
US5581734A (en) * 1993-08-02 1996-12-03 International Business Machines Corporation Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
US5845098A (en) * 1996-06-24 1998-12-01 Motorola Inc. Address lines load reduction
US6453400B1 (en) * 1997-09-16 2002-09-17 Nec Corporation Semiconductor integrated circuit device
US20070150641A1 (en) * 2005-12-22 2007-06-28 Sanyo Electric Co., Ltd. Bus Address Selecting Circuit and Bus Address Selecting Method
US20100169528A1 (en) * 2008-12-30 2010-07-01 Amit Kumar Interrupt technicques
US8307105B2 (en) 2008-12-30 2012-11-06 Intel Corporation Message communication techniques
US20150301945A1 (en) * 2004-12-29 2015-10-22 Intel Corporation System and method for one step address translation of graphics addresses in virtualization

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JPS56117024A (en) * 1980-02-19 1981-09-14 Sanyo Electric Co Ltd Flectronic oven
JP4984666B2 (ja) * 2006-06-12 2012-07-25 ソニー株式会社 不揮発性メモリ
US8441707B2 (en) 2009-06-11 2013-05-14 Switch Materials, Inc. Variable transmittance optical filter and uses thereof

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Cited By (29)

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Publication number Priority date Publication date Assignee Title
US4616311A (en) * 1980-10-03 1986-10-07 Tokyo Shibaura Denki Kabushiki Kaisha Data processing system
US4541045A (en) * 1981-09-21 1985-09-10 Racal-Milgo, Inc. Microprocessor architecture employing efficient operand and instruction addressing
US4580214A (en) * 1982-03-02 1986-04-01 Hitachi, Ltd. Memory control system
US4602368A (en) * 1983-04-15 1986-07-22 Honeywell Information Systems Inc. Dual validity bit arrays
US4901230A (en) * 1983-04-25 1990-02-13 Cray Research, Inc. Computer vector multiprocessing control with multiple access memory and priority conflict resolution method
US4636942A (en) * 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
US4675808A (en) * 1983-08-08 1987-06-23 American Telephone And Telegraph Company At&T Bell Laboratories Multiplexed-address interface for addressing memories of various sizes
US4608632A (en) * 1983-08-12 1986-08-26 International Business Machines Corporation Memory paging system in a microcomputer
US4714993A (en) * 1983-10-18 1987-12-22 International Business Machines Corporation Apparatus and method for effecting dynamic address translation in a microprocessor implemented data processing system
US4779191A (en) * 1985-04-12 1988-10-18 Gigamos Systems, Inc. Method and apparatus for expanding the address space of computers
US4745545A (en) * 1985-06-28 1988-05-17 Cray Research, Inc. Memory reference control in a multiprocessor
US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers
US5148539A (en) * 1987-10-16 1992-09-15 Hitachi, Ltd. Address bus control apparatus
US5251307A (en) * 1988-07-26 1993-10-05 Kabushiki Kaisha Toshiba Channel apparatus with a function for converting virtual address to real address
US5142638A (en) * 1989-02-07 1992-08-25 Cray Research, Inc. Apparatus for sharing memory in a multiprocessor system
US5119498A (en) * 1989-06-12 1992-06-02 International Business Machines Corporation Feature board with automatic adjustment to one of two bus widths based on sensing power level at one connection contact
US5581734A (en) * 1993-08-02 1996-12-03 International Business Machines Corporation Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
US5845098A (en) * 1996-06-24 1998-12-01 Motorola Inc. Address lines load reduction
US6453400B1 (en) * 1997-09-16 2002-09-17 Nec Corporation Semiconductor integrated circuit device
US20150301945A1 (en) * 2004-12-29 2015-10-22 Intel Corporation System and method for one step address translation of graphics addresses in virtualization
US10133674B2 (en) * 2004-12-29 2018-11-20 Intel Corporation System and method for one step address translation of graphics addresses in virtualization
US10671541B2 (en) 2004-12-29 2020-06-02 Intel Corporation System and method for one step address translation of graphics addresses in virtualization
US11023385B2 (en) 2004-12-29 2021-06-01 Intel Corporation System and method for one step address translation of graphics addresses in virtualization
US20070150641A1 (en) * 2005-12-22 2007-06-28 Sanyo Electric Co., Ltd. Bus Address Selecting Circuit and Bus Address Selecting Method
US20100169528A1 (en) * 2008-12-30 2010-07-01 Amit Kumar Interrupt technicques
US8307105B2 (en) 2008-12-30 2012-11-06 Intel Corporation Message communication techniques
US8645596B2 (en) * 2008-12-30 2014-02-04 Intel Corporation Interrupt techniques
US8751676B2 (en) 2008-12-30 2014-06-10 Intel Corporation Message communication techniques

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JPS5454536A (en) 1979-04-28
BR7806654A (pt) 1979-05-08
ES473937A1 (es) 1979-05-01
JPS5652386B2 (fr) 1981-12-11

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