US4459741A - Method for producing VLSI complementary MOS field effect transistor circuits - Google Patents

Method for producing VLSI complementary MOS field effect transistor circuits Download PDF

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US4459741A
US4459741A US06/408,788 US40878882A US4459741A US 4459741 A US4459741 A US 4459741A US 40878882 A US40878882 A US 40878882A US 4459741 A US4459741 A US 4459741A
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implantation
regions
occurs
silicon nitride
energy level
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Ulrich Schwabe
Erwin Jacobs
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Siemens AG
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Siemens AG
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H10P30/212—Through-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H10W10/0127—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers using both n-type and p-type impurities, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/07—Guard rings and cmos
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special

Definitions

  • the invention relates to VLSI complementary MOS field effect transistor circuits and somewhat more particularly to an improved method for producing such circuits.
  • CMOS circuits In known methods for manufacturing highly integrated complementary MOS field effect transistor circuits (CMOS circuits), multiple implantations, according to different technologies which are very involved, are employed for defining the various transistor threshold voltages.
  • CMOS circuits complementary MOS field effect transistor circuits
  • the invention provides a method for producing highly integrated complementary MOS field effect transistor circuits (CMOS circuits) in which p- or, respectively n-doped troughs or tubs are generated in a semiconductor substrate for the acceptance of the n- or p-channel transistors of the circuit, into which appropriate dopant element atoms are introduced for defining or setting the various transistor threshold voltages by a multiple ion implantation, with the masking for the individual ion implantations occuring by means of appropriate photoresist structures or silicon oxide structures or silicon nitride structures and in which the manufacture of source/drain and gate regions as well as the formation of the intermediate oxide and track level is undertaken according to known steps of the MOS technology.
  • CMOS circuits complementary MOS field effect transistor circuits
  • the invention provides a technique for preforming a CMOS process in which as few process steps as possible are utilized for manufacturing the desired circuits, but in which, nonetheless, it is guaranteed that the manner of functioning of the respective components of the circuits is not negatively influenced.
  • a surface-wide oxide layer is formed on the substrate surface so as to protect such surface before the surface-wide ion-implantation for producing the n-trough and for doping the p-channel.
  • the semiconductor substrate is either a n-doped silicon oriented in the ⁇ 100> direction and having a resistance ranging from about 10 to about 50 ohm cm, or is a similar epitaxial layer on a n + -doped silicon substrate.
  • the surface-wide implantation of a select ion occurs at a dose level ranging from about 5 ⁇ 10 10 to about 5 ⁇ 10 11 cm -2 and at an energy level ranging from about 25 to about 200 keV.
  • the double boron implantation occurs so that the first boron implantation is at a dose level ranging from about 3 ⁇ 10 12 to about 5 ⁇ 10 13 cm -2 and at an energy level ranging from about 10 to about 35 keV and the second boron implantation is at a dose level ranging from about 1 ⁇ 10 11 to about 2 ⁇ 10 12 cm -2 and at an energy level ranging from about 50 to about 150 keV.
  • the arsenic implantation during step (h) occurs at a dose level ranging from about 5 ⁇ 10 11 to about 1 ⁇ 10 13 cm -2 and at an energy level ranging from about 60 to about 180 keV.
  • the silicon nitride layer is deposited in a thickness ranging from about 60 to about 180 nm.
  • the silicon nitride layer is deposited in a layer thickness of about 120 nm and during the double boron implantation, the first boron implantation occurs at a dose level of about 1 ⁇ 10 13 cm -2 and at an energy level of about 25 keV and the second boron implantation occurs at a dose level of about 8 ⁇ 10 11 cm -2 and at an energy level of about 80 keV.
  • FIGS. 1-6 are partial, elevated, cross-sectional, somewhat schematic views of a circuit undergoing manufacture in accordance with the principles of the invention and illustrates structures attained by the method steps essential to the invention.
  • FIG. 1 is a diagrammatic representation of FIG. 1:
  • a p-trough or tub 5 is produced at the beginning of the process sequence.
  • a n-doped silicon substrate 1 which may be either a n-doped silicon wafer oriented in the ⁇ 100> direction and having a resistance ranging from about 10 to about 50 ohm cm or, as illustrated, a n epitaxial layer 2 on such an oriented n + silicon substrate.
  • the upper surface of the substrate (1 or 2) is provided with a masking oxide 3 having a thickness of about 700 nm and structured with the assistance of a photoresist process (not illustrated).
  • a boron implantation, schematically indicated at 4, for generating the p-trough 5 occurs at a dose and energy level in the range of about 2 ⁇ 10 12 to about 1 ⁇ 10 13 cm -2 and about 25 keV to about 180 keV, respectively.
  • FIG. 2 is a diagrammatic representation of FIG. 1
  • the oxide layer 3 is entirely removed and a scatter oxide layer 6 is grown on the substrate surface (1, 2) in a layer thickness of about 50 nm.
  • a surface-wide ion implantation, schematically indicated at 7, of an ion selected from the group consisting of phosphorus, arsenic or antimony then occurs for generating the p-channel and the n-trough 8.
  • the manufacture of the two troughs 5 and 8 occurs with only one mask, however while avoiding the self-adjusting step (as occurs in certain embodiments of the Parillo et al technique) which is disadvantageous in circuit-technical terms.
  • the n-trough 8 is formed without a separate masking step by means of the surface-wide phosphorus, arsenic or antimony implantation 7 (at a dose level ranging from about 7 ⁇ 10 10 to about 2 ⁇ 10 11 cm -2 and at a energy level ranging from about 25 to about 200 keV, preferably at about 160 keV), with a subsequent diffusion.
  • the disadvantages of a self-adjusting trough production process are thus eliminated.
  • the threshold voltage of p-channel transistor is set with the ion implantation 7, preferably phosphorus or arsenic. In this manner, a masking step is eliminated.
  • a further substantial advantage is that the otherwise standard high dose compensation implantation into the channel region, which would lead to a reduction of the break-through voltage (p-channel transistors), is eliminated.
  • FIG. 3 is a diagrammatic representation of FIG. 3
  • a silicon nitride layer is deposited in a thickness of about 60 to about 180 nm, preferably about 120 nm and structured so as to form a nitride mask 9 (mask LOCOS).
  • FIG. 4 is a diagrammatic representation of FIG. 4
  • the field and channel implantation of the n-channel transistors is carried with only one mask (LOCOS mask 9) and a double boron implantation, schematically indicated at 10a and 10b, then occurs.
  • the thickness of the LOCOS nitride mask 9 is adjusted in such a manner that a first, relatively low energy boron implantation 10a (at a dose level ranging from about 3 ⁇ 10 12 to about 5 ⁇ 10 13 cm -2 and preferably at about 1 ⁇ 10 13 cm -2 and at energy level ranging from about 10 to about 35 keV, and preferably at about 25 keV) is fully masked and only the field regions 11 are implanted.
  • a second, relatively higher energy boron implantation 10b is controlled in such a manner that both the threshold voltage of the n-channel thin-oxide transistors, as well as that of the thick oxide transistors (doubly implanted field regions) are controlled with definition. All regions outside of the p-trough regions 5 are covered with a first photoresist structure 13 (produced with a first photoresist process) just prior to the boron implantations 10a and 10b.
  • FIG. 5 is a diagrammatic representation of FIG. 5
  • a second photoresist structure 14 is formed by a second photoresist process so that all regions outside of the n-trough regions 8 are covered with the second photoresist structures 14.
  • the field implantation 16 of the p-channel transistors now occurs with an implantation of arsenic ions, schematically indicated at 15 (at a dose level ranging from about 5 ⁇ 10 11 to about 1 ⁇ 10 13 cm -2 and at energy level ranging from about 16 to about 180 keV).
  • arsenic ions schematically indicated at 15 (at a dose level ranging from about 5 ⁇ 10 11 to about 1 ⁇ 10 13 cm -2 and at energy level ranging from about 16 to about 180 keV).
  • FIG. 6 is a diagrammatic representation of FIG. 6
  • the field oxide regions 17 are formed in a layer thickness of about 1000 nm by a topical oxidation, with employment of the silicon nitride mask 9. After removal of the nitride mask 9, all further process steps can occur in accordance with known steps of the CMOS technology.

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US06/408,788 1981-08-27 1982-08-17 Method for producing VLSI complementary MOS field effect transistor circuits Expired - Fee Related US4459741A (en)

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DE3133841 1981-08-27
DE19813133841 DE3133841A1 (de) 1981-08-27 1981-08-27 Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen

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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4525920A (en) * 1983-04-21 1985-07-02 Siemens Aktiengesellschaft Method of making CMOS circuits by twin tub process and multiple implantations
US4549340A (en) * 1982-09-24 1985-10-29 Hitachi, Ltd. Method of making CMOS semiconductor device using specially positioned, retained masks, and product formed thereby
US4554726A (en) * 1984-04-17 1985-11-26 At&T Bell Laboratories CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well
US4562638A (en) * 1983-11-09 1986-01-07 Siemens Aktiengesellschaft Method for the simultaneous manufacture of fast short channel and voltage-stable MOS transistors in VLSI circuits
US4656730A (en) * 1984-11-23 1987-04-14 American Telephone And Telegraph Company, At&T Bell Laboratories Method for fabricating CMOS devices
WO1987005443A1 (en) * 1986-03-04 1987-09-11 Motorola, Inc. High/low doping profile for twin well process
US4717686A (en) * 1985-06-03 1988-01-05 Siemens Aktiengesellschaft Method for the simultaneous manufacture of bipolar and complementary MOS transistors on a common silicon substrate
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
US4806501A (en) * 1986-07-23 1989-02-21 Sgs Microelettronica S.P.A. Method for making twin tub CMOS devices
US4855245A (en) * 1985-09-13 1989-08-08 Siemens Aktiengesellschaft Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate
US4889825A (en) * 1986-03-04 1989-12-26 Motorola, Inc. High/low doping profile for twin well process
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate
US4987088A (en) * 1988-07-29 1991-01-22 Sgs-Thomson Microelectronics S.R.L. Fabrication of CMOS devices with reduced gate length
DE4107149A1 (de) * 1990-03-09 1991-09-12 Gold Star Electronics Blockierverfahren beim implantieren von hochenergetischen ionen unter verwendung eines nitridfilms
US5212111A (en) * 1992-04-22 1993-05-18 Micron Technology, Inc. Local-oxidation of silicon (LOCOS) process using ceramic barrier layer
US5482878A (en) * 1994-04-04 1996-01-09 Motorola, Inc. Method for fabricating insulated gate field effect transistor having subthreshold swing
US5525535A (en) * 1995-07-26 1996-06-11 United Microelectronics Corporation Method for making doped well and field regions on semiconductor substrates for field effect transistors using liquid phase deposition of oxides
US5831310A (en) * 1995-05-24 1998-11-03 Nec Corporation Semiconductor device for checking quality of a semiconductor region

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WO1985004525A1 (en) * 1984-03-29 1985-10-10 Hughes Aircraft Company A latch-up resistant cmos structure for vlsi
US4558508A (en) * 1984-10-15 1985-12-17 International Business Machines Corporation Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step
KR900005354B1 (ko) * 1987-12-31 1990-07-27 삼성전자 주식회사 Hct 반도체 장치의 제조방법
US5206535A (en) * 1988-03-24 1993-04-27 Seiko Epson Corporation Semiconductor device structure
KR940003218B1 (ko) * 1988-03-24 1994-04-16 세이꼬 엡슨 가부시끼가이샤 반도체 장치 및 그 제조방법
NL8802219A (nl) * 1988-09-09 1990-04-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin door ionenimplantaties halfgeleidergebieden worden gevormd.
JP2504567B2 (ja) * 1989-06-14 1996-06-05 株式会社東芝 半導体装置の製造方法
US5218224A (en) * 1989-06-14 1993-06-08 Kabushiki Kaisha Toshiba Semiconductor device including inversion preventing layers having a plurality of impurity concentration peaks in direction of depth
DE4404757C2 (de) * 1994-02-15 1998-08-20 Siemens Ag Verfahren zur Herstellung eines einem Graben benachbarten Diffusionsgebietes in einem Substrat

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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4549340A (en) * 1982-09-24 1985-10-29 Hitachi, Ltd. Method of making CMOS semiconductor device using specially positioned, retained masks, and product formed thereby
US4525920A (en) * 1983-04-21 1985-07-02 Siemens Aktiengesellschaft Method of making CMOS circuits by twin tub process and multiple implantations
US4562638A (en) * 1983-11-09 1986-01-07 Siemens Aktiengesellschaft Method for the simultaneous manufacture of fast short channel and voltage-stable MOS transistors in VLSI circuits
US4554726A (en) * 1984-04-17 1985-11-26 At&T Bell Laboratories CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well
US4656730A (en) * 1984-11-23 1987-04-14 American Telephone And Telegraph Company, At&T Bell Laboratories Method for fabricating CMOS devices
US4717686A (en) * 1985-06-03 1988-01-05 Siemens Aktiengesellschaft Method for the simultaneous manufacture of bipolar and complementary MOS transistors on a common silicon substrate
US4855245A (en) * 1985-09-13 1989-08-08 Siemens Aktiengesellschaft Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate
WO1987005443A1 (en) * 1986-03-04 1987-09-11 Motorola, Inc. High/low doping profile for twin well process
US4889825A (en) * 1986-03-04 1989-12-26 Motorola, Inc. High/low doping profile for twin well process
US4806501A (en) * 1986-07-23 1989-02-21 Sgs Microelettronica S.P.A. Method for making twin tub CMOS devices
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DE3133841A1 (de) 1983-03-17
ATE27751T1 (de) 1987-06-15
CA1187210A (en) 1985-05-14
JPS5843563A (ja) 1983-03-14
EP0073942B1 (de) 1987-06-10
EP0073942A2 (de) 1983-03-16
EP0073942A3 (en) 1984-10-17
DE3276558D1 (en) 1987-07-16

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