US4467420A - One-chip microcomputer - Google Patents

One-chip microcomputer Download PDF

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Publication number
US4467420A
US4467420A US06/359,818 US35981882A US4467420A US 4467420 A US4467420 A US 4467420A US 35981882 A US35981882 A US 35981882A US 4467420 A US4467420 A US 4467420A
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United States
Prior art keywords
processing unit
central processing
data
operatively connected
random
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Expired - Lifetime
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US06/359,818
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English (en)
Inventor
Jyoji Murakami
Tsuyoshi Watanabe
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Fujitsu Ltd
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Fujitsu Ltd
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Priority claimed from JP56040801A external-priority patent/JPS57155656A/ja
Priority claimed from JP56043503A external-priority patent/JPS6024980B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Assigned to FUJITSU LIMITED; A CORP. OF JAPAN reassignment FUJITSU LIMITED; A CORP. OF JAPAN ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: MURAKAMI, JYOJI, WATANABE, TSUYOSHI
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/786—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers) using a single memory module

Definitions

  • the present invention relates to a one-chip microcomputer.
  • a 4-bit microprocessor such as Intel 4004, which was also called a microcomputer, comprised a central processing unit (abbreviated CPU) on a single chip.
  • CPU central processing unit
  • LSI Large Scale Integration
  • a one-chip microcomputer generally comprises a CPU, a random-access memory (abbreviated RAM), a read-only memory (abbreviated ROM), input/output (abbreviated I/O) ports, a clock generator and the like on a single chip.
  • a one-chip microcomputer has full computer functions on a single chip and, accordingly, cost-performance thereof can be greatly improved.
  • DMA direct memory access
  • a one-chip microcomputer comprising: a central processing unit (CPU) having arithmetic, logic and control units; a random-access memory (RAM) for storing intermediate data and instructions processed by the central processing unit; an output buffer register for storing first data processed by the central processing unit; a direct memory access controller (DMAC), controlled by the central processing unit, for reading second data from a predetermined area of the random-access memory; port means for receiving the first data from the output buffer register and the second data of the random-access memory read by the direct memory access controller; terminals connected to the port means and used commonly during a CPU operation mode and a DMA operation mode; and time-division means, controlled by the direct memory access controller, for transmitting the first and second data through the port means to the terminals.
  • CPU central processing unit
  • RAM random-access memory
  • DMAC direct memory access controller
  • a one-chip microcomputer comprising: a central processing unit (CPU) having arithmetic, logic and control units; a random-access memory (RAM) for storing intermediate data and instructions processed by the central processing unit; an output buffer register for storing first data processed by the central processing unit; a direct memory access controller (DMAC) controlled by the central processing unit; gate means controlled by the central processing unit; address port means for transmitting an externally applied address signal to the random-access memory through the gate means so as to read second data from the random-access memory; a port means for receiving the first data from the output buffer register and the second data of the random-access memory read by the address port means; terminals connected to the port means and used commonly during a CPU operation mode and a DMA operation mode; and time-division means, controlled by the direct memory access controller, for transmitting the first and second data through the port means to the terminals.
  • CPU central processing unit
  • RAM random-access memory
  • DMAC direct memory access controller
  • a one-chip microcomputer comprising: a central processing unit (CPU) having arithmetic, logic and control units; a random-access memory (RAM) for storing intermediate data and instructions processed by the central processing unit; a register for storing the same data as that of a predetermined area of the random-access memory, the write operation upon the register and the predetermined area of the random-access memory being simultaneously performed by the central processing unit; a direct memory access controller (DMAC) controlled by the central processing unit; parallel-serial converter means, controlled by the central processing unit, for converting parallel data into serial data, the parallel data being sent from the register by the direct memory access controller; and a terminal connected to the parallel-serial converter means and used commonly during a CPU operation mode and a DMA operation mode.
  • CPU central processing unit
  • RAM random-access memory
  • register for storing the same data as that of a predetermined area of the random-access memory, the write operation upon the register and the predetermined area of the random-access memory being simultaneously performed by the central processing unit
  • a one-chip microcomputer comprising: a central processing unit (CPU) having arithmetic, logic and control units; a random-access memory (RAM) for storing intermediate data and instructions processed by the central processing unit; a direct memory access controller (DMAC) controlled by the central processing unit; an address counter, controlled by the direct memory access controller, for generating an address signal so as to read data from the random-access memory; parallel-serial converter means, controlled by the central processing unit, for converting parallel data into serial data, the data of the random-access memory accessed by the address counter being set in the parallel-serial converter means; and a terminal connected to the parallel-serial converter means and used commonly during a CPU operation mode and a DMA operation mode.
  • CPU central processing unit
  • RAM random-access memory
  • DMAC direct memory access controller
  • FIG. 1 is a block diagram of a first embodiment of a one-chip microcomputer according to the present invention
  • FIGS. 2A and 2B are timing diagrams of signals appearing in the circuit of FIG. 1;
  • FIG. 3 is a block diagram of a second embodiment of the one-chip microcomputer according to the present invention.
  • FIGS. 4A through 4C are timing diagrams of signals appearing in the circuit of FIG. 3;
  • FIG. 5 is a block diagram of a third embodiment of the one-chip microcomputer according to the present invention.
  • FIGS. 6A through 6J are timing diagrams of the signals appearing in the circuit of FIG. 5;
  • FIG. 7 is a block diagram of a fourth embodiment of the one-chip microcomputer according to the present invention.
  • FIG. 8 is a block diagram of a fifth embodiment of the one-chip microcomputer according to the present invention.
  • FIG. 1 is a first embodiment of the one-chip microcomputer according to the present invention
  • 1 is a central processing unit (CPU) having arithmetic, logic and control units
  • 2 is a direct memory access controller (DMAC) which is set by the CPU 1
  • 3 is a random-access memory (RAM) for storing intermediate data and instructions processed by the CPU 1
  • 4 is a output buffer register for storing output data processed by the CPU 1
  • 5 is a time-division control circuit controlled by the DMAC 2
  • 6-0, 6-1, . . . , 6-7 are I/O ports
  • 7 is a data bus
  • 8 is an address bus.
  • the RAM 3 has a data bus 9 for a direct memory access (DMA) operation mode. All the elements of FIG. 1 are formed on a single semiconductor chip.
  • DMA direct memory access
  • output data (which is referred to as CPU output data) is stored in the output buffer register 4 and, after that, the CPU output data is transferred through the ports 6-0, 6-1, . . . , 6-7 and terminals P 0 , P 1 , . . . , P 7 to the exterior.
  • output data (which is referred to as DMA output data) is read out of a predetermined area of the RAM 3 to the DMA data bus 9 by the DMAC 2.
  • the predetermined area is comprised of one word or eight bits.
  • the DMA output data is also transferred through the ports 6-0, 6-1, . . . , 6-7 and the terminals P 0 , P 1 , . . . , P 7 to the exterior.
  • Time-division control for this type of output data is performed by the time-division control circuit 5 which is also controlled by the DMAC 2.
  • the time-division control circuit 5, which is controlled by the DMAC 2, generates a clock signal T 1 as illustrated in FIG. 2A, its inverted signal T 1 and a clock signal T 2 is illustrated in FIG. 2B.
  • the difference in phase between the clock signals T 1 and T 2 is about 90 degrees.
  • Such clock signals T 1 and T 2 can be easily formed by using a reference signal of a reference clock generator and frequency dividers (not shown).
  • each of the ports 6-0, 6-1, . . . , 6-7 comprise two AND gates G 1 and G 2 , and an OR gate G 3 .
  • Each gate G 1 transmits the CPU output data from the output buffer register 4 to the exterior when the potential of the clock signal T 1 is high, while each gate G 2 transmits the DMA output data from the RAM 3 to the exterior when the potential of the clock signal T 1 is high.
  • the CPU output data and the DMA output data are alternately transmitted through the ports 6-0, 6-1, . . . , 6-7 and the terminals P 0 , P 1 , . . . , P 7 to the exterior.
  • the read operation timing of the DMAC 2 for the RAM 3 is in synchronization with the high potential of the clock signal T 1 .
  • FIG. 3 is a block diagram illustrating a second embodiment of the one-chip microcomputer according to the present invention.
  • an address counter 10 a DMA address bus 11, an OR gate 12 and a NOR gate 13 are added to FIG. 1.
  • the time-division control circuit 5 generates an inverted signal T 2 of the clock signal T 2 for a terminal P 9 .
  • the DMAC 2 increases the count of the address counter 10 which generates an address signal for the DMA address bus 11. Therefore, a plurality of words which serve as the DMA data are read out of the RAM 3 to the DMA data bus 9. For example, if the address counter 10 comprises 4 bits, eight words allocated by addresses "0", “1", "2", . . . , "7" can be read out from the RAM 3.
  • the CPU data and the DMA data are alternately transmitted through the ports 6-0, 6-1, . . . , 6-7 to the terminals P 0 , P 1 , . . . , P 7 , in the same way as in FIG. 1. In this case, however, it is necessary to know the address of a DMA output data (word) transmitted at the terminals P 0 , P 1 , . . . , P 7 . For this purpose, a terminal P 9 is provided.
  • the output potential T 3 of the NOR gate 13 is high only when the potential of each of the signals T 1 and T 2 and the value of the address counter 10 is "0". Therefore, the value of the address counter 10 can be read by providing an appropriate external counter (now shown). That is, the external counter is reset by the rise of the potential T 3 at the terminal P 9 and increases by one count based on the rise of the potential T 2 .
  • FIG. 5 is a block diagram illustrating a third embodiment of the one-chip microcomputer according to the present invention.
  • terminals P 11 through P 19 an address port 14, the gates G 11 through G 19 are provided to access the RAM 3 directly from the exterior during the DMA operation mode.
  • Each of the ports 6-0, 6-1, . . . , 6-7, which comprise six gates G 1 through G 6 is bidirectional.
  • the bidirectional I/O ports 6-0, 6-1, . . . , 6-7 are connected to a DMA write data bus 15.
  • D-type flip-flops 16 and 17, and an AND gate 18 are provided for a permission signal T 7 , which permits a DMA read or write operation.
  • the flip-flop 16 inputs the potential of signal T 4 , as illustrated in FIG. 6D, which is generated by the CPU 1. As a result, the flip-flop 16 generates a signal T 5 , as illustrated in FIG. 6E. Further, by the rise of the potential of the signal T 1 as illustrated in FIG. 6B, the flip-flop 17 stores the signal T 5 , and, accordingly, the flip-flop 17 generates a signal T 6 , as illustrated in FIG. 6F. Therefore, the permission signal T 7 generated from the AND gate 18, which receives the signals T 1 and T 6 , is illustrated in FIG. 6G.
  • the potential of each of the signals T 4 and T 7 is low and high, respectively.
  • the gates G 11 through G 19 are opened so that the address port 14 accesses the RAM 3 by supplying an externally-applied address signal.
  • the potential of a read/write signal R/W applied to a terminal P 10 is caused to be high, so as to open gate G 4 of each port 6-0, 6-1, . . . , 6-7.
  • the ports 6-0, 6-1, . . . , 6-7 transmit the DMA data from the RAM 3 to the exterior.
  • the CPU data is transmitted from the output buffer register 4 through the ports 6-0, 6-1, . . . , 6-7 to the exterior.
  • This type of data that is, DMA data and CPU data, can be discriminated between by the signal T 2 obtained at the terminal P 8 , as illustrated in FIG. 6C.
  • DMA read mode when address signals A, B, . . . are supplied to the address port 14, as illustrated in FIG. 6H, DMA read data RA, RB, . . . are obtained at the terminal P 0 through P 7 , as illustrated in FIG. 6I.
  • FIG. 7 is a block diagram illustrating a fourth embodiment of the one-chip microcomputer according to the present invention.
  • 21 is a resister for storing the same data as that of a predetermined area of the RAM 3. That is, when the CPU 1 performs a write operation upon the predetermined area of the RAM 3, the CPU 1 also performs the same write operation upon the register 21. Therefore, the data of the register 21 is always the same as that of the predetermined area of the RAM 3.
  • the DMAC 2 which is set by the CPU 1, transmits the contents of the register 21 to a shift register 22.
  • a shift clock signal generated from a clock generator (not shown) is supplied to the shift register 22, so that the shift operation is performed upon the shift register 22. Therefore, the parallel data stored in the register 21 is converted into serial data which is transmitted through a terminal P 21 to the exterior.
  • the above-mentioned predetermined area of the RAM 3 comprises a word (8 bits) allocated to one address.
  • the predetermined area can comprise at least one predetermined bit (i.e., a bit slice) of predetermined data words which are, for example, allocated by addresses "0", "1", . . . , "7".
  • FIG. 8 is a block diagram illustrating a fifth embodiment of the one-chip microcomputer according to the present invention.
  • an address counter 24 is provided instead of the register 21 of FIG. 7. That is, the DMAC 2 increases the count of the address counter 24, so that one word data (8 bits) is read out of the RAM 3 into the shift register 22.
  • a shift clock signal generated from a clock signal generator (not shown) is supplied to the shift register 22, so that the shift operation is performed on the shift register 22, in the same way as in FIG. 7.
  • the address counter 10 comprises 4 bits, eight words allocated by the addresses "0", "1", . . . , "7" can be read out of the RAM 3 to the shift register 22.
  • the DMAC 2 includes division means similar to those used in the previous examples to control, via the CPU 1, whether the first data is fed from the serial input/output circuit 23 to the shift register 22 or the second data is fed from the register 21 (or the RAM 3) to the shift register 22.
  • the present invention has an advantage in that direct data transfer between the RAM and the exterior can take place without increasing the number of terminals.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
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US06/359,818 1981-03-20 1982-03-19 One-chip microcomputer Expired - Lifetime US4467420A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP56-40801 1981-03-20
JP56040801A JPS57155656A (en) 1981-03-20 1981-03-20 One-chip microcomputer
JP56043503A JPS6024980B2 (ja) 1981-03-25 1981-03-25 マイクロコンピユ−タ
JP56-43503 1981-03-25

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Cited By (18)

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Publication number Priority date Publication date Assignee Title
US4680698A (en) * 1982-11-26 1987-07-14 Inmos Limited High density ROM in separate isolation well on single with chip
US4833620A (en) * 1985-03-08 1989-05-23 Fujitsu Limited Method for fabricating a 1-chip microcomputer
US5005121A (en) * 1985-03-25 1991-04-02 Hitachi, Ltd. Integrated CPU and DMA with shared executing unit
US5060134A (en) * 1988-05-12 1991-10-22 Motorola, Inc. Action direction port expansion circuit and system
US5228139A (en) * 1988-04-19 1993-07-13 Hitachi Ltd. Semiconductor integrated circuit device with test mode for testing CPU using external signal
US5452467A (en) * 1982-11-26 1995-09-19 Inmos Limited Microcomputer with high density ram in separate isolation well on single chip
US5493686A (en) * 1985-08-23 1996-02-20 Hitachi, Ltd. Data processor in which external sync signal may be selectively inhibited
US5513374A (en) * 1993-09-27 1996-04-30 Hitachi America, Inc. On-chip interface and DMA controller with interrupt functions for digital signal processor
US5535417A (en) * 1993-09-27 1996-07-09 Hitachi America, Inc. On-chip DMA controller with host computer interface employing boot sequencing and address generation schemes
US5625796A (en) * 1989-10-02 1997-04-29 Motorola, Inc. Method and apparatus for concurrently accessing multiple memories with different timing requirements
US5829015A (en) * 1996-09-05 1998-10-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device having multi-port RAM memory with random logic portion which can be tested without additional test circuitry
US5892976A (en) * 1989-11-03 1999-04-06 Compaq Computer Corporation System for parallel port with direct memory access controller for developing signal to indicate packet available and receiving signal that packet has been accepted
GB2344184A (en) * 1998-11-26 2000-05-31 Ericsson Telefon Ab L M Testing integrated circuits
US6108765A (en) 1982-02-22 2000-08-22 Texas Instruments Incorporated Device for digital signal processing
US6408346B1 (en) * 1989-11-03 2002-06-18 Compaq Computer Corporation System for communicating with an external device using a parallel port with DMA capabilities and for developing a signal to indicate the availability of data
US6414368B1 (en) 1982-11-26 2002-07-02 Stmicroelectronics Limited Microcomputer with high density RAM on single chip
US20040064606A1 (en) * 2002-09-26 2004-04-01 Mitsubishi Denki Kabushi Kaisha Memory system allowing fast operation of processor while using flash memory incapable of random access
US20040133729A1 (en) * 1987-12-14 2004-07-08 Intel Corporation. Memory component with synchronous data transfer

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JPH0738187B2 (ja) * 1984-03-23 1995-04-26 株式会社日立製作所 Ｌｓｉに構成されたマイクロコンピュータ
JPS6155747A (ja) 1984-08-28 1986-03-20 Toshiba Corp デ−タ転送制御回路を備えたデイジタル集積回路
JPH03156554A (ja) * 1989-11-14 1991-07-04 Hitachi Ltd データ転送制御方式
US6467009B1 (en) * 1998-10-14 2002-10-15 Triscend Corporation Configurable processor system unit
US6851047B1 (en) 1999-10-15 2005-02-01 Xilinx, Inc. Configuration in a configurable system on a chip
US6721840B1 (en) 2000-08-18 2004-04-13 Triscend Corporation Method and system for interfacing an integrated circuit to synchronous dynamic memory and static memory
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CN112416665B (zh) * 2019-08-20 2024-05-03 北京地平线机器人技术研发有限公司 检测处理器运行状态的装置和方法
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Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6108765A (en) 1982-02-22 2000-08-22 Texas Instruments Incorporated Device for digital signal processing
US5031092A (en) * 1982-11-26 1991-07-09 Inmos Limited Microcomputer with high density ram in separate isolation well on single chip
US4680698A (en) * 1982-11-26 1987-07-14 Inmos Limited High density ROM in separate isolation well on single with chip
US5452467A (en) * 1982-11-26 1995-09-19 Inmos Limited Microcomputer with high density ram in separate isolation well on single chip
US5491359A (en) * 1982-11-26 1996-02-13 Inmos Limited Microcomputer with high density ram in separate isolation well on single chip
US5506437A (en) * 1982-11-26 1996-04-09 Inmos Limited Microcomputer with high density RAM in separate isolation well on single chip
US6414368B1 (en) 1982-11-26 2002-07-02 Stmicroelectronics Limited Microcomputer with high density RAM on single chip
US4833620A (en) * 1985-03-08 1989-05-23 Fujitsu Limited Method for fabricating a 1-chip microcomputer
US5005121A (en) * 1985-03-25 1991-04-02 Hitachi, Ltd. Integrated CPU and DMA with shared executing unit
US5493686A (en) * 1985-08-23 1996-02-20 Hitachi, Ltd. Data processor in which external sync signal may be selectively inhibited
US20040139285A1 (en) * 1987-12-14 2004-07-15 Intel Corporation Memory component with multiple transfer formats
US20040133729A1 (en) * 1987-12-14 2004-07-08 Intel Corporation. Memory component with synchronous data transfer
US5581698A (en) * 1988-04-19 1996-12-03 Hitachi, Ltd. Semiconductor integrated circuit device with test mode for testing CPU using external Signal
US5228139A (en) * 1988-04-19 1993-07-13 Hitachi Ltd. Semiconductor integrated circuit device with test mode for testing CPU using external signal
US5060134A (en) * 1988-05-12 1991-10-22 Motorola, Inc. Action direction port expansion circuit and system
US5625796A (en) * 1989-10-02 1997-04-29 Motorola, Inc. Method and apparatus for concurrently accessing multiple memories with different timing requirements
US5892976A (en) * 1989-11-03 1999-04-06 Compaq Computer Corporation System for parallel port with direct memory access controller for developing signal to indicate packet available and receiving signal that packet has been accepted
US7103764B2 (en) 1989-11-03 2006-09-05 Hewlett-Packard Development Company, L.P. Parallel port with direct memory access capabilities
US6408346B1 (en) * 1989-11-03 2002-06-18 Compaq Computer Corporation System for communicating with an external device using a parallel port with DMA capabilities and for developing a signal to indicate the availability of data
US20040267970A1 (en) * 1989-11-03 2004-12-30 Jirgal James J. Parallel port with direct memory access capabilities
US6772238B2 (en) 1989-11-03 2004-08-03 Hewlett-Packard Development Company, L.P. Parallel port with direct memory access capabilities
US5535417A (en) * 1993-09-27 1996-07-09 Hitachi America, Inc. On-chip DMA controller with host computer interface employing boot sequencing and address generation schemes
US5513374A (en) * 1993-09-27 1996-04-30 Hitachi America, Inc. On-chip interface and DMA controller with interrupt functions for digital signal processor
US5829015A (en) * 1996-09-05 1998-10-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device having multi-port RAM memory with random logic portion which can be tested without additional test circuitry
US6445205B1 (en) 1998-11-26 2002-09-03 Telefonaktiebolaget Lm Ericsson Method of testing integrated circuits
GB2344184A (en) * 1998-11-26 2000-05-31 Ericsson Telefon Ab L M Testing integrated circuits
US20040064606A1 (en) * 2002-09-26 2004-04-01 Mitsubishi Denki Kabushi Kaisha Memory system allowing fast operation of processor while using flash memory incapable of random access
US6810444B2 (en) * 2002-09-26 2004-10-26 Renesas Technology Corp. Memory system allowing fast operation of processor while using flash memory incapable of random access

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