US4862241A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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Publication number
US4862241A
US4862241A US07/807,831 US80783185A US4862241A US 4862241 A US4862241 A US 4862241A US 80783185 A US80783185 A US 80783185A US 4862241 A US4862241 A US 4862241A
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Prior art keywords
field effect
source
effect transistor
elementary
channel mos
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US07/807,831
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US5205611A (en
Inventor
Yasuhiro Ashida
Shigeki Yokota
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Assigned to SANYO ELECTRIC CO., LTD., 18 KEIHANHONDORI 2-CHOME, MORIGUCHI-SHI, OSAKA-FU, JAPAN reassignment SANYO ELECTRIC CO., LTD., 18 KEIHANHONDORI 2-CHOME, MORIGUCHI-SHI, OSAKA-FU, JAPAN ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: ASHIDA, YASUHIRO, YOKOTA, SHIGEKI
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Definitions

  • the present invention relates to a semiconductor integrated circuit device of the type manufactured by a master slice method. More specifically, the present invention relates to an MOS type large scale integration of a gate array.
  • An example of a semiconductor integrated circuit device of a master slice method is disclosed in, for example, Japanese Utility Model Publication Gazette No. 44592/1983, wherein an aggregation of elementary units each normally including an elementary circuit including a plurality of transistors and resistors is first formed in on a mass production basis in a single semiconductor piece or chip, and a connection mask is later fabricated depending on a line of products to be developed, so that any necessary transistors and resistors may be interconnected to provide a large scale integration having a desired electrical circuitry operation.
  • an object of the present invention is to
  • a semiconductor integrated circuit device of a master slice type wherein a circuit requiring resistive elements such as a RC delay circuit, a circuit for decreasing a DC current and so on is realized without an increase in a chip area and without decreasing the number of transistors that can be contained therein.
  • One aspect of the present invention comprises a semiconductor integrated circuit device of a master slice type including an arrangement of a plurality of elementary units, wherein field effect transistors are formed with the source-drain regions thereof formed by a diffusion region of desired elementary units, while resistive elements are formed by selectively connecting arbitrary diffusion regions of the diffusion regions of the other elementary units.
  • Another aspect of the present invention comprises a semiconductor integrated circuit device of a master slice type, wherein field effect transistors are formed with the gate electrodes formed by an electrode of desired elementary units, while resistive elements are formed by selectively connecting arbitrary electrodes of the electrodes of the other elementary units.
  • the present invention enables reduction in chip area and an increase of the number of transistors in case a given chip area in a semiconductor integrated circuit device of a master slice method.
  • FIG. 1 is a schematic diagram of an inverter taken by way of an example of a circuit in which the present invention can be employed;
  • FIG. 2 is a view showing a pattern of a major portion of first embodiment of the present invention implementing the inverter shown in FIG. 1;
  • FIG. 3 is a view showing a pattern of a major portion of second embodiment implementing the inverter shown in FIG. 1.
  • a complementary metal-oxide inverter circuit employing a combination of P channel MOS transistors and N channel MOS transistors will be described as an example.
  • the present invention can be applied also to other types of integrated circuits, such as an integrated circuit employing bipolar technology of such as TTL's, ECL's and the like.
  • FIG. 1 is a schematic diagram of a complementary inverter comprising a P channel MOS field effect transistor 1 and N channel MOS field effect transistor 2.
  • the inverter shown in FIG. 1 further comprises resistors 3 and 4 inserted between a voltage source V DD and the source of the P channel MOS field effect transistor 1 and between the source of the N channel MOS field effect transistor 2 and the ground V SS , respectively, so that the voltages between the gates and sources of the respective field effect transistors 1 and 2 may be dropped and voltage references may be caused between the ground and the sources, thereby to increase the threshold values of the respective field effect transistors 1 and 2 thorough a backgate effect, thereby to suppress a current flowing through the inverter.
  • FIG. 2 shows a view of the first embodiment of the inventive gate array implementing the above described inverter.
  • FIG. 2 shows a pattern diagram of the embodiment shown in FIG. 2 comprising the resistors 3 and 4 shown in FIG. 1 implemented with the respective source/drain regions of a P channel MOS field effect transistor 6 and an N channel MOS field effect transistor 7 of an elementary unit 5 and the respective MOS field effect transistors 1 and 2 shown in FIG. 1 implemented with an elementary unit 8 formed adjacent thereto.
  • the reference numerals 9, 10 and 11 denote three P type diffusion regions inherently constituting a source region or a drain region of the P channel MOS field effect transistor 6, one of which is to be paired with another one.
  • the pared diffusion of regions are connected in series with a metallic connection 12 of aluminum or the like (shown by a dotted line) and contacts 13 (shown) by a symbol of a letter x in a square to from the resistor 3.
  • the reference numerals 14, 15 and 16 denote three N type diffusion regions inherently constituting a source region or a drain region of the N channel MOS field effect transistor one of which is 7 to be paired with another one, wherein these are connected in series with a metallic connection 12 of aluminum shown by dotted lines and a contact 13 (shown by a symbol of a letter X in a square) to form the resistor 4.
  • one end of the above described resistor 3 in the elementary unit 5 is connected to the voltage source V DD and the other end of the resistor 3 is connected to the source region S of the P channel MOS field effect transistor 1 in the elementary unit 8, while the drain region D of the field effect transistor 1 is connected to the drain region D of the N channel MOS field effect transistor 2 and, furthermore, the source region S of the field effect transistor 2 is connected to one end of the above described resistor 4 in the elementary unit 5, while the other end of the resistor 4 is connected to the ground V SS .
  • the input signal line V IN in the elementary unit 8 is connected to the gate electrodes G and G of both field effect transistor 1 and 2 and the output signal line V OUT is connected to the drain region D of one field effect transistor 1 and the drain region D of the other field effect transistor 2.
  • the respective gate electrodes of the elementary unit 5 constituting the resistors 3 and 4 are connected such that the gate electrode of the P channel field effect transistor 6 is connected to the voltage source V DD and the gate electrode of the N channel field effect transistor 7 is connected to the ground V SS , respectively, thereby to render the respective field effect transistors 6 and 7 in an off state and to separate the respective regions 9, 10 and 11 and the regions 14, 15 and 16.
  • the respective P type diffusion regions 9, 10 and 11 of the P channel MOS field effect transistor 6 are formed through diffusion of boron at 8 ⁇ 10 19 /cm 3 , wherein the resistance value in case where the sizes of the respective regions 9, 10 and 11 are 37 ⁇ m ⁇ 7 ⁇ m are 600 ⁇ and the resistance value of the resistor 3 in case of series connection is 1800 ⁇ .
  • the respective N type diffusion regions 14, 15 and 16 of the N channel MOS field effect transistor 7 are formed through diffusion of phosphorus at 1 ⁇ 10 20 cm 3 and the resistance values in case of the same sizes of the above described regions 9, 10 and 11 as above are 200 ⁇ and resistance value of the resistor 4 in such series connection is 600 ⁇ .
  • FIG. 3 shows the second embodiment of the inventive gate array implementing the inverter shown in FIG. 1.
  • FIG. 3 shows a pattern diagram of the second embodiment comprising the resistors 3 and 4 shown in FIG. 1 implemented with the gate electrodes of the P channel MOS field effect transistor 6 and the N channel MOS field effect transistor 7 of the elementary unit 5 and the respective field effect transistors 1 and 2 formed with the elementary unit 8 in the same manner as that of the above described embodiment shown in FIG. 1.
  • the reference numerals 17 and 18 denote polysilicon layers inherently constituting the gate electrode of the P channel MOS field effect transistor 6 to be layered with another one, wherein these are series connected with a metallic connection 12 of aluminum shown with the dotted line and a contact 13 shown by a symbol of a letter x in a square, thereby to form the resistor 3.
  • the reference numerals 19 and 20 likewise denote polysilicon layers of the gate electrode of the N channel MOS field effect transistor 7, wherein these are series connected to form the resistor 4.
  • the polysilicon layers 17 and 18 and 19 and 20 of the gate electrodes are employed in place of the diffusion regions 9, 10 and 11 and 14, 15 and 16 in case of the first embodiment shown in FIG. 2, wherein the resistance values of the respective polysilicon layers 17 to 20 are 500 ⁇ when the same is formed through doping of phosphorus at 1 ⁇ 10 20 /cm 3 and the sizes thereof are 3 ⁇ m ⁇ 40 ⁇ m, so that the respective resistors 3 and 4 exhibit the resistance value of 1000 ⁇ .
  • the respective diffusion regions of the elementary unit 5 forming the resistors 3 and 4 are connected such that the P type diffusion region is connected to the voltage source V DD and the N type diffusion region is connected to the ground V SS , thereby to keep them in the same potential.

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  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
US07/807,831 1984-12-18 1985-12-11 Semiconductor integrated circuit device Expired - Lifetime US4862241A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59266712A JPH0638468B2 (ja) 1984-12-18 1984-12-18 半導体集積回路装置
JP59-266712 1984-12-18

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JP (1) JPH0638468B2 (ja)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5124778A (en) * 1989-09-29 1992-06-23 Nec Corporation CMOS semiconductor integrated circuit device
US5136356A (en) * 1989-04-19 1992-08-04 Seiko Epson Corporation Semiconductor device
US5146113A (en) * 1990-03-09 1992-09-08 Fujitsu Limited Semiconductor integrated circuit having an oriented resistance pattern
US5175604A (en) * 1985-11-15 1992-12-29 Kabushiki Kaisha Toshiba Field-effect transistor device
US5225693A (en) * 1990-02-09 1993-07-06 Sony Corporation Cmos gate array configured as a sram with load resistors over gate electrodes
WO1995019649A1 (en) * 1994-01-12 1995-07-20 Micrel, Inc. High value gate leakage resistor
US5474948A (en) * 1990-10-22 1995-12-12 Nec Corporation Method of making semiconductor device having polysilicon resistance element
US5949098A (en) * 1995-06-15 1999-09-07 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit having an improved arrangement of power supply lines to reduce noise occurring therein
US5998842A (en) * 1995-07-24 1999-12-07 Ricoh Company, Ltd. Semiconductor device with gate and control electrodes that provide independent control of drain current
US6218703B1 (en) 1995-07-23 2001-04-17 Ricoh Company, Ltd. Semiconductor device with control electrodes formed from semiconductor material
US20060039227A1 (en) * 2004-08-17 2006-02-23 Lawrence Lai Memory device having staggered memory operations
JP2018142745A (ja) * 2018-06-18 2018-09-13 株式会社東芝 半導体集積回路

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2839375B2 (ja) * 1991-01-14 1998-12-16 三菱電機株式会社 半導体集積回路装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5844592A (ja) * 1981-07-24 1983-03-15 マ−ズ・リミテツド 分配供給装置
JPS59958A (ja) * 1983-06-24 1984-01-06 Hitachi Ltd 半導体集積回路
US4516312A (en) * 1981-02-12 1985-05-14 Fujitsu Limited Method for constructing delay circuits in a master slice IC
US4549131A (en) * 1981-12-26 1985-10-22 Olympus Optical Company Limited Semiconductor device and technique which employs normally unused interconnection elements as resistor circuit elements

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58119648A (ja) * 1982-01-08 1983-07-16 Mitsubishi Electric Corp 半導体集積回路装置
JPS6018932A (ja) * 1983-07-12 1985-01-31 Seiko Epson Corp 半導体装置
JPS6197843U (ja) * 1984-12-03 1986-06-23

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4516312A (en) * 1981-02-12 1985-05-14 Fujitsu Limited Method for constructing delay circuits in a master slice IC
JPS5844592A (ja) * 1981-07-24 1983-03-15 マ−ズ・リミテツド 分配供給装置
US4549131A (en) * 1981-12-26 1985-10-22 Olympus Optical Company Limited Semiconductor device and technique which employs normally unused interconnection elements as resistor circuit elements
JPS59958A (ja) * 1983-06-24 1984-01-06 Hitachi Ltd 半導体集積回路

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175604A (en) * 1985-11-15 1992-12-29 Kabushiki Kaisha Toshiba Field-effect transistor device
US5136356A (en) * 1989-04-19 1992-08-04 Seiko Epson Corporation Semiconductor device
US5124778A (en) * 1989-09-29 1992-06-23 Nec Corporation CMOS semiconductor integrated circuit device
US5225693A (en) * 1990-02-09 1993-07-06 Sony Corporation Cmos gate array configured as a sram with load resistors over gate electrodes
US5146113A (en) * 1990-03-09 1992-09-08 Fujitsu Limited Semiconductor integrated circuit having an oriented resistance pattern
US5474948A (en) * 1990-10-22 1995-12-12 Nec Corporation Method of making semiconductor device having polysilicon resistance element
WO1995019649A1 (en) * 1994-01-12 1995-07-20 Micrel, Inc. High value gate leakage resistor
US5589702A (en) * 1994-01-12 1996-12-31 Micrel Incorporated High value gate leakage resistor
US5949098A (en) * 1995-06-15 1999-09-07 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit having an improved arrangement of power supply lines to reduce noise occurring therein
US6218703B1 (en) 1995-07-23 2001-04-17 Ricoh Company, Ltd. Semiconductor device with control electrodes formed from semiconductor material
US5998842A (en) * 1995-07-24 1999-12-07 Ricoh Company, Ltd. Semiconductor device with gate and control electrodes that provide independent control of drain current
US20060039227A1 (en) * 2004-08-17 2006-02-23 Lawrence Lai Memory device having staggered memory operations
JP2018142745A (ja) * 2018-06-18 2018-09-13 株式会社東芝 半導体集積回路

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JPS61144056A (ja) 1986-07-01
JPH0638468B2 (ja) 1994-05-18

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