US5003561A - Process for the reception of a binary digital signal - Google Patents

Process for the reception of a binary digital signal Download PDF

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Publication number
US5003561A
US5003561A US07/417,150 US41715089A US5003561A US 5003561 A US5003561 A US 5003561A US 41715089 A US41715089 A US 41715089A US 5003561 A US5003561 A US 5003561A
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Prior art keywords
clock
delay
digital signal
pulses
pulse
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US07/417,150
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Alexander Dragotin
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Siemens AG
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Siemens AG
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Assigned to SIEMENS AKTIENGESELLSCHAFT, BERLIN AND MUNICH, FED. REP. OF GERMANY A CORP. OF FED. REP. OF GERMANY reassignment SIEMENS AKTIENGESELLSCHAFT, BERLIN AND MUNICH, FED. REP. OF GERMANY A CORP. OF FED. REP. OF GERMANY ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: DRAGOTIN, ALEXANDER
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop

Definitions

  • This invention relates to a process for the reception of a binary digital signal, which may also exhibit phase shifts, and it relates, more particularly, to an arrangement including elements having an approximately constant propagation delay, operating at a clock whose frequency is equal to or plesiochronous with the bit rate of the digital signal and whose phase difference is selected arbitrarily with respect to the digital signal.
  • a circuit arrangement for the regeneration and synchronization of a digital signal, which compensates for the phase oscillations of the incoming signal bits, is already known from German patent document DE 34 31 501 A1.
  • it contains a series circuit consisting of a controllable delay line coupled to a delay control unit, to which the controllable delay line is connected through address lines.
  • the decision logic is supplied over a clock line with a system clock whose frequency corresponds to the bit rate of the digital signal that is to be regenerated and synchronized.
  • the rising and falling edges of each binary digit lie within a fixed pattern, which is determined by the period of the clock frequency. Any deviation of the edges from this pattern is referred to as jitter. Within defined limits, this jitter must not result in information errors when the signal is received.
  • the first consists of time deviations of two successive edges from the prescribed raster, the second of slowly developing phase shifts, which can lead to a time shift of more than one period.
  • FIG. 1 shows a period T of the clock frequency, with a permissible jitter range -x and +x for the pulse transitions or edges. For a delay-free phase equalization, only one edge can be the reference point for the arrival of a new pulse of the digital signal. If this occurs, in accordance with FIG. 2, at the time t2, then a half-period T/2 of the clock frequency must elapse before the pulse is received at time t4. The deviations that can occur in the determination of the time T/2 are taken into account by the time intervals + y and - y.
  • An object of the present invention is to provide a process for the inertia-free reception of a binary digital signal with a changing phase position.
  • the invention accomplishes the foregoing purpose by a process step set wherein a binary digital signal subject to phase shifts.
  • An edge that serves to derive pulses is also referred to as an effective edge.
  • the deviation y depends first of all on the basic or additional delay t1, which can be expressed as the time interval T/n, where n is the number n of the pulses. It is also dependent on the accuracy ⁇ with which the time interval T/2 can be measured. This can be accomplished over a fixed number of gate delays. The formula for the deviation is then
  • the process according to the invention can be used in synchronously operating systems. In this case a perfect reception of the data signals is made possible by the compensation of any desired phase position. This process has the effect of clock recovery.
  • Another possible application is a block switching, in which a synchronization of the block frequencies is unnecessary.
  • the process can be used in order to compensate a phase that is continually changing because of differences in the clock frequency. However, it can also be used when the various information blocks have different phase positions.
  • FIG. 1 provides an explanation of jitter.
  • FIG. 2 shows a moment at which a pulse is received.
  • FIG. 3 shows a basic circuit diagram of an illustrative embodiment for carrying out the process according to the invention for constant delays.
  • FIG. 4 provides a basic circuit diagram of an illustrative embodiment for carrying out the process according to the invention for fluctuating delays.
  • FIG. 5 depicts a circuit diagram of an actual illustrative arrangement in accordance with FIG. 4.
  • FIG. 6 shows a circuit diagram of a practical illustrative embodiment in accordance with FIG. 3.
  • FIG. 3 shows a basic diagram of an arrangement for the implementation of the process with constant delays.
  • the arrangement includes a D flip-flop 6, an arrangement 4 for the derivation of a short read pulse I21 and an arrangement 5 for the derivation of a reset pulse RI from the effective edge of a digital signal D1, principal delay units "G” 7-11 additional delay units “Z” 12 and 13, arrangements 14-19 for the derivation of the pulses I11-I16, AND gates 20-25 and 32-37, SR flip-flops 26-31 and an OR gate 38.
  • the arrangements 4 and 5, and 14-19 may be implemented by a circuit such as that labelled "B" in FIG. 5.
  • An input 2 receives a clock frequency T1 which may deviate slightly from the bit sequence frequency of a digital signal D1 at the input 1 and may have an arbitrary phase position with respect to it.
  • the digital signal D1 is fed to the D input of the D flip-flop 6.
  • the rising edges of the digital signal D1 are the effective edges.
  • read pulses I21 are derived from these edges.
  • the duration of these pulses is small compared to a clock period T, but large enough so that logic elements can be driven by them.
  • further reset pulses RI of corresponding duration are derived from the effective edges of the digital signal D1 and fed to the R inputs of all the SR flip-flops 26-31.
  • the clock signal T1 is fed into the delay line of elements 7-13, which comprises principal delays elements "G" 7-11, and additional delay units "Z" 12 and 13.
  • the principal and additional delays t1 are equal to T/6.
  • Each principal delay unit “G” drives from the effective edges of the clock signals T1 to T6 short pulses Ill to I16, whose duration is larger than the principal delay t1 and is large enough, even for big values of n, so that logic elements can be driven by them.
  • the pulses I11-I16 are each applied to one input of the AND gates 20-25.
  • the second inputs are connected with the output of the arrangement 4. When a read pulse I21 arrives from this output, then the pulse or pulses that are already present is/are switched through from the sequence I11-I16 and arrive at the setting input S of the SR flip-flops 26-31, which have been reset with a resetting pulse shortly before.
  • the Q outputs of these RS flip-flops 26-31 are connected to the first inputs of the AND gates 32-37, whose second inputs are connected with clock outputs of the principal delay units "G" 8-11 and the additional delay units "Z" 12 and 13.
  • the pulses T3-T8 have been renamed F1-F6 for further processing.
  • the outputs of the AND gates 32-37 are wired to the inputs of the OR gate 38 and its output is wired in turn to the clock input of the D flip-flop 6.
  • the delay between the effective edge of the digital signal D1 and that of the input clock Te at the clock input of the D flip-flop 6 can be set in such a manner that it is equal to T/2 for each newly received pulse of the digital signal D1.
  • the emitted digital signal D2 thus consists only of correctly scanned pulses.
  • FIG. 4 shows a basic diagram of an arrangement for the implementation of the process with fluctuating delays.
  • the arrangement comprises all the elements of the arrangement according to FIG. 3.
  • it includes auxiliary delay units "H" 39 -41, arrangements 42-45 for the derivation of read pulses I21-I24, a clock period measurement device 46, AND gates 47-50, 60-63 and 68-71, supplementary delay units "E" 52-55, arrangements 56-59 for the derivation of pulses I17-I110, SR flip-flops 64 -67 and an OR gate 51.
  • the principal delay units "G" are sufficient.
  • the number of supplementary delay lines "E” must be chosen in such a manner that a further delay, equal to a clock period T takes place along the delay units of these two kinds.
  • an adjustable delay of the read command is introduced in the signal processing path. This is achieved by a gradual delay of the digital signal D1 so that a sequence of read pulses I21-I24 is derived over the auxiliary delay elements "H" 39-41 with auxiliary delays t2 and the arrangements 42-45.
  • the clock period measurement device 46 determines which of the arrangements 56-59 has a pulse at its output at that time. According to the result in each case, either a read pulse I21 is switched through over the AND gate 47, or a read pulse I22, I23 or I24 which is delayed with respect to the read pulse I21 is switched through one of the AND gates 48-50, as a read pulse I2x. This pulse then arrives through the OR gate 51 at the second inputs of the AND gates 20-25 and 60-63. The process then proceeds as has already been described with respect to FIG. 3.
  • the arrangements 42-45 and 56-59 may be implemented by the circuit labelled "B" in FIG. 5.
  • FIG. 5 shows a practical arrangement using the basic circuit diagram of FIG. 4.
  • the arrangement comprises a NAND gate 72, non-inverting gate elements 73-90 and inverting gate elements 91 -99, each of which is used for time delay, AND gates 100-115, D flip-flops "A” 116-124, an OR gate 125, circuit complexes "B” 126 -142, circuit complexes "C” 143-157, an OR gate 158 and the D flip-flop 6.
  • the circuit complex "B” comprises an AND gate 159, an inverting gate element 160 for delay and non-inverting gate elements 161 and 162 for delay.
  • the lower terminal is connected to the upper terminal (not shown) of the subsequent circuit complex "B" 126.
  • the circuit complexes 126-142 are connected with one another correspondingly.
  • the circuit complex "C” comprises a NAND gate 163, an SR flip-flop 164 and an AND gate 165.
  • the terminals in the circuit diagram are arranged geometrically in the same manner as in the "black boxes” 116-124, 126-142 and 143-157.
  • the circuit complexes "B” and “C” operate like the elements 7 -37 and 52-71 in FIG. 4.
  • the gates 73, 75, 77, 79, 81, 83, 85 and 87 form an auxiliary delay chain with eight members.
  • Each of the AND gates 100-108 which receives both a pulse Ilx and a read pulse I2x emits a signal to the OR gate 125, at whose output the read pulse I2x appears with the desired delay.
  • the NAND gate 72 supplies a reset pulse RI for all the SR flip-flops 164.
  • the AND gates 109-115 serve to suppress any second pulse Ilx that may have been stored. If, for example, the Q outputs of the D flip-flops "A" 116 and 117 are in the logic state "1", then the logic state at the output of the AND gate 109 is also "1" and a logic state "1" can occur at the output of the AND gate 102. Now if a logic state "0" occurs at the Q output of the D flip-flop "A”, then corresponding states must occur at the outputs of the AND gates 110-115.
  • FIG. 6 shows a practical embodiment of the arrangement according to FIG. 3.
  • the arrangement contains inverting gate elements 166-169 and 172-187 for delay, exclusive OR gates 170 and 171 and 188-193, AND gates 194-199 and 206-211, D flip-flops 200-205, an OR gate 212 and the D flip-flop 6 already shown in FIG. 3.
  • the digital signal D1 present at input 1 is read in the D flip-flop 6 with the input pulse Te and received at the output 3 as a digital signal D2.
  • the remainder of the circuit is used to derive the input pulse Te from the clock T1 that is present at the input 2.
  • the clock signal T1 is fed into a delay chain 172-187 with sixteen members, in which every two inverting gate elements form a delay element. Their number is chosen in such a manner that the clock signal at the output of the inverting gate element 183 is always delayed by one clock period with respect to the clock signal T1 at the input 2, when the delay time per gate element is at a minimum.
  • the exclusive OR gates 188-193 emit pulses with a width equal to three times the delay time of a gate element, if the state of the delay chain 172-187 changes in its range. These pulses cover, step by step, the phase range from 0° to 360°.
  • the exclusive OR gate 170 in conjunction with the inverting gate elements 166 and 167, emits a resetting pulse RI, which resets all the D flip-flops 200-205 for each change in the state of the digital signal D1.
  • RI resetting pulse
  • the inverting gate elements 168 and 169 and the exclusive OR gate 171 emit a read pulse that is delayed with respect to the resetting pulse RI.
  • the exclusive OR gate receives at its output a logic state of "1" , in which case the same state occurs at the input of the respective delay element if the read pulse is present.
  • a logic state of "1” must be present at the output of the respective exclusive OR gate from the exclusive OR gates 188-193, which is true only when there is a logic state of "0" at the output of the third inverting gate element following the input of the delay element.
  • the Q output of the next D flip-flop of the D flip-flops 200-205 also receives the logic state "1".
  • the next AND gate of the AND gates 206-211 receives at its output a logic state of "1", if not only the Q output of the respective D flip-flop but also the Q output of the preceding D flip-flop has the same state. In addition, the logic state at the output of the next delay element after that must have the logic state "1".
  • the outputs of AND gates 206-211 will be linked at OR gate 212. If two of the AND gates 206-211 have a logic state "1"0 at the output, and are based on clock pulses which shift with respect to each other by a clock period, that causes no problem.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Pulse Circuits (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Manipulation Of Pulses (AREA)
  • Communication Control (AREA)
  • Circuits Of Receivers In General (AREA)
US07/417,150 1988-10-13 1989-10-04 Process for the reception of a binary digital signal Expired - Fee Related US5003561A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP88117055A EP0363513B1 (de) 1988-10-13 1988-10-13 Verfahren und Schaltungsanordnung zum Empfang eines binären Digitalsignals
EP88117055 1988-10-13

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5220581A (en) * 1991-03-28 1993-06-15 International Business Machines Corporation Digital data link performance monitor
US5487095A (en) * 1994-06-17 1996-01-23 International Business Machines Corporation Edge detector
US5617452A (en) * 1993-03-01 1997-04-01 Telefonaktiebolaget Lm Ericsson Bit synchronizer
WO1998004043A1 (en) * 1996-07-23 1998-01-29 Honeywell Inc. High resolution digital synchronization circuit
EP0843418A1 (de) * 1996-11-19 1998-05-20 STMicroelectronics S.A. Serie-Parallel-Umwandlungsvorrichtung für Hochfrequenz-/Niedrigamplitude-Signale
US20090014539A1 (en) * 1998-09-11 2009-01-15 Metrologic Instruments, Inc. Electronic-ink based information organizing device employing an activator module mounted beneath the surface of an electronic-ink display structure
US20140241526A1 (en) * 2013-02-27 2014-08-28 Mstar Semiconductor, Inc. Data sampling and data encryption/decryption method and electronic device utilizing the methods

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146478A (en) * 1989-05-29 1992-09-08 Siemens Aktiengesellschaft Method and apparatus for receiving a binary digital signal
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
US6150855A (en) * 1990-02-06 2000-11-21 Bull, S.A. Phase-locked loop and resulting frequency multiplier
FR2664770A1 (fr) * 1990-07-11 1992-01-17 Bull Sa Procede et systeme de transmission numerique de donnees en serie.
FR2664769A1 (fr) * 1990-07-11 1992-01-17 Bull Sa Dispositif d'echantillonnage de donnees et systeme de transmission numerique de donnees en resultant.
EP0490273A3 (en) * 1990-12-10 1992-12-09 Advantest Corporation Retiming circuit

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US3593160A (en) * 1967-11-21 1971-07-13 Int Computers Ltd Clock-synchronizing circuits
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DE1221671B (de) * 1964-06-09 1966-07-28 Ericsson Telefon Ab L M Anordnung zum Empfang pulscodemodulierter Zeitteilungsmultiplex-Signale
US3593160A (en) * 1967-11-21 1971-07-13 Int Computers Ltd Clock-synchronizing circuits
US3819853A (en) * 1971-11-18 1974-06-25 Trt Telecom Radio Electr System for synchronous data transmission through a digital transmission channel
US3961138A (en) * 1974-12-18 1976-06-01 North Electric Company Asynchronous bit-serial data receiver
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US4385395A (en) * 1980-04-22 1983-05-24 Sony Corporation Bit clock reproducing circuit
GB2143407A (en) * 1983-06-06 1985-02-06 Nitsuko Ltd Synchronising clock with data
EP0168330A1 (de) * 1984-07-13 1986-01-15 Michel Servel Schaltungsanordnung zur automatischen Synchronisation eines lokalen Taktgenerators mit einem Datensignal und die Anordnung enthaltende Abtastschaltung
DE3441501A1 (de) * 1984-11-14 1986-05-15 Standard Elektrik Lorenz Ag, 7000 Stuttgart Schaltungsanordnung zum regenerieren und synchronisieren eines digitalen signals
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EP0260632A1 (de) * 1986-09-17 1988-03-23 Alcatel Cit Einrichtung zur Neusynchronisierung einer oder mehrerer binärer Datenströme mit identischer oder Untervielfach-Datenrate auf ein synchrones Taktreferenzsignal

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5220581A (en) * 1991-03-28 1993-06-15 International Business Machines Corporation Digital data link performance monitor
US5617452A (en) * 1993-03-01 1997-04-01 Telefonaktiebolaget Lm Ericsson Bit synchronizer
US5692022A (en) * 1993-03-01 1997-11-25 Telefonaktiebolaget Lm Ericsson Bit synchronizer
US5487095A (en) * 1994-06-17 1996-01-23 International Business Machines Corporation Edge detector
WO1998004043A1 (en) * 1996-07-23 1998-01-29 Honeywell Inc. High resolution digital synchronization circuit
EP0843418A1 (de) * 1996-11-19 1998-05-20 STMicroelectronics S.A. Serie-Parallel-Umwandlungsvorrichtung für Hochfrequenz-/Niedrigamplitude-Signale
FR2756120A1 (fr) * 1996-11-19 1998-05-22 Sgs Thomson Microelectronics Dispositif de conversion serie/parallele d'un signal haute frequence de faible amplitude
US6175885B1 (en) 1996-11-19 2001-01-16 Sgs-Microelectronics S.A. System for series to parallel conversion of a low-amplitude and high frequency signal
US20090014539A1 (en) * 1998-09-11 2009-01-15 Metrologic Instruments, Inc. Electronic-ink based information organizing device employing an activator module mounted beneath the surface of an electronic-ink display structure
US20140241526A1 (en) * 2013-02-27 2014-08-28 Mstar Semiconductor, Inc. Data sampling and data encryption/decryption method and electronic device utilizing the methods
US9210471B2 (en) * 2013-02-27 2015-12-08 Mstar Semiconductor, Inc. Data sampling and data encryption/decryption method and electronic device utilizing the methods

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Publication number Publication date
DE3887890D1 (de) 1994-03-24
CA1320543C (en) 1993-07-20
ATE101769T1 (de) 1994-03-15
EP0363513A1 (de) 1990-04-18
EP0363513B1 (de) 1994-02-16

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