US5328863A - Process for manufacturing a ROM cell with low drain capacitance - Google Patents

Process for manufacturing a ROM cell with low drain capacitance Download PDF

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Publication number
US5328863A
US5328863A US07/668,873 US66887391A US5328863A US 5328863 A US5328863 A US 5328863A US 66887391 A US66887391 A US 66887391A US 5328863 A US5328863 A US 5328863A
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United States
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type
regions
gate
layer
channel
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Expired - Lifetime
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US07/668,873
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English (en)
Inventor
Paolo Cappelletti
Silvia Lucherini
Bruno Vajana
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STMicroelectronics SRL
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SGS Thomson Microelectronics SRL
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Assigned to SGS-THOMSON MICROELECTRONICS S.R.L. reassignment SGS-THOMSON MICROELECTRONICS S.R.L. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: CAPPELLETTI, PAOLO, LUCHERINI, SILVIA, VAJANA, BRUNO
Priority to US08/210,595 priority Critical patent/US5732012A/en
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Publication of US5328863A publication Critical patent/US5328863A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/387—Source region or drain region doping programmed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/383—Channel doping programmed

Definitions

  • the present invention relates to a process for the fabrication of an ROM memory cell having a low drain capacity.
  • the starting point is typically a substrate of semiconductor material.
  • a complex is formed, for example, by a layer of gate oxide-polysilicon-tungsten silicide.
  • n-implantation for example of phosphorus, suitable for creating the extension regions of source and drain, followed by a further n+ implantation, for example of arsenic, of part of the regions of source and drain.
  • the doping of the substrate in the vicinity of the drain junction causes a drain capacitance of the programmed cell that is higher than that of the unprogrammed cell: the values measured in the two cases are 2.9 fF/bit (unprogrammed cell) and 6.4 fF/bit (programmed cell).
  • the drain capacitance of each cell affects the bit line capacitance of the memory which, together with the metallizing resistance, the polysilicon resistance and the word line capacitance, determines the total access time of the memory cell.
  • the object of the present invention is to realize an ROM memory cell having a low drain capacity when the cell is programmed.
  • such object is attained by means of a process for the fabrication of an ROM memory cell having a low drain capacity, comprising the formation of a gate complex on a part of a substrate of semiconductor material which shall form the cell's channel region and a subsequent step of n- implantation outside said channel region for the formation of regions of source and drain having n-doping, characterized in that it subsequently comprises the masking of the drain region and of an adjacent part of the gate complex and a subsequent step of n+ implantation for the creation of an area having n+ doping in said source region.
  • the capacity of the drain region is thus reduced and with it the overall access time of the cell.
  • FIGS. 1 to 5 illustrate the different steps of the process according to the invention.
  • a gate complex 10 formed, in a way known in itself, by a triple layer of gate oxide-polysilicon-tungsten silicide 2, 3, 4, there is executed an n-implantation, in particular an implantation of phosphorus.
  • such n- implantation has the object of creating two regions of source 5 and of drain 6, respectively.
  • silicon dioxide spacers 7 (FIG. 3), which cover part of the regions of source and drain.
  • n+ implantation for example of arsenic, which, as shown in FIG. 5, creates an n+ doping area 9 inside the source region 5.
  • the cell is now ready for programming, which may be executed conventionally with an implantation of p dopant, for example boron, which determines the rise in the cell's threshold voltage.
  • p dopant for example boron
  • drain region 6 The presence of a low doping of the drain region 6 allows an appropriate limitation of the drain capacity of the programmed cell.

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  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
US07/668,873 1990-03-15 1991-03-13 Process for manufacturing a ROM cell with low drain capacitance Expired - Lifetime US5328863A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/210,595 US5732012A (en) 1990-03-15 1994-03-17 Rom cell with reduced drain capacitance

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT19694A IT1239707B (it) 1990-03-15 1990-03-15 Processo per la realizzazione di una cella di memoria rom a bassa capacita' di drain
IT1969A/90 1990-03-15

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US08/210,595 Division US5732012A (en) 1990-03-15 1994-03-17 Rom cell with reduced drain capacitance

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US5328863A true US5328863A (en) 1994-07-12

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US07/668,873 Expired - Lifetime US5328863A (en) 1990-03-15 1991-03-13 Process for manufacturing a ROM cell with low drain capacitance
US08/210,595 Expired - Lifetime US5732012A (en) 1990-03-15 1994-03-17 Rom cell with reduced drain capacitance

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US08/210,595 Expired - Lifetime US5732012A (en) 1990-03-15 1994-03-17 Rom cell with reduced drain capacitance

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US (2) US5328863A (de)
EP (1) EP0451883B1 (de)
JP (1) JPH05259412A (de)
DE (1) DE69133178D1 (de)
IT (1) IT1239707B (de)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19541469A1 (de) * 1994-11-29 1996-05-30 Mitsubishi Electric Corp Halbleitervorrichtung mit einem maskenprogrammierbaren Speicher und Herstellungsverfahren derselben
US5753553A (en) * 1994-02-10 1998-05-19 Mega Chips Corporation Method of fabricating ROMs by selectively forming sidewalls on wordlines
US5790452A (en) * 1996-05-02 1998-08-04 Integrated Device Technology, Inc. Memory cell having asymmetrical source/drain pass transistors and method for operating same
US5793086A (en) * 1992-06-26 1998-08-11 Sgs-Thomson Microelectronics, S.R.L. NOR-type ROM with LDD cells and process of fabrication
US6027978A (en) * 1997-01-28 2000-02-22 Advanced Micro Devices, Inc. Method of making an IGFET with a non-uniform lateral doping profile in the channel region
US6492234B1 (en) * 1997-05-13 2002-12-10 Stmicroelectronics S.R.L. Process for the selective formation of salicide on active areas of MOS devices

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1239707B (it) * 1990-03-15 1993-11-15 St Microelectrics Srl Processo per la realizzazione di una cella di memoria rom a bassa capacita' di drain
JP3202784B2 (ja) * 1992-04-13 2001-08-27 三菱電機株式会社 マスクｒｏｍ半導体装置およびその製造方法
JP3221766B2 (ja) * 1993-04-23 2001-10-22 三菱電機株式会社 電界効果トランジスタの製造方法
JP5179692B2 (ja) * 2002-08-30 2013-04-10 富士通セミコンダクター株式会社 半導体記憶装置及びその製造方法

Citations (18)

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US4513494A (en) * 1983-07-19 1985-04-30 American Microsystems, Incorporated Late mask process for programming read only memories
US4514897A (en) * 1979-09-04 1985-05-07 Texas Instruments Incorporated Electrically programmable floating gate semiconductor memory device
US4536944A (en) * 1982-12-29 1985-08-27 International Business Machines Corporation Method of making ROM/PLA semiconductor device by late stage personalization
US4649629A (en) * 1985-07-29 1987-03-17 Thomson Components - Mostek Corp. Method of late programming a read only memory
US4649638A (en) * 1985-04-17 1987-03-17 International Business Machines Corp. Construction of short-length electrode in semiconductor device
EP0227965A2 (de) * 1985-12-12 1987-07-08 STMicroelectronics S.r.l. Verfahren zum Programmieren durch Ionen-Implantation von Nurlesespeichern-NMOS und ein dadurch erhaltener Nurlesespeicher-NMOS
US4698787A (en) * 1984-11-21 1987-10-06 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
US4852062A (en) * 1987-09-28 1989-07-25 Motorola, Inc. EPROM device using asymmetrical transistor characteristics
US4874713A (en) * 1989-05-01 1989-10-17 Ncr Corporation Method of making asymmetrically optimized CMOS field effect transistors
US4956308A (en) * 1987-01-20 1990-09-11 Itt Corporation Method of making self-aligned field-effect transistor
EP0401113A2 (de) * 1989-05-31 1990-12-05 Fujitsu Limited Halbleiteranordnung und Verfahren zu deren Herstellung
US5024960A (en) * 1987-06-16 1991-06-18 Texas Instruments Incorporated Dual LDD submicron CMOS process for making low and high voltage transistors with common gate
US5032881A (en) * 1990-06-29 1991-07-16 National Semiconductor Corporation Asymmetric virtual ground EPROM cell and fabrication method
US5036017A (en) * 1988-11-29 1991-07-30 Mitsubishi Denki Kabushiki Kaisha Method of making asymmetrical field effect transistor
US5043294A (en) * 1989-09-04 1991-08-27 Siemens Aktiengesellschaft Method for manufacturing an FET with asymmetrical gate region
EP0451883A1 (de) * 1990-03-15 1991-10-16 STMicroelectronics S.r.l. Verfahren zur Fertigung einer ROM-Speicherzelle mit einer niedrigen Drainkapazität
US5141890A (en) * 1982-02-01 1992-08-25 Texas Instruments Incorporated CMOS sidewall oxide-lightly doped drain process
US5155056A (en) * 1990-04-04 1992-10-13 Goldstar Electron Co., Ltd. Process for formation of cells having self-aligned capacitor contacts, and structure thereof

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US4059826A (en) * 1975-12-29 1977-11-22 Texas Instruments Incorporated Semiconductor memory array with field effect transistors programmable by alteration of threshold voltage
US4225875A (en) * 1978-04-19 1980-09-30 Rca Corporation Short channel MOS devices and the method of manufacturing same
US4208780A (en) * 1978-08-03 1980-06-24 Rca Corporation Last-stage programming of semiconductor integrated circuits including selective removal of passivation layer
US4376947A (en) * 1979-09-04 1983-03-15 Texas Instruments Incorporated Electrically programmable floating gate semiconductor memory device
JPS583192A (ja) * 1981-06-30 1983-01-08 Fujitsu Ltd 読み出し専用メモリ
US4599118A (en) * 1981-12-30 1986-07-08 Mostek Corporation Method of making MOSFET by multiple implantations followed by a diffusion step
JPS58148448A (ja) * 1982-03-01 1983-09-03 Nippon Denso Co Ltd 半導体ｒｏｍの製造方法
JPH0626246B2 (ja) * 1983-06-17 1994-04-06 株式会社日立製作所 半導体メモリの製造方法
US4805143A (en) * 1986-01-16 1989-02-14 Hitachi Ltd. Read-only memory
JPS6364361A (ja) * 1986-09-03 1988-03-22 Sharp Corp マスクｒｏｍの製造方法
JPH02355A (ja) * 1987-12-15 1990-01-05 Seiko Epson Corp 半導体記憶装置
IT1217372B (it) * 1988-03-28 1990-03-22 Sgs Thomson Microelectronics Procedimento per la programmazione di memorie rom in tecnologia mos ecmos
US5117389A (en) * 1990-09-05 1992-05-26 Macronix International Co., Ltd. Flat-cell read-only-memory integrated circuit
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US4514897A (en) * 1979-09-04 1985-05-07 Texas Instruments Incorporated Electrically programmable floating gate semiconductor memory device
US5141890A (en) * 1982-02-01 1992-08-25 Texas Instruments Incorporated CMOS sidewall oxide-lightly doped drain process
US4536944A (en) * 1982-12-29 1985-08-27 International Business Machines Corporation Method of making ROM/PLA semiconductor device by late stage personalization
US4513494A (en) * 1983-07-19 1985-04-30 American Microsystems, Incorporated Late mask process for programming read only memories
US4698787A (en) * 1984-11-21 1987-10-06 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
US4868619A (en) * 1984-11-21 1989-09-19 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
US4649638A (en) * 1985-04-17 1987-03-17 International Business Machines Corp. Construction of short-length electrode in semiconductor device
US4649629A (en) * 1985-07-29 1987-03-17 Thomson Components - Mostek Corp. Method of late programming a read only memory
EP0227965A2 (de) * 1985-12-12 1987-07-08 STMicroelectronics S.r.l. Verfahren zum Programmieren durch Ionen-Implantation von Nurlesespeichern-NMOS und ein dadurch erhaltener Nurlesespeicher-NMOS
US4956308A (en) * 1987-01-20 1990-09-11 Itt Corporation Method of making self-aligned field-effect transistor
US5024960A (en) * 1987-06-16 1991-06-18 Texas Instruments Incorporated Dual LDD submicron CMOS process for making low and high voltage transistors with common gate
US4852062A (en) * 1987-09-28 1989-07-25 Motorola, Inc. EPROM device using asymmetrical transistor characteristics
US5036017A (en) * 1988-11-29 1991-07-30 Mitsubishi Denki Kabushiki Kaisha Method of making asymmetrical field effect transistor
US4874713A (en) * 1989-05-01 1989-10-17 Ncr Corporation Method of making asymmetrically optimized CMOS field effect transistors
EP0401113A2 (de) * 1989-05-31 1990-12-05 Fujitsu Limited Halbleiteranordnung und Verfahren zu deren Herstellung
US5043294A (en) * 1989-09-04 1991-08-27 Siemens Aktiengesellschaft Method for manufacturing an FET with asymmetrical gate region
EP0451883A1 (de) * 1990-03-15 1991-10-16 STMicroelectronics S.r.l. Verfahren zur Fertigung einer ROM-Speicherzelle mit einer niedrigen Drainkapazität
US5155056A (en) * 1990-04-04 1992-10-13 Goldstar Electron Co., Ltd. Process for formation of cells having self-aligned capacitor contacts, and structure thereof
US5032881A (en) * 1990-06-29 1991-07-16 National Semiconductor Corporation Asymmetric virtual ground EPROM cell and fabrication method

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Patent Abstracts of Japan, vol. 13, No. 304 (E-786) [3652], published Jul. 12, 1989, relating to Japanese Application JP-A-1 081 360, Hitachi Ltd., Mar. 27, 1989.

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793086A (en) * 1992-06-26 1998-08-11 Sgs-Thomson Microelectronics, S.R.L. NOR-type ROM with LDD cells and process of fabrication
US5753553A (en) * 1994-02-10 1998-05-19 Mega Chips Corporation Method of fabricating ROMs by selectively forming sidewalls on wordlines
DE19541469A1 (de) * 1994-11-29 1996-05-30 Mitsubishi Electric Corp Halbleitervorrichtung mit einem maskenprogrammierbaren Speicher und Herstellungsverfahren derselben
US5811862A (en) * 1994-11-29 1998-09-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a mask programmable memory and manufacturing method thereof
DE19541469C2 (de) * 1994-11-29 2001-03-15 Mitsubishi Electric Corp Maskenprogrammierbare Halbleitervorrichtungen und Verfahren zu deren Herstellung
US5790452A (en) * 1996-05-02 1998-08-04 Integrated Device Technology, Inc. Memory cell having asymmetrical source/drain pass transistors and method for operating same
US6027978A (en) * 1997-01-28 2000-02-22 Advanced Micro Devices, Inc. Method of making an IGFET with a non-uniform lateral doping profile in the channel region
US6492234B1 (en) * 1997-05-13 2002-12-10 Stmicroelectronics S.R.L. Process for the selective formation of salicide on active areas of MOS devices
US6800901B2 (en) 1997-05-13 2004-10-05 Stmicroelectronics S.R.L. Process for the selective formation of salicide on active areas of MOS devices

Also Published As

Publication number Publication date
EP0451883A1 (de) 1991-10-16
IT1239707B (it) 1993-11-15
IT9019694A1 (it) 1991-09-15
DE69133178D1 (de) 2003-01-30
EP0451883B1 (de) 2002-12-18
JPH05259412A (ja) 1993-10-08
IT9019694A0 (it) 1990-03-15
US5732012A (en) 1998-03-24

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