US5644526A - Integrated circuit with improved immunity to large metallization defects - Google Patents

Integrated circuit with improved immunity to large metallization defects Download PDF

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US5644526A
US5644526A US08/538,302 US53830295A US5644526A US 5644526 A US5644526 A US 5644526A US 53830295 A US53830295 A US 53830295A US 5644526 A US5644526 A US 5644526A
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integrated circuit
groups
conductors
array
strapping
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Stefano Mazzali
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STMicroelectronics SRL
Micron Technology Inc
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SGS Thomson Microelectronics SRL
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Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STMICROELECTRONICS, S.R.L. (FORMERLY KNOWN AS SGS-THMSON MICROELECTRONICS S.R.L.)
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

Definitions

  • the present invention relates to strapping connections in integrated circuit memory structures.
  • Memory devices always comprise at least one cell matrix comprising a plurality of rows, a plurality of columns and, in correspondence with each crossing between the rows and columns, a more or less complex memory cell.
  • the rows and columns consist generally of electrical conductors made of silicide or polysilicon which are materials with relatively low conductivity.
  • the process for making from the second metallic layer the additional plurality of conductors is subject to even larger defects for a variety of reasons, one of the many of which is the difficulty of planarization of the underlying structure. Said defects result in short circuiting of two or more adjacent conductors (depending on the size of the defect, as may be seen in FIG. 1.
  • redundancy is limited to short circuits between two adjacent rows for reasons of failure frequency and redundancy management circuitry simplicity and, for flash EPROM memories, the space occupied by the row and/or column decoding circuitry.
  • flash EPROM memory devices can be erased only in their entirety while they can be written one cell at a time. If a cell were never written but repeatedly erased (together with the others) it would be "emptied” in a short time and this would lead to read errors for the cells located in the same column. To obviate this shortcoming, before any erasing phase of the device there is a "preconditioning" phase affecting individually all the cells of the device (those of the perfectly operating rows, the defective ones and also the redundant ones) and consisting of writing the cells not already written by injecting charges in the insulated gate of the MOS transistor which makes them up.
  • the purpose of the present invention is to provide an integrated circuit having a structure such as to be tolerant of large manufacturing defects.
  • the present invention also concerns a memory device where the innovative strapping lines are used to shunt word lines.
  • the probability that a defect would affect two conductors, causing a short circuit between them, is reduced and for three conductors it is reduced even further.
  • FIGS. 1 and 4 show top views of second conductors in accordance with the known art
  • FIGS. 2, 5 and 7 show top views of first and second conductors in accordance with the present invention.
  • FIG. 3 shows a cross section view along plane of cut A--A of the conductors of FIG. 2.
  • FIG. 6 shows an example of a memory chip in which this invention can advantageously be used.
  • FIG. 1 shows a second plurality made up of six second metallic conductors CO2 which exhibit various electrical connection points opposite positions CP. Said conductors could be electrically connected as word lines of a memory matrix. Beneath the second conductors CO2 and along their entire length there is a corresponding first plurality made up of six first conductors CO1 (not shown in FIG. 1), e.g. silicide, exhibiting various electrical connection points opposite the positions CP. Again opposite the positions CP there are provided VIAs permitting electrical connection between the conductors CO1 and the conductors CO2.
  • FIG. 1 shows a defect D-0 such as to short circuit two adjacent conductors CO2.
  • FIG. 2 shows the second conductors CO2 of FIG. 1 as modified in accordance with the present invention. As may be seen, these are interrupted every two consecutive points CP and the breaks are in alternating positions. In the areas where the conductors CO2 are interrupted, the conductors CO1 are visible, while the conductors CO1 are hidden by the conductors CO2 in the remaining areas. In this way there remains relatively large integrated circuit areas not traversed by conductors CO2. This means, for example, that the defect D-0 no longer causes any short circuit between the conductors CO2.
  • the conductors CO1 depends on the specific application of the integrated circuit. In the case of memory devices they are parallel with each other, while in another case they could, for example, be arranged as the spokes of a wheel.
  • the positions of the breaks in the conductors CO2 are determined in such a manner as to leave relatively large areas of the integrated circuit not traversed by the second conductors CO2. These depend thus on the mutual positions of the conductors and the size of the defects which it is intended to tolerate.
  • FIGS. 2 and 5 show two of the many possible choices.
  • the positions CP are found in general at a constant distance every certain number of memory cells, e.g. 512. In other applications this might not be the optimal choice. In general the positions CP are determined on the basis of considerations on the electrical signal propagation time in the conductors CO1 and hence depend also on the type and number of electronic devices connected thereto.
  • the conductors CO2 are advantageously of the same type as the conductors CO1 and are superimposed thereon.
  • the electrical connection is then completed by means of VIAs. Naturally this is not indispensable for the purposes of the present invention.
  • FIG. 3 shows a cross section view along plane of section A--A of the conductors of FIG. 2 as if these belonged to a memory device.
  • the first conductors CO1 which act as word lines of a memory device and are arranged above a substrate BU and separated therefrom by insulating layers IS.
  • the substrate BU In the substrate BU are made pockets SO and DR which act as source and drain areas respectively for MOS devices constituting memory cells.
  • a dielectric layer DL In which are arranged third metallic conductors CO3 acting as bit lines of the memory device.
  • second conductors CO2 opposite some of the first conductors CO1.
  • the present invention finds advantageous application in memory devices. With the aid of FIGS. 4 and 5 there is explained below an embodiment thereof suited specifically thereto.
  • FIG. 4 shows a plurality of rows of such a memory device and three defects D-1, D-2 and D-3 caused by the process for making the rows in a metallic layer.
  • the defect D-2 results in a short circuit between two adjacent rows and hence could be recovered by making use of redundancy.
  • the defects D-1 and D-3 would cause rejection of the device since they involve a short circuit between four and six adjacent rows respectively.
  • FIG. 4 was interrupted at several points giving rise to the rows of FIG. 5.
  • pairs of rows were taken into consideration, the rows of each pair were interrupted at the same positions, and adjacent pairs were interrupted in alternating positions.
  • each strap is e.g. 128 cells.
  • the pitch of metal2 is 2.4 ⁇ m (linewidth 2.2 ⁇ m).
  • the poly2 pitch in the presently preferred embodiment, is 1.2 microns (linewidth 0.6 micron).
  • FIG. 6 shows an example of a memory chip in which this invention can advantageously be used.
  • This is an 8K ⁇ 8 low-power EEPROM, but of course the disclosed innovative device structure can also be used in many other specific integrated circuits.
  • Address Latch 604 receives the low-order Address bits A0-A5, and Address Latch 602 receives the higher-order (page address) Address bits A6-A12.
  • the Address Latch 604 drives a Y Decode block 606, which provides corresponding output signals to a sense and data latch 632.
  • the Address Latch 602 provides address bits to the X Decode circuitry 608.
  • the sense and data latch 632 provides a data interface to the columns of this memory array.
  • I/O buffers 635 provide an external connection from the sense and data latch 632 to external data lines DQ0-DQ7.
  • Control logic 620 sends and receives external control signals, including RB, E, G, and W, and correspondingly provides control signals to other elements on chip. Note that the control logic 620 also drives a reset logic 622, which is connected to a Vpp Generator circuit 624.
  • FIG. 7 is a modification of FIG. 4, in that the rows containing the defect D-2 have been removed to illustrate another possible arrangement of the interruptions of the rows in groups of four. As may be seen in FIG. 7, defects D-1 and D-3 no longer cause any problems because they do not affect any row.
  • An integrated circuit memory comprising: an array of memory cells arranged in rows and columns; a plurality of word lines each connected to plural cells in at least one respective row of the array; a plurality of bitlines each connected to plural cells in at least one respective column of the array; and strapping connections, formed in an additional thin film layer, each connecting two separate locations of a respective one of the word lines to shunt the resistivity of a respective portion of the respective word line; wherein the strapping connections are arranged, in groups, in a checkerboard pattern over the array.
  • An integrated circuit memory comprising: an array of memory cells arranged in rows and columns; a plurality of word lines each connected to plural cells in at least one respective row of the array; a plurality of bitlines each connected to plural cells in at least one respective column of the array; and strapping connections, formed in an additional thin film layer, each connecting two separate locations of a respective one of the word lines to shunt the resistivity of a respective portion of the respective word line; wherein the strapping connections provide only discontinuous shunting of the word lines, and at least some of the strapping connections are adjacent to other strapping connections.
  • An integrated circuit memory comprising: an array of memory cells arranged in rows and columns; a plurality of word lines each connected to plural cells in at least one respective row of the array; a plurality of bitlines each connected to plural cells in at least one respective column of the array; and strapping connections, formed in an additional thin film layer, each connecting two separate locations of a respective one of the word lines to shunt the resistivity of a respective portion of the respective word line; wherein the strapping connections are arranged, in groups, in a regular pattern over the array such that at least some of the strapping connections in the pattern are laterally adjacent to exactly one other strapping connection.
  • An integrated circuit comprising: a) a first plurality of first conductors a first material with relatively low conductivity and each having a plurality of first electrical connection points arranged along itself, and b) a second corresponding plurality of second conductors made of a second material with relatively high conductivity and each having a plurality of second electrical connection points along itself and the plurality of first points being electrically connected to the plurality of second points respectively in such a manner as to reduce the series resistance of the first conductors and characterized in that the second conductors are interrupted between some second consecutive points in such a manner as to leave relatively large areas of the integrated circuit not traversed by the second conductors.
  • a method for fabricating an integrated circuit memory comprising the steps of: fabricating an array of memory cells arranged in rows and columns, and a plurality of word lines each connected to plural cells in at least one respective row of the array, and a plurality of bitlines each connected to plural cells in at least one respective column of the array; and forming strapping connections, in an additional thin film layer which is not otherwise used in the array or memory cells; wherein each the strapping connection connects two separate locations of a respective one of the word lines to shunt the resistivity of a respective portion of the respective word line; wherein the strapping connections are arranged, in groups, in a checkerboard pattern over the array.
  • a method for fabricating an integrated circuit memory comprising the steps of: fabricating an array of memory cells arranged in rows and columns, and a plurality of word lines each connected to plural cells in at least one respective row of the array, and a plurality of bitlines each connected to plural cells in at least one respective column of the array; and forming strapping connections, in an additional thin film layer which is not otherwise used in the array or memory cells; wherein each the strapping connection connects two separate locations of a respective one of the word lines to shunt the resistivity of a respective portion of the respective word line; wherein the strapping connections provide only discontinuous shunting of the word lines, and at least some of the strapping connections are adjacent to other strapping connections.
  • a method for fabricating an integrated circuit memory comprising the steps of: fabricating an array of memory cells arranged in rows and columns, and a plurality of word lines each connected to plural cells in at least one respective row of the array, and a plurality of bitlines each connected to plural cells in at least one respective column of the array; and forming strapping connections, in an additional thin film layer which is not otherwise used in the array or memory cells; wherein each the strapping connection connects two separate locations of a respective one of the word lines to shunt the resistivity of a respective portion of the respective word line; wherein the strapping connections are arranged, in groups, in a regular pattern over the array such that at least some of the strapping connections in the pattern are laterally adjacent to exactly one other strapping connection.
  • an integrated circuit memory wherein said memory cells are non-volatile memory cells.
  • an integrated circuit memory wherein the strapping connections are arranged in groups of two.
  • an integrated circuit memory wherein the strapping connections are arranged in groups of four.
  • the disclosed interconnect topology can be applied to strapping busses, or to strapping lines of a logic array.
  • the disclosed interconnect topology can be applied to processes which include more than two levels of metal and/or more than two levels of polysilicon or polycide.
  • the disclosed inventions are applied to a structure wherein the transistor channels are in a bulk monocrystalline silicon substrate; but alternatively the disclosed inventions can be applied to a structure using thin-film transistors, i.e. transistors with polysilicon or polySiGe channels.
  • the disclosed inventions are applied to a structure which includes only MOS devices; but alternatively the disclosed inventions can also be applied to structures which also include bipolar transistors (as long as the current density is low enough that the interrupted shunts can provide an adequate reduction in series resistance).
  • the disclosed interconnect topology can be applied to processes which include more than two levels of metal and/or more than two levels of polysilicon or polycide.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
US08/538,302 1994-09-30 1995-10-02 Integrated circuit with improved immunity to large metallization defects Expired - Lifetime US5644526A (en)

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EP94830468 1994-09-30
EP94830468A EP0704901B1 (de) 1994-09-30 1994-09-30 Integrierte Schaltung mit Toleranz bei wichtigen Herstellungsfehlern

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5933725A (en) * 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
US5940315A (en) * 1998-09-01 1999-08-17 Micron Technology, Inc. Strapped wordline architecture for semiconductor memory
US6549443B1 (en) * 2001-05-16 2003-04-15 Rockwell Collins, Inc. Single event upset resistant semiconductor circuit element
US10685951B1 (en) * 2018-12-10 2020-06-16 Globalfoundries Inc. Wordline strapping for non-volatile memory elements
US11004491B2 (en) 2019-09-25 2021-05-11 Globalfoundries U.S. Inc. Twisted wordline structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4777387A (en) * 1984-02-21 1988-10-11 International Rectifier Corporation Fast turn-off circuit for photovoltaic driven MOSFET
US4827449A (en) * 1986-06-27 1989-05-02 Oki Electric Industry Co., Ltd. Semiconductor device
US4833342A (en) * 1987-05-15 1989-05-23 Kabushiki Kaisha Toshiba Reference potential generating circuit
US5467316A (en) * 1991-12-04 1995-11-14 Samsung Electronics Co., Ltd. Device and method of reducing word line resistance of a semiconductor memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4777387A (en) * 1984-02-21 1988-10-11 International Rectifier Corporation Fast turn-off circuit for photovoltaic driven MOSFET
US4827449A (en) * 1986-06-27 1989-05-02 Oki Electric Industry Co., Ltd. Semiconductor device
US4833342A (en) * 1987-05-15 1989-05-23 Kabushiki Kaisha Toshiba Reference potential generating circuit
US5467316A (en) * 1991-12-04 1995-11-14 Samsung Electronics Co., Ltd. Device and method of reducing word line resistance of a semiconductor memory

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5933725A (en) * 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
US5940315A (en) * 1998-09-01 1999-08-17 Micron Technology, Inc. Strapped wordline architecture for semiconductor memory
US6549443B1 (en) * 2001-05-16 2003-04-15 Rockwell Collins, Inc. Single event upset resistant semiconductor circuit element
US10685951B1 (en) * 2018-12-10 2020-06-16 Globalfoundries Inc. Wordline strapping for non-volatile memory elements
US11004491B2 (en) 2019-09-25 2021-05-11 Globalfoundries U.S. Inc. Twisted wordline structures

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EP0704901A1 (de) 1996-04-03
DE69422174D1 (de) 2000-01-20
DE69422174T2 (de) 2000-08-24
EP0704901B1 (de) 1999-12-15

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