US5963460A - Apparatus for computing transcendental functions quickly - Google Patents

Apparatus for computing transcendental functions quickly Download PDF

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Publication number
US5963460A
US5963460A US08/768,781 US76878196A US5963460A US 5963460 A US5963460 A US 5963460A US 76878196 A US76878196 A US 76878196A US 5963460 A US5963460 A US 5963460A
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Prior art keywords
read rom
multiply
rom
read
add element
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Leonard D. Rarick
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STMicroelectronics lnc USA
Metaflow Technologies Inc
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Metaflow Technologies Inc
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Assigned to METAFLOW TECHNOLOGIES, INC. reassignment METAFLOW TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RARICK, LEONARD
Priority to EP97310118A priority patent/EP0849664B1/fr
Priority to DE69712720T priority patent/DE69712720T2/de
Priority to JP9344758A priority patent/JPH10214176A/ja
Priority to US09/267,330 priority patent/US6317764B1/en
Publication of US5963460A publication Critical patent/US5963460A/en
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Assigned to STMICROELECTRONICS, INC. reassignment STMICROELECTRONICS, INC. MERGER (SEE DOCUMENT FOR DETAILS). Assignors: METAFLOW TECHNOLOGIES INCORPORATED
Priority to US10/012,660 priority patent/US6581079B2/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/556—Logarithmic or exponential functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/548—Trigonometric functions; Co-ordinate transformations

Definitions

  • This invention relates to apparatus for computing transcendental functions quickly.
  • Taylor series generally requires one "add” instruction (which might take, for example, three clock times) and one "multiply” instruction (which might also take, for example, three more clock times) for each term.
  • add which might take, for example, three clock times
  • multiply which might also take, for example, three more clock times
  • processors computing transendental functions to significant accuracy, it requires a number of terms to achieve a residual error less than the least significant bit of the answer.
  • the number of terms is about ten for achieving 64-bit accuracy for the full range of an ordinary Taylor series; if multiply and add operations each take about three clock times, this would take about sixty clock times, which can be a significant amount of time when computation resources are at a premium. To obtain greater accuracy, even more terms and thus even more time would be required.
  • the invention provides a method and system for computing transcendental functions quickly.
  • the multiply arithmetic logic unit (ALU) is enhanced to include the operation of adding a term to the product, (2) rounding operations for intermediate multiply and add operations are skipped, (3) the Taylor series for the transcendental function is separated into two partial series which are performed in parallel, and (4) subtraction and recipricoals, if any, are reserved for the end of the computation.
  • ALU multiply arithmetic logic unit
  • transcendental functions computed using a series with multiple terms are thus performed in about one sixth of the "natural" amount of time per term, or about one clock time per term in processors in which multiply and add operations each take about three clock times each.
  • FIG. 1 shows a floating-point processing unit for computing transcendental functions.
  • FIG. 1 shows a floating-point processing unit for computing transcendental functions.
  • the floating-point processing unit 100 receives an operand at the input register 110, computes a transcendental function, such as a trigonometric function (SIN, COS, TAN, SEC, CSC, or COT), an inverse trigonometric function (ARCSIN, ARCCOS, ARCTAN, ARCSEC, ARCCSC, or ARCCOT), an exponential function (EXP or LN), a hyperbolic trigonometric function (SINH, COSH, TANH, SECH, CSCH, or COTH), or an inverse hyperbolic trigonometric function (ARCSINH, ARCCOSH, ARCTANH, ARCSECH, ARCCSCH, or ARCCOTH), and provides an output value at the output register 150.
  • a trigonometric function such as a trigonometric function (SIN, COS, TAN, SEC, CSC, or COT)
  • ARCSIN, ARCCOS, ARCTAN, ARCSEC, ARCCSC, or ARCCOT an
  • each transcendental function is computed using a Taylor series.
  • Taylor series are known in the art of computing transcendental functions.
  • SIN function can be computed using the following series: ##EQU1## where a b indicates exponentiation: a b .
  • the input register 110, register file 130, storage element 140, the output register 150, and other registers described herein each comprise 32-bit, 64-bit, or 80-bit registers disposed for storing floating-point numbers stored in a known floating-point numeric format, such as the IEEE standard format for floating-point numbers having one bit for sign, 15 bits for exponent, and 64 bits for mantissa.
  • the floating-point processing unit 100 operates under control of the control element 180, which directs the flow of data among the elements of the floating-point processing unit 100 using control signals. Control signal paths are omitted from FIG. 1 for clarity.
  • the multiply-add unit 120 comprises a first input and a first holding register 123 for a first multiplicand, a second input and a second holding register 124 for a second multiplicand, a third input and a third holding register 125 for an addend, and an output.
  • the multiply-add unit 120 multiplies its multiplicands to produce a product, to which it adds its addend to produce its output.
  • the multiply-add unit 120 may comprise more than two pipeline stages (such as for example three, four, five, or more actual pipeline stages), in which cases a first group of its pipeline stages are collectively treated as the first stage 121 and a second group of its pipeline stages are collectively treated as the second stage 122.
  • the first stage 121 and the second stage 122 take approximately equal amounts of time to perform their functions.
  • the multiply-add unit 120 comprises multiply circuits which compute partial products for its two multiplicands.
  • the addend for the multiply-add unit 120 is additively combined with the partial products when those partial products are added, thus saving time otherwise required for an addition operation.
  • the method of computation uses a reformulated series for computing each transcendental function.
  • the column labeled "mul 1" indicates an operation performed by the first stage 121 of the floating-point multiply-add unit 120.
  • the column labeled “mul 2” indicates an operation performed by the second stage 122 of the floating-point multiply-add unit 120. Since each multiply-add operation requires two clock cycles, each operation which appears in the column labeled "mul 1" always appears in the next clock cycle in the column labeled "mul 2".
  • the equals sign indicates a name given to an output; outputs are routed to a register in the register file 130 for storage, or can be routed to one of the multiplicand holding registers 123 or 124 of the multiply-add unit 120, for further computation.
  • Data in the registers is indicated by names such as "a”, “b”, “c”, “d”, “e”, “f”, “g”, “h”, “i”, and “j”; these names can be reused in the table for different values. Routing directly to one of the multiplicand holding registers 123 or 124 is indicated by the names "p” and "q”; these names are not reused in the table for different values and typically indicate a value having that name in an indicated Taylor series.
  • Original input is indicated by the name "x".
  • the column labeled "add 1" indicates an operation performed by the first stage 161 of the adder unit 160.
  • the column labeled “add 2” indicates an operation performed by the second stage 162 of the adder unit 160
  • the column labeled “add 3” indicates an operation performed by the third stage 163 of the adder unit 160. Since each addition operation for the adder unit 160 requires three clock cycles, each operation which appears in the column labeled “add 1” always appears in the next clock cycle in the column labeled "add 2" and in the following clock cycle in the column labeled "add 3".
  • control indicates an operation directed by the control unit 180.
  • the operation "read rom” means to read a value from the storage element 150, which may comprise a read-only memory (“ROM").
  • ROM read-only memory
  • the value 1.0 may also be supplied to the multiply-add unit 120 from the ROM, or may be generated internally in the first stage 121.
  • the function cos(x) may be computed in a similar manner as shown in table 2-2.
  • the two functions sin(x) and cos(x) may also be computed together in a single operation, in a similar manner, as shown in table 2-3.
  • the function tan(x) may be computed in a similar manner as shown in table 2-4.
  • the function TAN x uses computation of a multiplicative inverse.
  • the column labeled "newton” indicates operation of the newton element 170.
  • the value in parentheses indicates the number of bits of accuracy being computed. A greater number of bits of accuracy requires more time.
  • COSH x, SINH x, and TANH x are computed in a similar manner as COS x, SIN x, and TAN x, except that the different subseries are added instead of subtracted, as shown in equations 222, 223, and 226, respectively.
  • EXP x is computed in a similar manner as COS x or SIN x, except that subseries are used as shown in equation 224.
  • the function (2 x)-1 may be computed using these partial series as follows:
  • the function (2 x)-1 may therefore be computed as shown in table 2-5.
  • This equation 268 is computed as shown in table 2-7.
  • the function lg(x), the logarithm of x base 2, is another transcendental function which can be determined using a series.
  • the input argument, (x), is expressed as (p)(2 q), where q is an integer and 11/16 ⁇ p ⁇ 23/16; the integer q might be positive, zero, or negative.
  • the function lg(x) may therefore be computed as shown in table 2-8, for values of the input operand x>zero.
  • the function lg(x) is not defined for values of the input operand x ⁇ zero.
  • the function lg(x+1) may therfore be computed as shown in table 2-10, for values of the input operand x>1/4.
  • Table 3-1 shows a set of experimental latency times for computing transcendental functions, comparing latency times for a processor including a floating-point unit according to the invention with the "Pentium" processor available from Intel Corporation of Santa Clara, Calif. As shown in table 3-1, the floating-point unit according to the invention is in most cases much faster than the Pentium processor.

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  • Engineering & Computer Science (AREA)
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  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
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  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
US08/768,781 1996-12-17 1996-12-17 Apparatus for computing transcendental functions quickly Expired - Lifetime US5963460A (en)

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Application Number Priority Date Filing Date Title
US08/768,781 US5963460A (en) 1996-12-17 1996-12-17 Apparatus for computing transcendental functions quickly
EP97310118A EP0849664B1 (fr) 1996-12-17 1997-12-15 Appareil à calculer rapidement des functions transcendentaux
DE69712720T DE69712720T2 (de) 1996-12-17 1997-12-15 Gerät zur schnellen Berechnung tranzedentaler Funktionen
JP9344758A JPH10214176A (ja) 1996-12-17 1997-12-15 超越関数を迅速に計算する装置
US09/267,330 US6317764B1 (en) 1996-12-17 1999-03-12 Apparatus for computing transcendental functions quickly
US10/012,660 US6581079B2 (en) 1996-12-17 2001-11-12 Apparatus for computing transcendental functions quickly

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Cited By (19)

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US6317764B1 (en) * 1996-12-17 2001-11-13 Stmicroelectronics, Inc. Apparatus for computing transcendental functions quickly
US6581079B2 (en) * 1996-12-17 2003-06-17 Stmicroelectronics, Inc. Apparatus for computing transcendental functions quickly
US6363405B1 (en) 1997-12-24 2002-03-26 Elbrus International Limited Computer system and method for parallel computations using table approximation methods
US6567831B1 (en) * 1997-12-24 2003-05-20 Elbrus International Limited Computer system and method for parallel computations using table approximation
US6240433B1 (en) * 1998-02-02 2001-05-29 International Business Machines Corporation High accuracy estimates of elementary functions
US6581085B1 (en) * 1999-05-12 2003-06-17 Ati International Srl Approximation circuit and method
US20030217022A1 (en) * 2002-05-16 2003-11-20 Giampietro Tecchiolli Electronic device to calculate and generate linear and non-linear functions
US7290020B2 (en) * 2002-05-16 2007-10-30 Neuricam Spa Electronic device to calculate and generate linear and non-linear functions
US20070124357A1 (en) * 2003-12-03 2007-05-31 Marvell International Ltd. Methods and apparatus fro performing calculations using reduced-width data
US7555508B2 (en) * 2003-12-03 2009-06-30 Marvell World Trade Ltd. Methods and apparatus for performing calculations using reduced-width data
US20090265408A1 (en) * 2003-12-03 2009-10-22 Marvell World Trade Ltd. Methods and apparatus for performing calculations using reduced-width data
US8275819B2 (en) 2003-12-03 2012-09-25 Marvell World Trade Ltd. Methods and apparatus for performing calculations using reduced-width data
US20060224648A1 (en) * 2005-03-30 2006-10-05 Lockheed Martin Corporation Method and apparatus for providing a base-2 logarithm approximation to a binary number
US7606850B2 (en) 2005-03-30 2009-10-20 Lockheed Martin Corporation Method and apparatus for providing a base-2 logarithm approximation to a binary number
US20080005211A1 (en) * 2006-06-26 2008-01-03 Matula David W Determining A Table Output Of A Table Representing A Hierarchical Tree For An Integer Valued Function
US7962537B2 (en) * 2006-06-26 2011-06-14 Southern Methodist University Determining a table output of a table representing a hierarchical tree for an integer valued function
US20100332573A1 (en) * 2009-06-30 2010-12-30 Fujitsu Limited Processing unit
US8533248B2 (en) * 2009-06-30 2013-09-10 Fujitsu Limited Processing unit
US9875084B2 (en) 2016-04-28 2018-01-23 Vivante Corporation Calculating trigonometric functions using a four input dot product circuit

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US6581079B2 (en) 2003-06-17
DE69712720D1 (de) 2002-06-27
EP0849664A2 (fr) 1998-06-24
DE69712720T2 (de) 2003-02-13
JPH10214176A (ja) 1998-08-11
US20020087608A1 (en) 2002-07-04
EP0849664B1 (fr) 2002-05-22

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