US6498509B2 - Device to control the power supply in an integrated circuit comprising electrically programmable non-volatile memory elements - Google Patents

Device to control the power supply in an integrated circuit comprising electrically programmable non-volatile memory elements Download PDF

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Publication number
US6498509B2
US6498509B2 US09/896,817 US89681701A US6498509B2 US 6498509 B2 US6498509 B2 US 6498509B2 US 89681701 A US89681701 A US 89681701A US 6498509 B2 US6498509 B2 US 6498509B2
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voltage reference
transistor
voltage
integrated circuit
programming
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US09/896,817
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US20020018367A1 (en
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Richard Fournel
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Bell Semiconductor LLC
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STMicroelectronics SA
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Assigned to STMICROELECTRONICS INTERNATIONAL N.V. reassignment STMICROELECTRONICS INTERNATIONAL N.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STMICROELECTRONICS, INC.
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits

Definitions

  • the present invention relates to the field of integrated circuits, and more particularly, to a device for controlling a power supply in an integrated circuit comprising electrically programmable non-volatile memory elements.
  • each part will receive the corresponding optimum supply voltage. It is possible for example to have an integrated circuit with one part that is supplied at 3.3 volts while the other part is supplied at 1.8 volts depending on the thickness of the oxides in each part. Usually, the integrated circuit then receives an external logic supply voltage that is the highest supply level, i.e., 3.3 volts in the example. A voltage divider is provided in the circuit to provide the lowest supply level, 1.8 volts in the example. This divider is such that it is capable of withstanding the highest voltage level.
  • Integrated circuits based on submicron technologies may comprise an electrically programmable non-volatile memory, such as for example, EEPROM, EPROM, flash EPROM or other similar memories.
  • Memories of this kind use voltage levels, for their programming, that are greater than the logic supply voltages of the integrated circuits. These programming voltage levels depend essentially on the technology considered.
  • This circuitry includes, for example, a voltage adder or multiplier type circuit.
  • the integrated circuits typically receive this high voltage permanently at an external pin.
  • the oxides are particularly thin. Even when using the greatest thickness available in the technology considered, it would have to be ensured that each oxide to be protected has a cascode type protection element so that the reliability is not reduced. For reasons of complexity, functionality and cost, an approach of this kind is not satisfactory.
  • a power supply control device such that the elements of the selection and programming circuit associated with the non-volatile memory elements are powered by the logic power voltage at least outside the programming cycle.
  • the selection and programming circuit associated with the non-volatile memory elements are subjected to programming voltage levels only during the programming cycles. For the remainder of the time, they receive the lower level logic power voltage without in any way endangering the submicron oxides. Thus, the time of exposure to the programming voltage levels is significantly reduced. The reliability of the integrated circuits comprising a power supply control device of this kind is greatly improved.
  • a power supply control device has two voltage selector switches, one to switch over the high voltage and the other to switch over the logic supply voltage to a power supply input node of the selection and programming circuitry associated with the memory elements. These selection switches are controlled in a complementary way by a voltage level translator connected between the high voltage and ground. This translator is controlled by a binary control signal generated internally by the integrated circuit. The active level of this control signal, used to switch over the high voltage, may correspond to a cycle for writing elements of the non-volatile memory. Outside the writing cycle, this control signal is at its inactive level, which is the supply voltage that is switched over to the input supply node of the selection and programming circuitry.
  • the level translator is sized so that it can switch over at very high speed, so that it is possible to switch over the high voltage at each change in programming address, to carry out the programming operation at this address and then switch the supply voltage over during the read verification of this programming operation.
  • the time of exposure to the high voltage is reduced to the maximum.
  • the invention therefore relates to an integrated circuit comprising electrically programmable non-volatile memory elements and an associated selection and programming circuitry.
  • the integrated circuit includes as supply voltages, a ground reference voltage, at least one logic supply voltage and a high voltage.
  • the high voltage is used to give the voltage levels needed for the programming of one or more non-volatile memory elements.
  • this integrated circuit furthermore comprises a voltage control device applied to a power input node of the selection and programming circuitry to apply either the high voltage or a logic supply voltage as a function of a programming control signal.
  • FIG. 1 is a block diagram of an integrated circuit based on submicron technology comprising non-volatile memory elements and a power control device according to the present invention
  • FIG. 2 is a detailed diagram of an embodiment of the power control device illustrated in FIG. 1;
  • FIG. 3 is a block diagram of an alternative embodiment of a power control device in an integrated circuit with two logic supply voltages according to the present invention.
  • FIG. 4 is a diagram of the circuit that generates the control signal for the power control device according to the present invention.
  • FIG. 1 is a block diagram of an integrated circuit 1 using submicron technology.
  • the integrated circuit 1 receives via external pins a ground reference Gnd, a logic supply voltage Vdd and a high voltage HV.
  • This integrated circuit 1 has logic circuitry 2 , which is not shown in detail, that may comprise for example a microprocessor and ROM, RAM or other type memories, as well as an electrically programmable non-volatile memory MEM and an associated selection and programming circuitry 3 .
  • the selection and programming circuitry 3 receives, in addition to the logic supply voltage Vdd and ground Gnd, a voltage applied by a control device 5 according to the present invention to a power input node N. Depending on whether the operation is in a write (or programming) cycle, this node receives the high voltage HV or the logic supply voltage Vdd.
  • the control device 5 is controlled by a binary control signal IN generated internally by the logic circuitry 2 .
  • the input node N of the selection and programming circuitry 3 is taken to the high voltage HV only during the writing and programming cycles. Outside these cycles, the node N is taken to the logic supply voltage Vdd.
  • the control device 5 has two selection switches 51 and 52 .
  • a first selection switch 51 is connected between the high voltage HV and the power input node N of the selection and programming circuitry 3 .
  • a second selection switch 52 is connected between the power supply voltage Vdd and the node N.
  • the two selection switches 51 and 52 are controlled by means 50 in a complementary way so that only one is closed at a given point in time, to apply the associated voltage to the input node N.
  • the means 50 are, in practice, a level translator capable of providing a binary signal at an output.
  • the two high and low levels of this binary signal corresponds respectively at least to the level of the high voltage HV to be switched over and at most to the level of the logic supply voltage Vdd to be switched over.
  • FIG. 2 An exemplary embodiment of a control device according to the present invention is shown in detail in FIG. 2 .
  • the translator 50 is controlled by the binary control signal IN. It is powered between the high voltage HV and ground Gnd. In order that this translator may not be damaged by the high voltage, it must have a protection stage of at least one cascode stage. This protection stage is used to limit the internal nodes of the translator to intermediate voltage levels, so that no transistor of the translator receives an excessively high voltage at its terminals.
  • the translator 50 has two cascode stages and one circuit REF for the generation of the reference voltages of the cascode stages.
  • the translator in each of its two arms, has four series-connected transistors between the high voltage HV and ground.
  • Each arm includes a load transistor connected to the high voltage, a selection switch transistor connected to ground and controlled by the binary control signal or its inverse and two cascode transistors.
  • One of the cascode transistors is to protect the load transistor and the other is to protect the selection switch transistor.
  • the selection switch transistors are N-type transistors and have their sources connected to ground.
  • the load transistors are P-type transistors and each of them has its source connected to the high voltage HV and its gate connected to the drain of the load transistor of the other arm.
  • the first arm thus has, in series between the high voltage and ground a P-type load transistor M 1 , a P-type cascode transistor M 5 , an N-type cascode transistor M 7 and an N-type selection switch transistor M 3 .
  • the second arm is similar to the first arm and includes a P-type load transistor M 2 , a P-type cascode transistor M 6 , an N-type cascode transistor M 8 and an N-type selection switch transistor M 4 .
  • the control device 5 has a circuit REF for the generation of reference voltages V REF N and V REFp to control the gates of the N-type and P-type cascode transistors.
  • the circuit REF has three MOS transistors M 9 , M 10 , M 11 series-connected between the high voltage HV and ground. These three transistors operate as resistors since each of them has its gate connected to its drain. In the example, they are P-type transistors.
  • the reference voltages V REF N and V REFp are obtained by taking the voltage on either side of the middle transistor M 10 .
  • each cascode transistor limits the voltage swings at its terminals.
  • the source of each P-type cascode transistor cannot fall below V REFp +Vt p , where Vt p is the threshold voltage of the P type cascode transistor.
  • the source of each N-type cascode transistor cannot rise above VREF N ⁇ Vt n , where Vt n is the threshold voltage of the N-type cascode transistor.
  • the transistor 52 may be efficiently turned off, while its drain, connected to the node N, is at the high voltage HV and its source is connected to the logic supply voltage Vdd, it is necessary to apply, to its gate, at most the level of the voltage of its source, namely a maximum of 3.3 volts.
  • the value of the low level of the output OUT of the translator is obtained by appropriately sizing the transistors of the reference circuit of the cascode transistors. In the example, it is therefore necessary to size the reference circuit so that V REFp — +Vt is in the range of 3 volts. It will be noted that the substrate effect received by the transistor 52 facilitates turning this transistor 52 off.
  • the control signal IN of the power supply control device may come from any part of the integrated circuit. If it is given by the circuit powered at the logic supply voltage Vdda, which is 1.8 volts in the example, the two voltage levels of the signal IN are then at 1.8 volts and 0 volts. If it is given by the part powered at the logic supply voltage Vdd, which is 3.3 volts in the example, the two voltage levels of the signal IN are then at 3.3 volts and 0 volts.
  • the logic supply voltage switched over to the input node N of the selection and programming circuitry 3 may be the logic supply voltage Vdd or the second logic supply voltage Vdda, independently of the logic associated with the control signal IN.
  • the translator of the control device is then adapted to provide, at its output OUT, the levels needed to make the transistors 51 and 52 switch over properly. More specifically, the cascode reference circuit of the translator is then sized to give a low level of the signal OUT that is a level at most equal to Vdda.
  • the control and address signals it is possible to apply the high voltage only during the active programming phase.
  • the changes in address in the programming phases are performed at low voltage.
  • the translator 50 has to be sized to obtain a very fast switching time.
  • the application time of the high voltage HV on the supply input node of the selection and programming circuitry 3 is reduced to the necessary minimum.
  • the integrated circuitry is protected to the maximum against the effects of stress due to high voltage, at low cost for the integrated circuit, since only the control device will permanently receive the high voltage applied to it.
  • the application can be applied especially when the high voltage is applied to the integrated circuit on an external pin, but also when it is given internally by a charge pump type of circuit for example.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
US09/896,817 2000-06-30 2001-06-29 Device to control the power supply in an integrated circuit comprising electrically programmable non-volatile memory elements Expired - Lifetime US6498509B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0008548A FR2811131A1 (fr) 2000-06-30 2000-06-30 Dispositif de controle d'alimentation dans un circuit integre comprenant des elements de memoire non volatile electriquement programmable
FR0008548 2000-06-30

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US6498509B2 true US6498509B2 (en) 2002-12-24

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6717456B2 (en) * 2001-12-21 2004-04-06 Texas Instruments Incorporated Level conversion circuit
US20070257724A1 (en) * 2006-05-08 2007-11-08 Sony Corporation Level conversion circuit and input-output device using same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8145317B2 (en) * 2002-04-08 2012-03-27 Ardian, Inc. Methods for renal neuromodulation

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4694430A (en) 1985-03-21 1987-09-15 Sprague Electric Company Logic controlled switch to alternate voltage sources
US4835423A (en) 1986-11-21 1989-05-30 Thomson Semiconducteurs MOS technology voltage switch-over circuit
US4837744A (en) 1986-11-04 1989-06-06 Thomson Semiconducteurs Integrated circuit of the logic circuit type comprising an electrically programmable non-volatile memory
US5293561A (en) 1991-02-15 1994-03-08 Nec Corporation Write-in voltage source incorporated in electrically erasable programmable read only memory device with redundant memory cell array
EP0657890A2 (fr) 1993-12-08 1995-06-14 AT&T Corp. Composants à haute tension pour système EEPROM
US6055205A (en) * 1999-03-05 2000-04-25 Xilinx, Inc. Decoder for a non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2797119B1 (fr) * 1999-07-30 2001-08-31 St Microelectronics Sa Dispositif de commande d'un commutateur haute tension de type translateur

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4694430A (en) 1985-03-21 1987-09-15 Sprague Electric Company Logic controlled switch to alternate voltage sources
US4837744A (en) 1986-11-04 1989-06-06 Thomson Semiconducteurs Integrated circuit of the logic circuit type comprising an electrically programmable non-volatile memory
US4835423A (en) 1986-11-21 1989-05-30 Thomson Semiconducteurs MOS technology voltage switch-over circuit
US5293561A (en) 1991-02-15 1994-03-08 Nec Corporation Write-in voltage source incorporated in electrically erasable programmable read only memory device with redundant memory cell array
EP0657890A2 (fr) 1993-12-08 1995-06-14 AT&T Corp. Composants à haute tension pour système EEPROM
US6055205A (en) * 1999-03-05 2000-04-25 Xilinx, Inc. Decoder for a non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6717456B2 (en) * 2001-12-21 2004-04-06 Texas Instruments Incorporated Level conversion circuit
US20070257724A1 (en) * 2006-05-08 2007-11-08 Sony Corporation Level conversion circuit and input-output device using same
US7511555B2 (en) * 2006-05-08 2009-03-31 Sony Corporation Level conversion circuit and input-output device using same

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US20020018367A1 (en) 2002-02-14
EP1168364A1 (fr) 2002-01-02
FR2811131A1 (fr) 2002-01-04

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