US7026190B2 - Method of manufacturing circuit device - Google Patents

Method of manufacturing circuit device Download PDF

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Publication number
US7026190B2
US7026190B2 US10/211,758 US21175802A US7026190B2 US 7026190 B2 US7026190 B2 US 7026190B2 US 21175802 A US21175802 A US 21175802A US 7026190 B2 US7026190 B2 US 7026190B2
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US
United States
Prior art keywords
manufacturing
circuit device
conductive pattern
block
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime, expires
Application number
US10/211,758
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English (en)
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US20030040138A1 (en
Inventor
Yoshiyuki Kobayashi
Noriaki Sakamoto
Kouji Seki
Kouji Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001255474A external-priority patent/JP4708625B2/ja
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Assigned to SANYO ELECTRIC CO., LTD. reassignment SANYO ELECTRIC CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KOBAYASHI, YOSHIYUKI, SAKAMOTO, NORIAKI, SEKI, KOUJI, TAKAHASHI, KOUJI
Publication of US20030040138A1 publication Critical patent/US20030040138A1/en
Application granted granted Critical
Publication of US7026190B2 publication Critical patent/US7026190B2/en
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC reassignment SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC ASSIGNMENT OF 50% INTEREST Assignors: SANYO ELECTRIC CO., LTD.
Assigned to DEUTSCHE BANK AG NEW YORK BRANCH reassignment DEUTSCHE BANK AG NEW YORK BRANCH SECURITY INTEREST Assignors: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Assigned to DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT reassignment DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Assignors: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Adjusted expiration legal-status Critical
Assigned to FAIRCHILD SEMICONDUCTOR CORPORATION, SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC reassignment FAIRCHILD SEMICONDUCTOR CORPORATION RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Assignors: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/042—Etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7438—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07502—Connecting or disconnecting of bond wires using an auxiliary member
    • H10W72/07504—Connecting or disconnecting of bond wires using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
    • H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present invention relates to a method of manufacturing a circuit device, particularly to a method of manufacturing a circuit device of thin type not needing a supporting substrate.
  • a first electrode 7 , a second electrode 8 , and die pad 9 are formed at the front face of the glass epoxy 5 , and the rear face, a first rear face electrode 10 and a second rear face electrode 11 are formed.
  • the first electrode 7 and the first rear face electrode 10 , and the second electrode 8 and the second rear face electrode 11 are connected electrically through through-holes TH.
  • the bare transistor chip T is fixed at the die pad 9 , the emitter electrode of the transistor chip T and the first electrode 7 are connected through a metal fine wire 12 , and the base electrode of the transistor chip T and the second electrode 8 are connected through a metal fine wire 12 .
  • the resin layer 13 is provided on the glass epoxy substrate 5 so as to cover the transistor chip T.
  • the CSP 6 is mounted on the printed circuit board PS as shown in FIG. 13 .
  • the printed circuit board PS electrodes and wiring forming an electric circuit are provided, and the CSP 6 , the package type semiconductor device 1 , chip resistors CR, or chip capacitors CC are connected electrically and fixed.
  • the emitter electrode of the transistor chip T and the first electrode 7 , and the base electrode of the transistor chip T and the second electrode 8 are connected through the metal fine wires 12 , and covered with the resin layer 13 . (See FIG. 15D )
  • the glass epoxy substrate 5 being the supporting substrate is needless originally as described above. However, on the method of manufacturing, the substrate is adopted as a supporting substrate to bond the electrodes, so it is not possible to remove the glass epoxy substrate 5 .
  • FIGS. 9A and 9B are views explaining a method of manufacturing a circuit device of the invention.
  • FIG. 10 is a view explaining a circuit device of the invention.
  • FIG. 13 is a view explaining a method of mounting a conventional circuit device
  • a conductive pattern is formed by three flows: Cu foil; Ag plating; and half-etching. Mounting the circuit elements on each mounting portion and connection between the electrodes of the circuit elements and the conductive pattern are performed by two flows of die bonding and wire bonding.
  • the common molding member performing molding a block providing plural mounting portions using one die cavity.
  • In the flow of removing rear face Cu foil whole area of the rear face of the conductive foil is etched until the insulating resin is exposed.
  • electrode treatment of the conductive pattern exposed at the rear face is performed.
  • judge of quality and classing characteristic rank of the circuit elements attached in each mounting portion are performed.
  • dicing separation to individual circuit element from the insulation resin by dicing.
  • a first process of the invention is to form a conductive pattern 51 by providing a conductive foil 60 , and by forming a isolation trench 61 having shallower thickness than that of the conductive foil 60 at the conductive foil 60 of area except a conductive pattern 51 forming at least many mounting portions of circuit elements 52 as shown in FIG. 2A to FIG. 4B .
  • a sheet shaped conductive foil 60 is provided first as FIG. 2A .
  • Material of the conductive foil 60 is selected in consideration of adhesion, bonding, and plating qualities of brazing material, then, conductive foil being Cu as a main material, conductive foil being Al as a main material, or conductive foil made of alloy of Fe—Ni is used.
  • the sheet shaped conductive foil 60 may be provided wound in roll shape, for example, with 45 mm to transfer to each process described later, and the rectangular shaped conductive foil 60 cut in the predetermined size may be provided to transfer to each process described later.
  • the circuit elements 52 are semiconductor element such as transistor, diode, IC chip, and passive elements such as chip capacitor, chip resistor, and the like.
  • Semiconductor elements of facedown such as CSP, BGA, and the like can be mounted though thickness of the device becomes thick.
  • the insulating resin 50 covers entirely circuit elements 52 A and 52 B, and plural conductive patterns 51 A, 51 B, and 51 C, and the insulating resin 50 connects strongly fixing to curved structures of side faces of the conductive patterns 51 A, 51 B, and 51 C filled with the insulating resin 50 at the isolation trench 61 between conductive patterns 51 as shown in FIG. 9A . Then the conductive pattern 51 is supported by the insulation resin 50 .
  • Thickness of the insulating resin 50 covered on surface of the conductive foil 60 is adjusted so as to cover about 100 ⁇ m from the top portion of the metal fine wire 55 A of the circuit element 52 . It is possible to make the thickness thick or thin.
  • test of the property is performed before separating to individual circuit device by dicing in the process, it is possible to perform test of the property after dicing as the circuit device is in the state bonded at the sheet even when dicing is performed in the invention.
  • a seventh process of the invention is to separate the insulating resin 50 at every mounting portion 65 by dicing as shown in FIG. 12 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)
US10/211,758 2001-08-27 2002-08-02 Method of manufacturing circuit device Expired - Lifetime US7026190B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPP.2001-255474 2001-08-27
JP2001255474A JP4708625B2 (ja) 2001-04-26 2001-08-27 ボンディング装置およびそれを用いた半導体装置の製造方法

Publications (2)

Publication Number Publication Date
US20030040138A1 US20030040138A1 (en) 2003-02-27
US7026190B2 true US7026190B2 (en) 2006-04-11

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US10/211,758 Expired - Lifetime US7026190B2 (en) 2001-08-27 2002-08-02 Method of manufacturing circuit device

Country Status (4)

Country Link
US (1) US7026190B2 (ko)
KR (1) KR20030019082A (ko)
CN (1) CN1211848C (ko)
TW (1) TW538658B (ko)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050214981A1 (en) * 2004-03-24 2005-09-29 Jun Sakano Circuit device and manufacturing method thereof
US20080196226A1 (en) * 2007-02-20 2008-08-21 Texas Instruments Incorporated Transfer mask in micro ball mounter
US20090134201A1 (en) * 2006-04-20 2009-05-28 Riki Jindo Work Clamp and Wire Bonding Apparatus
US20090230524A1 (en) * 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof
US20100044843A1 (en) * 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
US20100258934A1 (en) * 2009-04-10 2010-10-14 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
US20110163430A1 (en) * 2010-01-06 2011-07-07 Advanced Semiconductor Engineering, Inc. Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods

Families Citing this family (9)

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WO2004010751A1 (ja) * 2002-07-18 2004-01-29 Hitachi Chemical Co., Ltd. 多層配線板、およびその製造方法、ならびに半導体装置および無線電子装置
US7256486B2 (en) * 2003-06-27 2007-08-14 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Packaging device for semiconductor die, semiconductor device incorporating same and method of making same
US7919787B2 (en) * 2003-06-27 2011-04-05 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Semiconductor device with a light emitting semiconductor die
US7279355B2 (en) * 2003-06-27 2007-10-09 Avago Technologies Ecbuip (Singapore) Pte Ltd Method for fabricating a packaging device for semiconductor die and semiconductor device incorporating same
US7182793B2 (en) * 2004-01-22 2007-02-27 Asm Technology Singapore Pty Ltd. System for reducing oxidation of electronic devices
US7246434B1 (en) * 2004-10-11 2007-07-24 Pericom Semiconductor Corp. Method of making a surface mountable PCB module
US20090068797A1 (en) * 2005-07-21 2009-03-12 Chipmos Technologies Inc. Manufacturing process for a quad flat non-leaded chip package structure
TWI294674B (en) * 2005-12-06 2008-03-11 Subtron Technology Co Ltd High thermal conducting circuit substrate and manufacturing process thereof
KR20140113964A (ko) * 2012-12-14 2014-09-25 아사히 가세이 일렉트로닉스 가부시끼가이샤 자기 센서 및 자기 센서 장치, 자기 센서의 제조 방법

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US6562660B1 (en) * 2000-03-08 2003-05-13 Sanyo Electric Co., Ltd. Method of manufacturing the circuit device and circuit device
US6596564B2 (en) * 2000-09-06 2003-07-22 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US6624511B2 (en) * 2000-06-08 2003-09-23 Sanyo Electric Co., Ltd. Hybrid integrated circuit device

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US6715659B2 (en) * 1996-01-26 2004-04-06 Micron Technology, Inc. Apparatus for clamping semiconductor devices using sliding finger supports
US5890644A (en) * 1996-01-26 1999-04-06 Micron Technology, Inc. Apparatus and method of clamping semiconductor devices using sliding finger supports
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Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7329957B2 (en) * 2004-03-24 2008-02-12 Sanyo Electric Co., Ltd. Circuit device and manufacturing method thereof
US20050214981A1 (en) * 2004-03-24 2005-09-29 Jun Sakano Circuit device and manufacturing method thereof
US20090134201A1 (en) * 2006-04-20 2009-05-28 Riki Jindo Work Clamp and Wire Bonding Apparatus
US7975899B2 (en) * 2006-04-20 2011-07-12 Kaijo Corporation Work clamp and wire bonding apparatus
US7882625B2 (en) * 2007-02-20 2011-02-08 Texas Instruments Incoporated Transfer mask in micro ball mounter
WO2008103714A3 (en) * 2007-02-20 2008-12-04 Texas Instruments Inc Transfer mask in micro-ball mounter
US20080196226A1 (en) * 2007-02-20 2008-08-21 Texas Instruments Incorporated Transfer mask in micro ball mounter
US20090230524A1 (en) * 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof
US20090230525A1 (en) * 2008-03-14 2009-09-17 Pao-Huei Chang Chien Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof
US8120152B2 (en) 2008-03-14 2012-02-21 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof
US8492883B2 (en) 2008-03-14 2013-07-23 Advanced Semiconductor Engineering, Inc. Semiconductor package having a cavity structure
US8115285B2 (en) 2008-03-14 2012-02-14 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof
US20100044843A1 (en) * 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
US8237250B2 (en) 2008-08-21 2012-08-07 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
US20100258934A1 (en) * 2009-04-10 2010-10-14 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US8106492B2 (en) 2009-04-10 2012-01-31 Advanced Semiconductor Engineering, Inc. Semiconductor package and manufacturing method thereof
US20110163430A1 (en) * 2010-01-06 2011-07-07 Advanced Semiconductor Engineering, Inc. Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods

Also Published As

Publication number Publication date
CN1211848C (zh) 2005-07-20
KR20030019082A (ko) 2003-03-06
TW538658B (en) 2003-06-21
US20030040138A1 (en) 2003-02-27
CN1402320A (zh) 2003-03-12

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