US8951885B2 - Insulation wall between transistors on SOI - Google Patents

Insulation wall between transistors on SOI Download PDF

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Publication number
US8951885B2
US8951885B2 US13/571,603 US201213571603A US8951885B2 US 8951885 B2 US8951885 B2 US 8951885B2 US 201213571603 A US201213571603 A US 201213571603A US 8951885 B2 US8951885 B2 US 8951885B2
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Prior art keywords
trench
semiconductor substrate
layer
width
wall
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US13/571,603
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US20130049163A1 (en
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David Barge
Pierre Morin
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STMicroelectronics Crolles 2 SAS
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STMicroelectronics Crolles 2 SAS
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Assigned to STMICROELECTRONICS (CROLLES 2) SAS reassignment STMICROELECTRONICS (CROLLES 2) SAS ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BARGE, DAVID, MORIN, PIERRE
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    • H01L21/76283—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

  • the present invention relates to the lateral insulation between transistors formed on a substrate of semiconductor on insulator or SOI type.
  • FIGS. 1A to 1D An insulation structure between two transistors of complementary type is shown in FIGS. 1A to 1D .
  • FIGS. 1A and 1C are to views and FIGS. 1B and ID are cross-section views along planes BB and D-D defined in FIGS. 1A and IC.
  • the case of an SOI structure comprising a thin silicon layer 1 on a thin silicon oxide layer 2 on a silicon substrate 2 is here considered.
  • trenches 4 are made to cross layers 1 and 2 and to penetrate into substrate 3 . Trenches 4 further delimit wells 3 a and 3 b of opposite doping, shallower than trenches 4 and arranged under each of the active areas. Trenches 4 are filled with silicon oxide, commonly called field oxide 5 , to form insulation walls.
  • transistors 6 comprise, between drain and source regions 7 , a conductive gate 10 insulated by a layer 8 .
  • Spacers 9 are formed on either side of the gate.
  • Source and drain regions 7 axe formed after the gate, for example by transforming into silicide the apparent portions of this layer 1 . Simultaneously, the upper portion of gate 10 a is silicided.
  • FIG. 2 shows trench 4 filled with an insulator 5 . Further, an insulating layer 5 a formed above insulator and protrudes on either side of the trench.
  • an embodiment provides an insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.
  • the thin layer is made of silicon, germanium, or silicon-germanium; the insulating layer is and the insulating material of the wall are made of silicon oxide; and the substrate is made of silicon.
  • the wall insulates doped wells formed in the substrate under each transistor, and the thin semiconductor layer has a thickness ranging from 5 to 15 nm, the insulating layer has a thickness ranging from 10 to 30 nm, the wells have a depth ranging between 0.5 and 1 ⁇ m, the wall has a width ranging from 50 to 100 nm, and the lateral extensions have a width ranging between 5 and 10 nm and a height ranging between 5 and 10 nm.
  • An embodiment provides a method for manufacturing an insulating wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, comprising the steps of:
  • the protection of the sides is performed during said partial etching.
  • the side protection is performed after said partial etching and comprises the steps of: conformally depositing an insulator and removing the portion of this insulator which rests on the bottom of the opening.
  • the insulator is silicon nitride.
  • said removal of a portion of the silicon substrate is performed by isotropic etching.
  • said removal of a portion of the silicon substrate is performed by oxidizing the silicon.
  • FIGS. 1A and 1C previously described, are top views of two steps of the manufacturing of an insulation wall between active areas, and FIGS. 1B and 1D are cross-section views respectively corresponding to cross-section planes BB and DD of FIGS. 1A and 1C ;
  • FIG. 2 previously described, illustrates an alternative insulation wall between active areas
  • FIGS. 3A and 3B are cross-section views illustrating an insulation wall between active areas, respectively before and after the forming of transistors in the active areas;
  • FIGS. 4A to 4E illustrate successive steps of the forming of a wall such as that in FIG. 3A according to a first embodiment
  • FIGS. 5A to 5D illustrate successive steps of the forming of a wall such as that in FIG. 3A according to a second embodiment.
  • FIG. 3A shows an insulation wall between active areas of an integrated circuit.
  • This insulation wall is intended to delimit active areas in a thin semiconductor layer 1 formed on an insulator 2 resting on a substrate 3 , generally a silicon substrate.
  • a substrate 3 generally a silicon substrate.
  • Under the left-hand active area is formed a well of a first conductivity type 3 a and under the right-hand active area is formed a well of a second conductivity type 3 b .
  • the insulation wall is formed of a vertical portion 21 crossing layers 1 and 2 and well 3 a to reach substrate 3 .
  • This wall comprises lateral extensions 23 extending on either side of vertical portion 21 under a portion of insulating layer 2 .
  • FIG. 3B illustrates the shape of the structure after the forming of components such as MOS transistors 6 in active areas located to the right and to the left of the drawing.
  • the various elements of these MOS transistors are designated with the same reference numerals as in FIG. 1D .
  • cavities generally form at the outer limits of the wall at the level of its interfaces with adjacent layers. Such cavities comprise a first portion 25 along silicon layer 1 and along insulating layer 2 . Then, the cavities risk having a lateral extension 26 under insulating layer 2 . However, given the presence of lateral extensions 23 of the insulation wall, the risk for these cavities to join well 3 a or 3 b is extremely limited.
  • Another advantage of a wall of the type in FIG. 3A is that is does not limit the available surface area at the level of each of the active areas.
  • FIG. 3A Another advantage of a wall of the type in FIG. 3A is as will be described hereafter, that it may he obtained by a particularly simple manufacturing method especially implying no additional masking step with respect to the forming of a simple wall such as that in FIGS. 1A and 1B .
  • FIGS. 4A to 4E illustrate a first embodiment of a trench having a structure illustrated in FIG. 1A .
  • FIG. 4A it is started from an SOI-type structure comprising, on a semiconductor substrate 3 , a thin insulating layer 2 and a thin semiconductor layer 1 .
  • the assembly is coated with a masking layer 30 , for example, a silicon nitride layer.
  • a trench 32 crossing successive layers 30 , 1 , 2 and reaching substrate 3 has been defined by masking and etched.
  • a protection layer 34 has been formed on the sides of trench 32 .
  • This protection layer may be formed by one of many known means. For example, a silicon nitride layer may be uniformly deposited, after which a anisotropic etching may be performed, which results in silicon nitride remaining on the side and in the removal of the silicon nitride from the bottom of the trench.
  • an isotropic etching of substrate 3 has been performed down to a depth e.
  • the opening extends across a width w substantially equal to e.
  • a new anisotropic etching is performed across a width W defined by the dimensions of mask 30 , that is, substantially the same width as the initial width of trench 32 described in relation with FIG. 4B .
  • This thus provides, after filling with an insulating material, a wall such as that illustrated in relation with FIG. 3A having on the most part of its height a width W and having on a small part of its height, just under insulating layer 2 , lateral extensions having a width w.
  • protection layer 34 has not been shown in FIG. 4D . It should be noted that protection layer 34 may or not be removed, and that if it is removed, this may he done immediately after the isotropic etching described in relation with FIG. 4D or just before the trench filling after its deepening illustrated in relation with FIG. 4E . According to the moment when this removal is carried out, the trench widths may be slightly modified.
  • FIGS. 5A to 5D show another way to form a wall such as in FIG. 3A .
  • FIG. 5A is identical to FIG. 4C .
  • a thermal oxidation is carried out to oxidize an area 41 down to a depth e, area 41 extending under the remaining portion of insulating layer 2 across a width w.
  • the trench which then has a width W substantially equal to the width of the opening initially formed in masking layer 30 , is deepened.
  • the trench is filled with an insulating material, currently silicon oxide 43 .
  • Next steps, not shown, for obtaining the wall of FIG. 3A will for example comprise removing masking layer 30 and the upper portion of oxide layer 43 by chem.-mech. polishing.
  • spacer structure 34 is no longer shown in FIG. 5C . It should be understood that the spacer may be removed before or after the deepening of the trench illustrated in FIG. 5C , or else that this spacer may be left in place. It should be understood that the widths are not exactly the same according to whether spacer structure 34 has or not been left in place but the results are quite equivalent, the important point being the existence of lateral extensions of the trench across a width w.
  • an SOI-type structure has been previously described as comprising a silicon layer on a thin silicon oxide layer, itself formed on a silicon substrate, other materials may be used.
  • the thin insulating layer may be an insulating material other than silicon oxide, for example, sapphire or diamond, and semiconductor layer 1 may be made of a semiconductor material other than silicon, for example, germanium or silicon-germanium.
  • the insulating material filling the previously-described trench has always been indicated as being silicon oxide, it will be understood by those skilled in the art that any adapted insulating material may be used.
  • the integrated circuits comprise biasing wells under at least some of the active areas, the insulation walls will penetrate into the substrate beyond the bottom of these wells.
  • the structure according to the present invention is particularly well adapted to integrated circuit manufacturing technologies where the active areas have a width ranging from 60 to 100 nm, the biasing wells formed under the active components have a depth approximately ranging from 100 to 150 nm, the trenches have a depth on the order of 250 nm and a width approximately ranging from 50 to 100 nm, the lateral extensions under the oxide layer approximately reaching a length between 20 and 50 nm, insulating layer 2 having a thickness approximately ranging from 10 to 25 nm, and semiconductor layer 1 having a thickness approximately ranging from 10 to 25 nm.

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  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
US13/571,603 2011-08-29 2012-08-10 Insulation wall between transistors on SOI Active 2032-12-04 US8951885B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/605,064 US9269768B2 (en) 2011-08-29 2015-01-26 Insulation wall between transistors on SOI

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR1157596A FR2979477A1 (fr) 2011-08-29 2011-08-29 Mur d'isolement entre transistors sur soi
FR11/57596 2011-08-29
FR1157596 2011-08-29

Related Child Applications (1)

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US14/605,064 Division US9269768B2 (en) 2011-08-29 2015-01-26 Insulation wall between transistors on SOI

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US8951885B2 true US8951885B2 (en) 2015-02-10

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Publication number Priority date Publication date Assignee Title
FR2995137B1 (fr) 2012-09-05 2015-12-11 Commissariat Energie Atomique Dispositif microelectronique a tranchees d'isolation debordant sous une zone active

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5910018A (en) * 1997-02-24 1999-06-08 Winbond Electronics Corporation Trench edge rounding method and structure for trench isolation
US20010042890A1 (en) 1997-12-04 2001-11-22 Chulin Liang Isolated junction structure and method of manufacture
US6696348B1 (en) * 2002-12-09 2004-02-24 Advanced Micro Devices, Inc. Wide neck shallow trench isolation region to prevent strain relaxation at shallow trench isolation region edges
US20040110383A1 (en) 2002-12-05 2004-06-10 Hiroyuki Tanaka Method of forming device isolation trench
US20080150074A1 (en) 2006-12-21 2008-06-26 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system with isolation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100546852B1 (ko) * 2002-12-28 2006-01-25 동부아남반도체 주식회사 반도체 소자의 제조 방법
US8026571B2 (en) * 2008-05-29 2011-09-27 United Microelectronics Corp. Semiconductor-device isolation structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5910018A (en) * 1997-02-24 1999-06-08 Winbond Electronics Corporation Trench edge rounding method and structure for trench isolation
US20010042890A1 (en) 1997-12-04 2001-11-22 Chulin Liang Isolated junction structure and method of manufacture
US20040110383A1 (en) 2002-12-05 2004-06-10 Hiroyuki Tanaka Method of forming device isolation trench
US6696348B1 (en) * 2002-12-09 2004-02-24 Advanced Micro Devices, Inc. Wide neck shallow trench isolation region to prevent strain relaxation at shallow trench isolation region edges
US20080150074A1 (en) 2006-12-21 2008-06-26 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system with isolation

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US20150137242A1 (en) 2015-05-21
FR2979477A1 (fr) 2013-03-01
US20130049163A1 (en) 2013-02-28
US9269768B2 (en) 2016-02-23

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