UST892019I4 - Semiconductor integrated circuit with isolated elements and power transistor utilizing substrate "for low collector resistance - Google Patents

Semiconductor integrated circuit with isolated elements and power transistor utilizing substrate "for low collector resistance Download PDF

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Publication number
UST892019I4
UST892019I4 US892019DH UST892019I4 US T892019 I4 UST892019 I4 US T892019I4 US 892019D H US892019D H US 892019DH US T892019 I4 UST892019 I4 US T892019I4
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United States
Prior art keywords
power transistor
integrated circuit
substrate
collector resistance
semiconductor integrated
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Publication of UST892019I4 publication Critical patent/UST892019I4/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/641—Combinations of only vertical BJTs
    • H10D84/642—Combinations of non-inverted vertical BJTs of the same conductivity type having different characteristics, e.g. Darlington transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/019—Manufacture or treatment of isolation regions comprising dielectric materials using epitaxial passivated integrated circuit [EPIC] processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion

Definitions

  • a substrate preferably of low resistivity, can serve as a collector contact region of a power transistor as Well as a support for other functional elements of an integrated circuit.

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

A SUBSTRATE, PREFERABLY OF LOW RESISTIVITY, CAN SERVE AS A COLLECTOR CONTACT REGION OF A POWER TRANSISTOR AS WELL AS A SUPPORT FOR OTHER FUNCTIONAL ELEMENTS OF AN INTEGRATED CIRCUITS. AN EPITAXIAL LAYERS ON THE SURFACE OF THE SUBSTRATE, OF THE SAME CONDUCTIVITY TYPE BUT HIGHER RESISTIVITY, CONTAINS OTHER REGIONS OF FUNCTIONAL ELEMENTS. ISOLATION MEANS SUCH AS PN JUNCTION FORMING REGIONS OR DIELECTRIC MATERIAL, UNDERLIES AND ENCLOSES THOSE PORTIONS OF THE EPITAXIAL LAYER TO BE ISOLATED. MINIMAL COLLECTOR RESISTANCE AND INCREASED POWER HANDLING CAPABILITY CAN BE OBTAINED WITH THE POWER TRANSISTOR STRUCTURE WITHOUT SACRIFICING ISOLATION OR COMPLICATING FABRICATION.

Description

DEFENSIVE PUBLICATION UNITED STATES PATENT OFFICE Published at the request of the applicant or owner in accordance with the Notice of Dec. 16, 1969, 869 O.G. 687. The abstracts of Defensive Publication applications are identified by distinctly numbered series and are arranged chronologically. The heading of each abstract indicates the number of pages of specification, including claims and sheets of drawings contained in the application as originally filed. The files of these applications are available to the public for inspection and reproduction may be purchased for 30 cents asheet.
Defensive Publication applications have not been examined as to the merits of alleged invention. The Patent Oillcc makes no assertion as to the novelty of the disclosed subject matter.
PUBLISHED NOVEMBER 30, 1971 892 O.G. 160a T892,019 SEMICONDUCTOR INTEGRATED CIRCUIT WITH ISOLATED ELEMENTS AND POWER TRANSIS- TOR UTILIZING SUBSTRATE FOR LOW COLLEC- TOR RESISTANCE Edgar A. Sack, 48 St. Andrews St, Severna Park, Md. 21146 Filed Jan. 27, 1969, Ser. No. 794,046 Int. Cl. H011 19/00 US. Cl. 317-235 1 Sheet Drawing. 8 Pages Specification "allrnww zewnuwnanmywws via-u IIIIIIIII/III/I/I/IIIlI/III/III.
A substrate, preferably of low resistivity, can serve as a collector contact region of a power transistor as Well as a support for other functional elements of an integrated circuit. An epitaxial layer on the surface of the substrate, of the same conductivity type but higher resistivity, contains other regions of functional elements. Isolation means such as PN junction forming reg-ions or dielectric material, underlies and encloses those portions of the epitaxial layer to be isolated. Minimal collector resistance and increased power handling capability can be obtained with the power transistor structure without sacrificing isolation or complicating fabrication.
US892019D 1969-01-27 1969-01-27 Semiconductor integrated circuit with isolated elements and power transistor utilizing substrate "for low collector resistance Pending UST892019I4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US79404669A 1969-01-27 1969-01-27

Publications (1)

Publication Number Publication Date
UST892019I4 true UST892019I4 (en) 1971-11-30

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Family Applications (1)

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US892019D Pending UST892019I4 (en) 1969-01-27 1969-01-27 Semiconductor integrated circuit with isolated elements and power transistor utilizing substrate "for low collector resistance

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4046605A (en) 1974-01-14 1977-09-06 National Semiconductor Corporation Method of electrically isolating individual semiconductor circuits in a wafer
US4926231A (en) 1988-08-05 1990-05-15 Motorola Inc. Integrated pin photo-detector
US5461253A (en) * 1988-09-30 1995-10-24 Nippon Steel Inc. Semiconductor substrate structure for producing two isolated circuits on a same substrate
USRE35642E (en) * 1987-12-22 1997-10-28 Sgs-Thomson Microelectronics, S.R.L. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
US5688702A (en) * 1988-02-08 1997-11-18 Kabushiki Kaisha Toshiba Process of making a semiconductor device using a silicon-on-insulator substrate
USRE36311E (en) * 1987-12-22 1999-09-21 Sgs-Thomson Microelectronics, S.R.L. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4046605A (en) 1974-01-14 1977-09-06 National Semiconductor Corporation Method of electrically isolating individual semiconductor circuits in a wafer
USRE35642E (en) * 1987-12-22 1997-10-28 Sgs-Thomson Microelectronics, S.R.L. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
USRE36311E (en) * 1987-12-22 1999-09-21 Sgs-Thomson Microelectronics, S.R.L. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
US5688702A (en) * 1988-02-08 1997-11-18 Kabushiki Kaisha Toshiba Process of making a semiconductor device using a silicon-on-insulator substrate
US4926231A (en) 1988-08-05 1990-05-15 Motorola Inc. Integrated pin photo-detector
US5461253A (en) * 1988-09-30 1995-10-24 Nippon Steel Inc. Semiconductor substrate structure for producing two isolated circuits on a same substrate

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