WO1987002814A1 - Affichage de caracteres avec des attributs selectionnables - Google Patents

Affichage de caracteres avec des attributs selectionnables Download PDF

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Publication number
WO1987002814A1
WO1987002814A1 PCT/US1986/002274 US8602274W WO8702814A1 WO 1987002814 A1 WO1987002814 A1 WO 1987002814A1 US 8602274 W US8602274 W US 8602274W WO 8702814 A1 WO8702814 A1 WO 8702814A1
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WO
WIPO (PCT)
Prior art keywords
character
attribute
slice
accordance
dot signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1986/002274
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English (en)
Inventor
Martin Clive Reynolds
Daniel Glen Bezzant
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Memorex Corp
Original Assignee
Memorex Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memorex Corp filed Critical Memorex Corp
Publication of WO1987002814A1 publication Critical patent/WO1987002814A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/30—Control of display attribute

Definitions

  • the present invention generally relates to video display circuitry, and more particularly to improved means and methods for displaying characters with
  • CTR cathode ray tube
  • a more specific object of the invention is to provide improved means and methods for minimizing the added delay incurred when a selected attribute is incor ⁇ porated into a video dot stream.
  • An additional object of the invention in accordance with the foregoing objects is to provide im ⁇ proved means and methods for displaying characters with selectable attributes at high speed even where a rela ⁇ tively large plurality of selectable attributes are pro ⁇ vided.
  • a further object of the invention is to provide for the implementation of the foregoing objects in a relatively simple and economical manner.
  • a specially chosen encoding is employed for the attribute * data, which encoding is performed concurrently with con-
  • _c ventional character slice generation and serialization 5 operations.
  • the resulting encoded attribute signals are applied to specially chosen attribute combinational logic for logical combination with corresponding serialized character slice signals.
  • the attribute encoding and combinational logic are chosen so as to produce, with 10 relatively little added delay, a composite video dot signal containing both character and attribute data, thereby making it possible to display characters with selectable attributes on a CRT at high speed.
  • FIG. 1 is an electrical block diagram illustrating a typical prior art embodiment for display ⁇ ing characters on a CRT with selectable attributes.
  • FIG. 2 illustrates an example of a row of displayed characters which may typically be provided by 25 the prior art embodiment of FIG. 1 along with the associ ⁇ ated video dot signals corresponding thereto.
  • FIG. 3 is an electrical block diagram illustrating a particular preferred embodiment of the invention for displaying characters with selectable at- * 30 tributes on a CRT at high speed.
  • FIG. 1 generally illustrates how the prior art 5 typically provides for generating a video dot signal for displaying characters on a CRT with selectable at ⁇ tributes.
  • a character is formed by se ⁇ lectively turning on (lighting) particular dots in the matrix at appropriate times during a plurality of scan lines L0-L9 so as to produce a visual display of the
  • FIG. 2 il ⁇ lustrates, for example, a display of the characters A, P and T on a CRT by lighting particular dots of the charac ⁇ ter' s dot matrix.
  • FIG. 2 also illustrates (below the display) the associated video dot signals S0-S9 respec-
  • FIG. 2 further illustrates examples of typical attributes which may be provided for particular charac ⁇ ters.
  • the letter A is displayed without any 0 attributes, while the letter P is provided with an underline attribute, and the letter ' is displayed in inverse video (another type of common attribute).
  • each charac ⁇ 0 ter in a row is formed by the video dot signal on a slice-by-slice basis. More specifically, each row of characters is formed by first forming the top horizontal slice of each character in the row, then forming the next lower slice of character, and so on.
  • character generator 12 receives character data signals 10a identifying the characters to be displayed, the characters being provided in a sequence corresponding to the positioning of the characters on the CRT.
  • the character generator 12 also receives scanning signals 10b indicative of CRT scanning, which is used by the charac- ter generator 12 for producing character slice signals 12a representing a corresponding character slice.
  • the character data signals 10a and the scanning data signals 10b may be provided in various well known ways which need not be further described for the purposes of the present invention.
  • the character generator 12 may typically include a read-only memory (ROM) for se ⁇ quentially producing groups of parallel character slice signals 12a (one group for each character) in response to the character data signals 10a and scanning signals 10b.
  • ROM read-only memory
  • These character slice signals 12a produced by the charac ⁇ ter generator 12 in FIG. 1 are applied to a video serial- izer 16 which, in response to a dot clock CD, serializes each group of parallel character slice signals 12a so as to form a character slice video dot signal 16a having a dot pattern corresponding to the character slices to be displayed for the line being scanned (for example, see character slice video dot signal SI in FIG. 2 provided for the character slice corresponding to line Ll of each of the characters A, P and T) .
  • the dot clock CD is synchronized with CRT scanning and occurs at a rate corresponding to the spacing between columns of the character matrix.
  • Such a dot clock CD is typically included as part of the scanning data 10b.
  • the character slice video dot sig ⁇ nal 16a produced by the video serializer 16 in FIG. 2 would be applied directly to the CRT drive circuitry 22 in FIG. 1.
  • attribute data must be logi ⁇ cally combined with the character slice video dot signals 16a. In the prior art embodiment shown in FIG.
  • FIG. 3 illustrates a preferred embodiment of the invention for displaying characters with selected attributes in a manner such that the time required for logically combining a selected attribute with a corre- sponding character video dot signal is significantly reduced, even where a relatively large number of selecta ⁇ ble attributes are provided.
  • character data signals 10a identifying characters to be displayed a CRT are applied to character generator 12 along with scanning signals 10b for producing groups of parallel character slice signals 12a which are in turn applied to a video serializer 16 for producing character slice video dot signals 16a.
  • the character data signals 10a iden- tifying each character are accompanied by attribute data signals 10c identifying the attribute, if any, to be provided for each character.
  • the attribute data signals 10c are applied to an attribute encoder 24 along with scanning signals 10b.
  • the attribute encoder 24 operates in response to these inputs to produce a spe ⁇ cially chosen pair of attribute slice logic signals 24a and 24b having values determined by the attribute identi- fied by the input attribute data signals 10c and the CRT scanning line indicated by the input scanning signals IOC.
  • the attribute encoder 24 will provide a pair of attribute slice logic signals 24a and 24b having predetermined values indicative of the attribute to be provided for each corresponding character slice.
  • the encoder 24 may include a ROM for generating these attribute logic signals 24a and 24b in response to the attribute and scanning signals 10c and 10b.
  • the characteristics of the pair of attribute logic slice signals 24a and 24b are chosen so that one functions as an inhibit signal 24a, and the other functions as an invert signal 24b.
  • These inhibit and invert signals 24a and 24b, along with the character slice video dot signals 16a, are applied via a synchro ⁇ nizing latch 26 to combination logic which in the partic ⁇ ular preferred embodiment of FIG. 3 comprises just an AND gate 30 and an EXCLUSIVE OR Gate 40.
  • the synchronizing latch 26 operates in a conventional manner to appropri ⁇ ately synchronize the signals 16a, 24a and 24b prior to their logical combination by AND gate 30 and EXCLUSIVE OR gate 40. More specifically, it will be seen in FIG. 3 that the synchronized character slice video dot signal 16a" is applied to one input of AND gate 30, while the synchronized inhibit signal 24a' is applied to an inverse input (indicated by the solid circle) of AND gate 30. Accordingly, the output 30a of gate 30 will be TRUE or
  • the AND gate output 30a will have the same logical level as the synchronized character slice video dot signal 16a' , except when the synchronized inhibit signal 24a' is TRUE or HIGH, in which case AND gate output 30a will be FALSE or LOW.
  • AND gate output 30a is applied to EXCLUSIVE OR gate 40 along with the synchro ⁇ nized invert signal 24b' . Accordingly, the output 40a of EXCLUSIVE OR gate 40, which is the resulting video dot signal applied to the CRT drive circuitry 22, will be TRUE or HIGH only when AND gate output 30a and the syn ⁇ chronized invert signal 24b' are different. It should be evident from the foregoing that the particular attribute encoding and two-level attribute combinational logic employed in the preferred embodiment of FIG.
  • this control can be achieved with a high character display rate because: (1) the encoding time required by the attribute encoder 24 does not add any delay to the character display time since it is per ⁇ formed concurrently with the generation of the character slice video signal 16a which normally requires as much time as attribute encoding even where a large number of selectable attributes are provided and (2) the combina ⁇ tional logic required for incorporating a selectable attribute into the resultant video dot signal adds only a relatively small delay to the overall character display time since only a small number of logical gating levels are required, as exemplified by AND gate 30 and EXCLUSIVE OR gate 40 in FIG. 3.
  • a selectable attribute (or no selected attribute) can be incorporated into the result- ing video dot signal by encoding each selected attribute into just the inhibit and invert signals 24a and 24b and then logically combining these inhibit and invert signals with the character slice dot signal using just the AND gate 30 and EXCLUSIVE OR gate 40 as illustrated in FIG. 3 will now be demonstrated for a number of common types of attributes.
  • Example 1 No Selected Attribute
  • the encoding provided by the encoder 24 in FIG. 3 is such that the inhibit and invert signals 24a and 24b are both maintained LOW or F7ALSE for all charac ⁇ ter slices which causes the resulting video dot signal 40a to correspond to the character slice dot video signal " 16a.
  • the encoding provided by the encoder 24 in FIG. 3 is such that the inhibit and 0 invert signals 24a and 24b are both maintained LOW or
  • Example 3 Inverse Video Attribute O
  • the encoding provided by the encoder 24 in FIG. 3 is such that for character slices corresponding to scan lines L0-L9 in FIG. 2, the inhibit signal 24a is maintained FALSE or LOW for all character 5 slices, while the invert signal 24b is maintained TRUE or HIGH, whereby a resulting video dot signal 40a will be produced for each of these character slices which will be the inverse of the character slice video dot signal 16a, as illustrated by the portions of signals L0-L8 corre- 0 sponding to the character T in FIG. 2.
  • both the inhibit and invert signals are caused to be FALSE or LOW so that the normal unlighted slice of line L9 is produced.
  • Example 4 Blank Attribute For this attribute, a blank is provided regardless of the character. Accordingly, for all char ⁇ acter slices, the encoder 24 causes the inhibit signal 5 24a to be TRUE or HIGH and the invert signal 24b to be FALSE or LOW, which thereby results in no lighted dots being produced.
  • the encoder 24 in the embodiment of FIG. 3 can pro- 1.0 vide for encoding many types of attributes into appropri ⁇ ate logical combinations of the inhibit and invert sig ⁇ nals 24a and 24b.
  • the embodiment illustrated in FIG. 3 is considered to be of particular advantage, it is to be understood that the invention is not limited to use 15 of the particular combinational gates 30 and 40 shown in 'the FIG. 3 embodiment, since other advantageous embodi ⁇ ments can be provided using the teachings provided here ⁇ in.
  • the present invention is to be 20 considered as including all apparatus and methods coming within the scope of the invention as defined by the ap ⁇ pended claims.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

Des caractères avec des attributs sélectionnables sont affichés à haute vitesse à l'écran d'un tube cathodique (22) en codant (24) les donnés d'attributs (10c) simultanément avec la production (12) de signaux (12a) de découpage de caratères, et en combinant ensuite logiquement les signaux d'attributs (24a et 24b) avec les signaux (12a) de découpage de caractères produits en utilisant uniquement deux niveaux d'éléments logiques de déclenchement (30 et 40).
PCT/US1986/002274 1985-11-01 1986-10-22 Affichage de caracteres avec des attributs selectionnables Ceased WO1987002814A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US79394685A 1985-11-01 1985-11-01
US793,946 1985-11-01

Publications (1)

Publication Number Publication Date
WO1987002814A1 true WO1987002814A1 (fr) 1987-05-07

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1986/002274 Ceased WO1987002814A1 (fr) 1985-11-01 1986-10-22 Affichage de caracteres avec des attributs selectionnables

Country Status (3)

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EP (1) EP0247092A1 (fr)
JP (1) JPS63501247A (fr)
WO (1) WO1987002814A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989001679A1 (fr) * 1987-08-11 1989-02-23 Nicholas John Murrell Marqueur de ligne pour terminal a ecran de visualisation
US5339094A (en) * 1987-08-11 1994-08-16 Murrell Nicholas J VDU line marker

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4455554A (en) * 1980-12-30 1984-06-19 International Business Machines Corporation Proportionality in minature displays

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4455554A (en) * 1980-12-30 1984-06-19 International Business Machines Corporation Proportionality in minature displays

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Electronique Applications, No. 37, August-September 1984 (Evry, FR) MARCHAL: "Attributs Video pour Micro-Ordinateurs", pages 57-61, see figures 1,3 *
IBM Technical Disclosure Bulletin, Vol. 27, No. 4A, September 1984 (New York, US) LANDERS: "Attribute Memory for Display Adapter", pages 2175 and 2176, see the whole document *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989001679A1 (fr) * 1987-08-11 1989-02-23 Nicholas John Murrell Marqueur de ligne pour terminal a ecran de visualisation
US5339094A (en) * 1987-08-11 1994-08-16 Murrell Nicholas J VDU line marker

Also Published As

Publication number Publication date
JPS63501247A (ja) 1988-05-12
EP0247092A1 (fr) 1987-12-02

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