WO1987007796A1 - Dispositif de chiffrage et de dechiffrage - Google Patents

Dispositif de chiffrage et de dechiffrage Download PDF

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Publication number
WO1987007796A1
WO1987007796A1 PCT/SE1986/000275 SE8600275W WO8707796A1 WO 1987007796 A1 WO1987007796 A1 WO 1987007796A1 SE 8600275 W SE8600275 W SE 8600275W WO 8707796 A1 WO8707796 A1 WO 8707796A1
Authority
WO
WIPO (PCT)
Prior art keywords
code
bits
shift register
unit
ciphering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/SE1986/000275
Other languages
English (en)
Inventor
Stefan Santesson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Datakonsult I Malmo AB
Original Assignee
Datakonsult I Malmo AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR1019880700146A priority Critical patent/KR920001575B1/ko
Priority to DE8686903695T priority patent/DE3687235T2/de
Priority to US07/285,970 priority patent/US4972481A/en
Priority to AT86903695T priority patent/ATE83106T1/de
Priority to JP61503445A priority patent/JPH01503028A/ja
Priority to EP86903695A priority patent/EP0309447B1/fr
Application filed by Datakonsult I Malmo AB filed Critical Datakonsult I Malmo AB
Publication of WO1987007796A1 publication Critical patent/WO1987007796A1/fr
Priority to DK060488A priority patent/DK60488D0/da
Priority to NO1988880545A priority patent/NO880545D0/no
Priority to FI885698A priority patent/FI885698A7/fi
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04K—SECRET COMMUNICATION; JAMMING OF COMMUNICATION
    • H04K1/00—Secret communication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/12—Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Definitions

  • the invention also relates to a deciphering de ⁇ vice which is associated with the ciphering device and designed for serially transmitted information, and which comprises an input for a sequence of bits to be deciphered, an output for the deciphered bit sequence, and a mixing unit connected between the input and the output, said mixing unit being adapted to receive both the bit sequence to be deciphered and a sequence of code bits for deciphering said bit sequence, and, by a mixing operation, to generate the deciphered bit sequence, and a code unit adapted to generate code bits and comprising a shift register into which bits from the ciphered bit sequence are shifted, and a memory containing code bits and ad ⁇ dressed with bits from the shift register.
  • this object is achiev ⁇ ed by means of a ciphering device of the type stated in the introduction to this specification, which is characterized by first means for selecting whether a bit in the bit sequence to be ciphered should be mixed with a code bit or not, and by means of a de ⁇ ciphering device of the type stated in the introduc ⁇ tion to this specification, which is characterized by first means for selecting whether a bit in the bit sequence to be deciphered should be mixed with a code bit or not.
  • the devices comprise means for selecting which bits in the ciphered bit. sequence should be used as address to the memory.
  • the present invention therefore comprises a shift register which is disposed between the two code units and the input of which is connected to the first code unit, and an EXOR gate which on its inputs receives bits from the shift register and the output of which is connected to the shift register of the second code unit. In this manner, it is possible to increase the number of addresses to the replacement memory which thus becomes so large that it is impossible to map it in a reasonable time.
  • the algorithm is of the type which generates a code that cannot be traced mathematically backwards in time, it becomes impossible to decipher previously tapped infor- mation by means of the deciphering device. The security requirement for information to be kept secret after the transmission is thus satisfied.
  • Fig- .l is a block diagram of a ciphering device according to the present invention.
  • Fig. 2 is block diagram of a deciphering device correspond ⁇ ing to the ciphering device of Fig. 1.
  • Fig. 3 is a block diagram showing one embodiment of the ciphering device having double code units.
  • the device comprises a second code .unit 4' the input of which is connected to the output of the first code unit 4 and which is designed in the same way as this, namely with a 16-bit shift register 9', a memory 5 ' , which may be a byte-organized ROM or EPROM, and a multiplexer 10'.
  • the code bits generated by the code unit 4 are supplied to the shift register S ' , the first thirteen bits of which are used for addressing the memory 5 ' and the last three bits of which serve as input signal to the multiplexer 10' for selecting which bit in the word addressed in the memory 5 ' should constitute a code bit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Storage Device Security (AREA)

Abstract

Un système de chiffrage comprend un dispositif de chiffrage ayant une entrée (1) pour une séquence de bits devant être chiffrés, une sortie (2) pour la séquence des bits chiffrés et une unité de mélange (3) connectée entre l'entrée (1) et la sortie (2). L'unité de mélange reçoit à la fois la séquence de bits devant être chiffrés et une séquence de bits de codes pour le chiffrage de la séquence de bits et produit, par une opération de mélange, la séquence de bits chiffrés. La sortie de l'unité de mélange (3) est connectée à une unité de codage (4) servant à produire des bits de codes. L'unité de codage (4) comprend une mémoire (5) contenant des bits de codes et adressée avec des bits provenant de la séquence de bits chiffrés pour la production de bits de codes. Le dispositif de chiffrage comprend en outre un organe (7) qui permet de décider si un bit de la séquence de bits devant être chiffrés doit ou ne doit pas être mélangé à un bit de codes et un organe (6) permettant de choisir quels bits de la séquence de bits chiffrés doivent être utilisés pour l'adressage de la mémoire. Ces organes sont commandés par une unité de commande programmable (8). Le dispositif de déchiffrage du système de chiffrage est conçu de la même manière que le dispositif de chiffrage, excepté que l'entrée de l'unité de codage reçoit des signaux d'entrée provenant de l'entrée du dispositif de déchiffrage. Etant donné que le dispositif de chiffrage et le dispositif de déchiffrage sont conçus de la même manière et que leurs unités différentes reçoivent les mêmes informations, ces dispositifs sont automatiquement synchronisés après une interruption. Le dispositif de chiffrage est en outre très rapide et le délai de transmission des informations est négligeable.
PCT/SE1986/000275 1984-12-10 1986-06-09 Dispositif de chiffrage et de dechiffrage Ceased WO1987007796A1 (fr)

Priority Applications (9)

Application Number Priority Date Filing Date Title
DE8686903695T DE3687235T2 (de) 1986-06-09 1986-06-09 Einrichtung zur verschluesselung und zur entschluesselung.
US07/285,970 US4972481A (en) 1986-06-09 1986-06-09 Ciphering and deciphering device
AT86903695T ATE83106T1 (de) 1986-06-09 1986-06-09 Einrichtung zur verschluesselung und zur entschluesselung.
JP61503445A JPH01503028A (ja) 1986-06-09 1986-06-09 暗号化及び解読装置
EP86903695A EP0309447B1 (fr) 1986-06-09 1986-06-09 Dispositif de chiffrage et de dechiffrage
KR1019880700146A KR920001575B1 (ko) 1984-12-10 1986-06-09 암호화 및 해독장치
DK060488A DK60488D0 (da) 1986-06-09 1988-02-05 Chifrerings- og dechifreringsandordning
NO1988880545A NO880545D0 (no) 1986-06-09 1988-02-08 Krypterings- og dekrypteringsinnretning.
FI885698A FI885698A7 (fi) 1986-06-09 1988-12-08 Krypterings- och dekrypteringsanordning.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE8406242A SE447859B (sv) 1984-12-10 1984-12-10 Krypteringsanordning samt dekrypteringsanordning

Publications (1)

Publication Number Publication Date
WO1987007796A1 true WO1987007796A1 (fr) 1987-12-17

Family

ID=20358096

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1986/000275 Ceased WO1987007796A1 (fr) 1984-12-10 1986-06-09 Dispositif de chiffrage et de dechiffrage

Country Status (3)

Country Link
KR (1) KR920001575B1 (fr)
SE (1) SE447859B (fr)
WO (1) WO1987007796A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0457709A1 (fr) * 1990-05-10 1991-11-21 Amper Datos S.A. Machine de chiffrage
EP0673133A1 (fr) * 1994-03-18 1995-09-20 Koninklijke KPN N.V. Traitement de données cryptographique utilisant une cascade des éléments cryptographiques dans une structure à contre-réaction
WO1998017028A1 (fr) * 1996-10-15 1998-04-23 Ericsson Inc. Utilisation d'algorithmes de chiffrement duplex pour voies de satellites presentant un retard

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1388035A (en) * 1971-04-19 1975-03-19 Gretag Ag Method of and apparatus for encoded communications transmission
US3984668A (en) * 1974-03-20 1976-10-05 U.S. Philips Corporation Method for generating pseudo-random bit sequence words and a device for carrying out the method
US4133974A (en) * 1976-11-05 1979-01-09 Datotek, Inc. System for locally enciphering prime data
US4176247A (en) * 1973-10-10 1979-11-27 Sperry Rand Corporation Signal scrambler-unscrambler for binary coded transmission system
US4431865A (en) * 1979-10-10 1984-02-14 Telediffusion De France Digital signal enciphering and deciphering apparatus and system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1388035A (en) * 1971-04-19 1975-03-19 Gretag Ag Method of and apparatus for encoded communications transmission
US4176247A (en) * 1973-10-10 1979-11-27 Sperry Rand Corporation Signal scrambler-unscrambler for binary coded transmission system
US3984668A (en) * 1974-03-20 1976-10-05 U.S. Philips Corporation Method for generating pseudo-random bit sequence words and a device for carrying out the method
US4133974A (en) * 1976-11-05 1979-01-09 Datotek, Inc. System for locally enciphering prime data
US4431865A (en) * 1979-10-10 1984-02-14 Telediffusion De France Digital signal enciphering and deciphering apparatus and system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0457709A1 (fr) * 1990-05-10 1991-11-21 Amper Datos S.A. Machine de chiffrage
EP0673133A1 (fr) * 1994-03-18 1995-09-20 Koninklijke KPN N.V. Traitement de données cryptographique utilisant une cascade des éléments cryptographiques dans une structure à contre-réaction
NL9400428A (nl) * 1994-03-18 1995-11-01 Nederland Ptt Inrichting voor het cryptografisch bewerken van datapakketten, alsmede werkwijze voor het genereren van cryptografische bewerkingsdata.
US5809147A (en) * 1994-03-18 1998-09-15 Koninklijke Ptt Nederland Device for cryptographically processing data packets and method of generating cryptographic processing data
WO1998017028A1 (fr) * 1996-10-15 1998-04-23 Ericsson Inc. Utilisation d'algorithmes de chiffrement duplex pour voies de satellites presentant un retard
US5825889A (en) * 1996-10-15 1998-10-20 Ericsson Inc. Use of duplex cipher algorithms for satellite channels with delay

Also Published As

Publication number Publication date
KR880701502A (ko) 1988-07-27
SE447859B (sv) 1986-12-15
KR920001575B1 (ko) 1992-02-18
SE8406242D0 (sv) 1984-12-10
SE8406242L (sv) 1986-06-11

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