WO1988008577A3 - Node for servicing interrupt request messages on a pended bus - Google Patents

Node for servicing interrupt request messages on a pended bus Download PDF

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Publication number
WO1988008577A3
WO1988008577A3 PCT/US1988/001261 US8801261W WO8808577A3 WO 1988008577 A3 WO1988008577 A3 WO 1988008577A3 US 8801261 W US8801261 W US 8801261W WO 8808577 A3 WO8808577 A3 WO 8808577A3
Authority
WO
WIPO (PCT)
Prior art keywords
node
interrupt
interrupt request
servicing
request messages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1988/001261
Other languages
French (fr)
Other versions
WO1988008577A2 (en
Inventor
Douglas D Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Priority to KR1019880701767A priority Critical patent/KR920006745B1/en
Priority to DE88905055T priority patent/DE3883532T2/en
Publication of WO1988008577A2 publication Critical patent/WO1988008577A2/en
Publication of WO1988008577A3 publication Critical patent/WO1988008577A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
  • Computer And Data Communications (AREA)

Abstract

Interrupt servicing node for servicing interrupt request on a pended bus (25). The interrupt servicing node provides interrupt acknowledge messages including destination data specifying a particular interrupting node at times when the interrupt servicing node is ready to service the interrupt request message. The interrupt servicing node includes storage means (164) for indicating whether an interrupt request is pending from a particular interrupting node. An interrupt request message on the bus includes ID data for identifying a particular interrupting node as the source of an interrupt request.
PCT/US1988/001261 1987-05-01 1988-04-20 Node for servicing interrupt request messages on a pended bus Ceased WO1988008577A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019880701767A KR920006745B1 (en) 1987-05-01 1988-04-20 Interrupt service node on the pending bus
DE88905055T DE3883532T2 (en) 1987-05-01 1988-04-20 NODE FOR OPERATING INTERRUPT REQUEST MESSAGES ON A PENDING BUS.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US044,755 1987-05-01
US07/044,755 US4953072A (en) 1987-05-01 1987-05-01 Node for servicing interrupt request messages on a pended bus

Publications (2)

Publication Number Publication Date
WO1988008577A2 WO1988008577A2 (en) 1988-11-03
WO1988008577A3 true WO1988008577A3 (en) 1988-11-17

Family

ID=21934160

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/001261 Ceased WO1988008577A2 (en) 1987-05-01 1988-04-20 Node for servicing interrupt request messages on a pended bus

Country Status (8)

Country Link
US (1) US4953072A (en)
EP (1) EP0358716B1 (en)
JP (1) JPH02500784A (en)
KR (1) KR920006745B1 (en)
AU (1) AU604330B2 (en)
CA (1) CA1303226C (en)
DE (1) DE3883532T2 (en)
WO (1) WO1988008577A2 (en)

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US5613128A (en) * 1990-12-21 1997-03-18 Intel Corporation Programmable multi-processor interrupt controller system with a processor integrated local interrupt controller
JP2855298B2 (en) * 1990-12-21 1999-02-10 インテル・コーポレーション Arbitration method of interrupt request and multiprocessor system
US5179704A (en) * 1991-03-13 1993-01-12 Ncr Corporation Method and apparatus for generating disk array interrupt signals
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US5542076A (en) * 1991-06-14 1996-07-30 Digital Equipment Corporation Method and apparatus for adaptive interrupt servicing in data processing system
US5369748A (en) * 1991-08-23 1994-11-29 Nexgen Microsystems Bus arbitration in a dual-bus architecture where one bus has relatively high latency
US5371897A (en) * 1991-08-27 1994-12-06 International Business Machines Corporation Method for requesting identification of a neighbor node in a data processing I/O system
US5269005A (en) * 1991-09-17 1993-12-07 Ncr Corporation Method and apparatus for transferring data within a computer system
US5404535A (en) * 1991-10-22 1995-04-04 Bull Hn Information Systems Inc. Apparatus and method for providing more effective reiterations of processing task requests in a multiprocessor system
JP3411300B2 (en) * 1992-02-18 2003-05-26 株式会社日立製作所 Information processing device
US5581770A (en) * 1992-06-04 1996-12-03 Mitsubishi Denki Kabushiki Kaisha Floating interruption handling system and method
US5473763A (en) * 1993-08-02 1995-12-05 Advanced Micro Devices, Inc. Interrupt vector method and apparatus
US5588125A (en) * 1993-10-20 1996-12-24 Ast Research, Inc. Method and apparatus for increasing bus bandwidth on a system bus by inhibiting interrupts while posted I/O write operations are pending
WO1995016965A1 (en) * 1993-12-16 1995-06-22 Intel Corporation Multiple programmable interrupt controllers in a multi-processor system
US6026455A (en) * 1994-02-24 2000-02-15 Intel Corporation Architecture and method for providing guaranteed access for a retrying bus master to a data transfer bridge connecting two buses in a computer system
US5781187A (en) * 1994-05-31 1998-07-14 Advanced Micro Devices, Inc. Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system
US5689713A (en) * 1995-03-31 1997-11-18 Sun Microsystems, Inc. Method and apparatus for interrupt communication in a packet-switched computer system
FR2737590B1 (en) * 1995-08-03 1997-10-17 Sgs Thomson Microelectronics INTERRUPTION MANAGEMENT DEVICE
US5701422A (en) * 1995-12-13 1997-12-23 Ncr Corporation Method for ensuring cycle ordering requirements within a hierarchical bus system including split-transaction buses
JP3731263B2 (en) * 1996-09-11 2006-01-05 ソニー株式会社 Communication method and electronic device
US5848279A (en) * 1996-12-27 1998-12-08 Intel Corporation Mechanism for delivering interrupt messages
US20050228917A1 (en) * 2004-03-30 2005-10-13 Brink Peter C Novel structure and method for interrupt detection and processing
CN101355365A (en) 2007-07-27 2009-01-28 佛山市顺德区顺达电脑厂有限公司 Method for detecting and processing scanning code of designable computer keyboard key

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US4296466A (en) * 1978-01-23 1981-10-20 Data General Corporation Data processing system including a separate input/output processor with micro-interrupt request apparatus
EP0138676A2 (en) * 1983-09-22 1985-04-24 Digital Equipment Corporation Retry mechanism for releasing control of a communications path in a digital computer system

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JPS5259534A (en) * 1975-11-11 1977-05-17 Panafacom Ltd Data transfer system
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US4240140A (en) * 1978-12-26 1980-12-16 Honeywell Information Systems Inc. CRT display terminal priority interrupt apparatus for generating vectored addresses
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AU562975B2 (en) * 1983-09-22 1987-06-25 Digital Equipment Corporation Message oriented interrupt mechanism for multiprocessor systems
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4020471A (en) * 1975-06-30 1977-04-26 Honeywell Information Systems, Inc. Interrupt scan and processing system for a data processing system
US4296466A (en) * 1978-01-23 1981-10-20 Data General Corporation Data processing system including a separate input/output processor with micro-interrupt request apparatus
EP0138676A2 (en) * 1983-09-22 1985-04-24 Digital Equipment Corporation Retry mechanism for releasing control of a communications path in a digital computer system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, vol. 27, no. 1B, June 1984, IBM Corp. (New York, US), R.E. Russell et al.: "Interrupt request circuit", pages 554-556 *

Also Published As

Publication number Publication date
JPH02500784A (en) 1990-03-15
DE3883532T2 (en) 1994-04-14
US4953072A (en) 1990-08-28
CA1303226C (en) 1992-06-09
AU604330B2 (en) 1990-12-13
DE3883532D1 (en) 1993-09-30
KR920006745B1 (en) 1992-08-17
KR890702137A (en) 1989-12-22
EP0358716A1 (en) 1990-03-21
WO1988008577A2 (en) 1988-11-03
AU1807988A (en) 1988-12-02
EP0358716B1 (en) 1993-08-25

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