WO1991013392A3 - Circuit logique rapide entierement differentiel facilement configurable - Google Patents

Circuit logique rapide entierement differentiel facilement configurable Download PDF

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Publication number
WO1991013392A3
WO1991013392A3 PCT/US1991/000987 US9100987W WO9113392A3 WO 1991013392 A3 WO1991013392 A3 WO 1991013392A3 US 9100987 W US9100987 W US 9100987W WO 9113392 A3 WO9113392 A3 WO 9113392A3
Authority
WO
WIPO (PCT)
Prior art keywords
fully differential
sum
logic circuit
differential
cout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1991/000987
Other languages
English (en)
Other versions
WO1991013392A2 (fr
Inventor
James Hesson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of WO1991013392A2 publication Critical patent/WO1991013392A2/fr
Publication of WO1991013392A3 publication Critical patent/WO1991013392A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3876—Alternation of true and inverted stages

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Mathematical Optimization (AREA)
  • Logic Circuits (AREA)

Abstract

Circuit logique CMOS rapide entièrement différentiel utilisant uniquement des tampons trois états et capable d'un retard de propagation aussi faible que celui d'un seul transistor. Le mode de réalisation préféré de l'invention comprend quatre tampons trois états (A1, A2, A3, et A4) connectés ensemble de manière à avoir des entrées différentielles mutiples et une sortie différentielle. Différentes configurations de la sortie et des entrées permettent d'obtenir différentes fonctions logiques. Un autre mode de réalisation combine trois de ces circuits logiques afin d'obtenir un additionneur complet de trois entrées entièrement différentielles, produisant des sorties de somme (SOMME/SOMME*) et de report (COUT/COUT*) dans des retards de deux transistors.
PCT/US1991/000987 1990-02-12 1991-02-12 Circuit logique rapide entierement differentiel facilement configurable Ceased WO1991013392A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US478,906 1983-03-25
US47890690A 1990-02-12 1990-02-12

Publications (2)

Publication Number Publication Date
WO1991013392A2 WO1991013392A2 (fr) 1991-09-05
WO1991013392A3 true WO1991013392A3 (fr) 1991-10-31

Family

ID=23901864

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1991/000987 Ceased WO1991013392A2 (fr) 1990-02-12 1991-02-12 Circuit logique rapide entierement differentiel facilement configurable

Country Status (1)

Country Link
WO (1) WO1991013392A2 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4718035A (en) * 1984-05-24 1988-01-05 Kabushiki Kaisha Toshiba Logic operation circuit having an exclusive-OR circuit
US4718579A (en) * 1986-05-27 1988-01-12 General Foods Corporation Beverage dispensing machine
US4740907A (en) * 1984-03-29 1988-04-26 Kabushiki Kaisha Toshiba Full adder circuit using differential transistor pairs
US4749886A (en) * 1986-10-09 1988-06-07 Intersil, Inc. Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate
US4870609A (en) * 1986-11-13 1989-09-26 Mitsubishi Denki Kabushiki Kaisha High speed full adder using complementary input-output signals

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4740907A (en) * 1984-03-29 1988-04-26 Kabushiki Kaisha Toshiba Full adder circuit using differential transistor pairs
US4718035A (en) * 1984-05-24 1988-01-05 Kabushiki Kaisha Toshiba Logic operation circuit having an exclusive-OR circuit
US4718579A (en) * 1986-05-27 1988-01-12 General Foods Corporation Beverage dispensing machine
US4749886A (en) * 1986-10-09 1988-06-07 Intersil, Inc. Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate
US4870609A (en) * 1986-11-13 1989-09-26 Mitsubishi Denki Kabushiki Kaisha High speed full adder using complementary input-output signals

Also Published As

Publication number Publication date
WO1991013392A2 (fr) 1991-09-05

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