WO1992005496A1 - Systeme de signalement d'evenement et procede pour un systeme de processeur comprenant une unite de memoire centrale - Google Patents

Systeme de signalement d'evenement et procede pour un systeme de processeur comprenant une unite de memoire centrale Download PDF

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Publication number
WO1992005496A1
WO1992005496A1 PCT/US1991/006713 US9106713W WO9205496A1 WO 1992005496 A1 WO1992005496 A1 WO 1992005496A1 US 9106713 W US9106713 W US 9106713W WO 9205496 A1 WO9205496 A1 WO 9205496A1
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WIPO (PCT)
Prior art keywords
data ram
address
bus
event
processor
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PCT/US1991/006713
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English (en)
Inventor
Keith Rouse
Terry F. Montlick
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Star Semiconductor Corp
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Star Semiconductor Corp
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Priority claimed from PCT/US1991/003386 external-priority patent/WO1991018342A1/fr
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/786—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers) using a single memory module

Definitions

  • the present invention relates to event signalling systems and methods for digital signal processor systems. More particularly, the present invention relates to systems and methods for signalling the occurrence of events to one or more computing processors, where data flow into and out of a digital signal processor system is substantially through a data RAM and is independent of the one or more computing processors.
  • SCDSPs Single chip digital signal processors
  • the signal processors of the art are burdened with the interrupt structures and the memory intensiveness of their microprocessor ancestors.
  • the interrupt structures found in the SCDSPs of the art typically result in the SCDSPs being limited to a frequency spectrum from DC to the low tens of KHz.
  • a digital signal processor also referred to as a "SPROC" architecture was set forth in parent application Serial No. (Attorney Docket #SSD-002) , where the interrupt structure and tasks are substantially removed from the tasks of the computing processor(s) (e.g. the GSPs) .
  • the separation is achieved by providing a central memory unit (data RAM) through which flows substantially all the data coming into and out of the signal processor, and by providing a data flow manager (i.e. a data I/O processor) which handles I/O between the central memory unit and the "outside" world.
  • the computing processor(s) is coupled to the central memory unit and does not.communicate directly with the outside world.
  • the multiple processors do not communicate directly; rather they communicate via the central memory unit.
  • the computing processors are shielded from the I/O functions of the SCDSP and are therefore capable of increased throughput, a mechanism for informing (signalling) the computing processors of events of interest such as the availability of desired information must be provided.
  • an event signalling system for a digital signal processor apparatus which has a central data RAM, a computing processor having an event occurrence circuitry, a data I/O processor, and a data RAM bus coupled to the data RAM, the computing processor and the I/O processor.
  • the event signalling system includes: an address code generating circuit in the data I/O processor for generating a predetermined address code and for writing the predetermined address code onto the data RAM bus upon the occurrence of an event of interest; a data RAM bus address decoder for monitoring the data RAM bus for predetermined address codes, and for generating a signal when a predetermined address code is written to the data RAM; and a flag bus coupled to the event occurrence circuitry of the computing processor for transmitting the signal generated by the data RAM bus address decoder to the event occurrence circuitry.
  • the computing processor also includes an address code generating means for signalling the occurrence of an event of interest, and access to the data RAM bus from the data I/O processor and the computing processor is time division multiplexed.
  • each data RAM bus is monitored by the data RAM bus address decoder.
  • the event signalling system is preferably utilized in conjunction with a digital signal processor apparatus having a plurality of data I/O processors, where each data I/O processor is coupled in a time division multiplexed manner to the data RAM bus, and each data I/O processor has an address code generating circuit which generates a different predetermined address code.
  • the data RAM bus address decoder monitors a plurality of predetermined addresses, and the flag bus is preferably a parallel bus.
  • each computing processor preferably has event occurence circuitry (e.g. a resettable register) which is coupled to the flag bus, and address code generating means coupled to the data RAM bus.
  • Figure 1 is a high level block diagram of a preferred digital signal processor having data flow managers, computing processors, a central data RAM and data RAM bus, and a data RAM bus decoder in which the event signalling system is embodied.
  • Figure 2 is a timing diagram of the access of the various components of the digital signal processor to the "multiported" data RAM via the time division multiplexed data RAM bus.
  • FIG. 3 is a partial block diagram of the computing processors (GSP ⁇ ) of the digital signal processor in which the event signalling system is embodied.
  • Figure 4a is a block diagram of the input side of the I/O processor (data flow manager) which includes an address code generating circuit.
  • Figure 4b is a representation of a FIFO which is implemented in the multiported data RAM, and which is utilized by the I/O processor.
  • FIG. 5 is a circuit diagram of the data RAM bus address decoder of the event signalling system invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • the preferred digital signal processor 10 includes: a central "multiported" data RAM 100 accessed via a time division multiplexed data RAM bus 125; a "multiported” program RAM 150 accessed via a time division multiplexed program RAM bus 155; a plurality of internal computing processors (GSP) 400 which are coupled to the data RAM bus 125 and the program RAM bus 155 and which perform general processing functions; a plurality of data flow managers (I/O processors or DFM's) 600 which are coupled to the data RAM bus 125 and which generally control the flow of data into and out of the digital signal processor 10 and relieve the GSPs from dealing with that data flow; a plurality of serial data ports 700 which are coupled to the DFMs 600; a host port 800 coupled to both the data RAM bus 125 and the program RAM bus 155, the host port serving to couple the SPROC via the host bus 165 to either an EPROM 170 in
  • the data RAM 100 is effectively multiported by causing access to the data RAM bus 125 to be time division multiplexed. As indicated in Figure 2, each GSP 400 is given a single time slot to either read from or write to the data RAM 100.
  • the fifth time slot (time s " ⁇ ot 2) is subdivided in time as follows: 50% for the host interface; and the remaining fifty percent equally divided among the access port 900, each of eight DFMs 600, and the probe 1000.
  • the RAMs 100 and 150 of the invention are preferably separate RAM devices and do not share memory spa ⁇ - .
  • the program RAM 150 is preferably a IK L__. 24 bit RAM which is assigned address locations 0000 to 03ff Hex.
  • the data RAM 100 is preferably a 3K by 24 bit data RAM with primary data RAM space of 2K assigned address 0800 to Offf Hex, and auxiliary register based space of IK assigned addresses 0400 to 07ff Hex.
  • addresses 0800 through 0813 Hex relate to the event signalling system. Eight of the those particular addresses are used by the eight DFMs to signal that the DFM has filled a buffer in the data R. ' with data, as described -.n more detail hereinafter.
  • the remainder of addresses 0800 through 0813 Hex may be used by the GSP computing processors 400 or by other components of the digital signal processor 10.
  • the computing processors (GSPs) 400 are substantially described by the details and functioning of six sections: a block controller 410; a program control logic block 420; a multiplier block 430; an ALU block 450; a flag or event occurrence block 460; and a data RAM address generator block 470.
  • Coupling all six sections, as well as a break register 492, a data access register 494, and a temporary register 496 is an internal twenty-four bit bus 490. All access from any of the sections or from the registers 492, 494, or 496 onto the internal bus 490 is via tristate drivers 429, 449a, 449b, 459, 469, 489, and 499.
  • Block controller 410 is comprised of instruction decoder 412, and sequencer 414.
  • the instruction decoder 412 when enabled, takes fourteen bits (nine bits of opcode, and five bits of operand) off of the data portion of the program RAM bus 155.
  • Six of the nine opcode bits are used to indicate the operation (instruction) which the GSP is to perform (e.g. add, shift, jump, etc.), with up to sixty-four instructions being accommodated.
  • an additional three bits of opcode are utilized to specify the addressing mode the GSP is to use.
  • the fifteen bits in the O register 472 of the address generator block 470 are used to select an address in the data RAM 100, and the data in that address of data RAM is used for the operation.
  • the five operand bits obtained by the instruction decoder 412 are used to specify which register of the numerous registers of the GSP is to place its contents onto the internal bus 490.
  • the fifteen bits of data in the 0 register are to be put into the fifteen sb slots of the internal bus 490
  • the fifteen bits are put into the fifteen lsb slots of the internal bus.
  • Instruction decoder 412 is not only coupled to the program RAM bus, but to the numerous multiplexers, tristate drivers, registers, etc. of the GSP via lines 416. Based on the instruction which is decoded by instruction decoder 412, various of those lines 416 are enabled in a sequence as determined by the sequencer 414. In effect, instruction decoder 412, and sequencer 414 are simply look-up charts, with instruction decoder 412 looking up which lines 416 must be enabled based on the code found in the nine bits of opcode, and sequencer 414 looking up the sequence to which the enabled lines must subscribe.
  • While instruction decoder 412 decodes whatever instruction is on the program RAM bus 155 when the GSP 400 is granted access to that bus, the instruction which is on the bus is generated and dictated by the program logic block 420.
  • Program control logic block 420 is comprised of a tristate driver 422, a program address value register 424 (also called the "P" register), an incrementer 425, an increment (I) register 426, a jump (J) register 428, a multiplexer 430, and a branch logic block 432.
  • the P register 424 contains the location of the program RAM 150 which con t ains the microinstructions which are to be used b ⁇ e GSP 400.
  • P register 424 writes that address onto tht, program RAM bus 155 by sending it to tristate driver 422 which acts as the bus interface. Updating of the P register 424 is accomplished via muxP 430 which chooses one of the twelve bit addresses stored in the I register 426 or the J register 428 based on information from branch logic block 432. The address stored in the I register is simply the next numerical address after the address stored in the P register, as a value of one is added at incrementer 425 to the value stored in P register 424. In most situations, muxP 430 will permit the P register 424 to be updated by the I register, and the sequential addressing of the program RAM will continue.
  • the multiplexer 430 will permit the address in the J register 428 to be loaded into the P register 424.
  • the decision to jump is made by the branch logic block 432 which reads the status of a plurality of status flags as is hereinafter discussed.
  • the address to which the jump is made is obtained by the J reg 428 from the internal bus 490,- which may obtain the address from any of the sections of the GSP 400 (or from the data RAM 100).
  • the wait flag block 460 (also referred to as the event occurrence circuitry) is comprised of two wait flag registers WFreg 462 and DFreg 464, a multiplexer 466, and OR gate 468.
  • the bits of the wait flag registers are typically set (i.e. written to) by data sent over the internal bus 490.
  • registers WFreg 462 and DFreg 464 are coupled to a flag bus 198 which is written to each time predetermined locations in the data RAM 125 are addressed as will be described in more detail hereinafter. In this manner, each bit of the wait flag registers 462 and 464 may be selectively cleared. When all of the bits in register WFreg 462 have been cleared due to the occurrences of specified events (e.g.
  • OR gate 468 is used to provide a status flag W which indicates the same. Status flag W is read by the branch logic block 432. In this manner, "jump on wait flag" commands may be executed.
  • the DFreg 464 of the wait flag block 460 functions similarly to the the WFreg 462, except that no signals indicating the presence of all zeros (or ones) are output by the DFreg.
  • the register In order to check the contents of the DFreg (or the WFreg, if all values in the WFreg are not zero) , the register must be selected to put its contents on the internal bus 490. The selection of one of the registers is made by the instruction decode 412 and sequencer 414, and the contents are forwarded via multiplexer 466 and the tristate driver 469.
  • An easy manner of determining whether the DFreg 464 has all zeros is to forward the contents of the DFreg 464 to the ALU 452, which will provide a status flag Z if the contents are zero.
  • the WF and DF registers of the wait flag block 460 also include bits which are cleared by "compute lines" (not shown) which function in a similar manner to the wait flag bus 198.
  • the compute lines are preferably coupled to hardware pins (not shown) and are useful in providing external timing information to the GSPs 400 and the DFMs 600 of the digital signal processor 10.
  • the final large block of the general signal processor is the data RAM address generator block 470 which includes bus wide OR gate 471, registers Oreg 472, Dreg 473, Lreg 474, Breg 476, Freg 477, adders 481, 482, and 483, multiplexers muxBFL 484, muxL 485, muxA 486, muxBF 487, muxO 488, and an address access block 489.
  • the Oreg 472 obtains the fifteen least significant bits of the instruction on the program RAM bus. If "absolute" addressing is desired, i.e.
  • the address to be written onto the data RAM bus is included in the program RAM microinstruction itself, the address is written into the Oreg 472, and then forwarded to the data RAM bus (a sixteenth bit having been added by a zero extender, not shown) via muxA 486 and the address access block 489. The sixteen bit address is then placed on the data RAM bus at the appropriate time. All other situations constitute "indexed" addressing, where the address to be put out on the data RAM bus is generated internally by the data RAM address generator block 47.0.
  • Addresses are generated by adding the values in the various registers.
  • the Oreg 472 is the offset register
  • the Dreg 473 is a decrement register
  • the Lreg 474 is a loop register which sets the length of a loop
  • the Breg 476 is a base address register
  • the Freg 477 is a frame address register which acts as a second base address register.
  • the 0 register obtains its data off of the program RAM bus
  • registers D, L, B and F obtain their data from the internal bus 490. If it is desired to add some offset value to the value in the base or frame register (i.e.
  • muxBF 487 selects appropriately the Breg 476 or the Freg 477
  • muxBFL 484 selects the value coming from muxBF 487
  • the Breg or Freg value is added to the offset value of the Oreg by the adder 483. That value is then selected by muxA 486 for output over the data RAM bus via the address access block 489.
  • muxA 486 for output over the data RAM bus via the address access block 489.
  • the value in the L register is added to the value in the B or F registers at adder 482, and the sum is passed via muxBFL 484 to adder 483 which adds the value to the value in the 0 register.
  • adder 481 By providing adder 481, and by coupling the decrement register Dreg and the loop register Lreg to the adder 481, registers an address loop is effectuated.
  • the Lreg sets the length of the loop, while the Dreg sets the value by which the loop is decremented.
  • the new value is fed back into the Lreg 475 via uxL 485.
  • the resulting value in the Lreg is decreased by the value of the Dreg. If added to the Breg or Freg, by ider 482, the address generated is a sequentially decrementin address where the value in the Dreg is positive, and a sequentially incrementing address where the value in the Dreg is negative.
  • the ability to loop is utilized not only to provide a decrementing (or incrementing) address for the data RAM bus, but is also utilized to effect changes in the program RAM address generation by providing a "decrement and jump on not equal" (DJNE) ability.
  • Th « output from the adder 481 is read by OR gate 471 which proviues a status flag L (loop) to branch logic block 432.
  • the status flag L maintains its value until the L register has looped around enough times to be decremented to the value zero. Before that point, when the Lreg is not zero, the next instruction of the GSP is dictated by the instruction indicated by the Jreg 428.
  • tne program jumps to the location of the Jreg instruction instead of continuing with the next instruction located in the I register.
  • the OR gate 471 goes low and toggles flag L.
  • C the next DJNE instruction, since the "not equal" state does not exist (i.e. the Lreg is zero)
  • branch logic 432 causes muxP 430 of the program logic block 420 to return to obtaining values from the lreg 426 instead of from the Jreg 428, and the program continues.
  • the values of any of the 0, D, L, B, or F registers may be placed on the internal bus 490, by having uxO 488 (and where appropriate mux BF 487) select the appropriate register and forward its contents via tristate driver 489 to the internal bus.
  • the data access port 494 is capable of reading data from and writing data to the data RAM and is given access to the data RAM in a time division multiplexed manner as previously described. In writing to the data RAM, the data access port 494 and the address access port 489 are activated simultaneously. In reading data from the RAM, the address access port 489 first places on the data RAM bus the data RAM address in which the desired data is stored. The data is then placed on the data RAM bus by the data RAM, and the data access port 494 which is essentially a dual tri-state driver, receives the data and passes it onto the internal bus 490 for storage in the desired GSP register.
  • the data RAM address generator block is capable of generating any desired address, including those addresses which are monitored by data RAM bus address decoder 196. While the generation of a monitored address is not hardwired so as to be automatic upon the occurrence of given events, the code contained in the program RAM 150 can be arranged to effectuate the monitored address generation at desired times. Thus, if it is desirable for a GSP to signal to other GSPs, the DFMs, or other circuits the occurrence of an event (e.g. the completion of a particular calculation) , the program RAM causes the GSP to have its data RAM address generator block 470 generate one of the addresses 0800 to 0813 Hex; the generated address not being one of the addresses generated by the DFMs 600 as discussed below.
  • FIG. 4a and 4b a block diagram of the input circuitry of the I/O processor t FM) 600 is seen, as is an example FIFO which relates to the Di ⁇ .
  • the DFM 600 serves the important function of handling the flow of data into and out of the processor apparatus so that GSPs of the processor apparatus need not be interrupted in their processing tasks.
  • the DFM takes data received by the serial port from the "world" outside of the particular processor apparatus and organizes it inside a FIFO such as the FIFO of Fig. 6b which is implemented in desired locations of the data RAM 100.
  • the DFM 600 takes data in a FIFO, and organizes it for output to a serial output port of the digital signal processor 10.
  • the DFM is also capable of directing data into a FIFO and drawing data from a FIFO at desired speeds so as to accommodate a decimation operation performed by the digital signal processor. Further, the DFM causes decoder 196 to place signals onto the flag bus 198 (and hence to the event occurrence circuitry 460 of the GSPs 400) regarding the status of the buffers.
  • the circuitry for receiving data from a serial port and organizing it for storage in a FIFO of the data RAM 100 is seen in Figure 4a.
  • the data flow itself is simple, with the data being sent from the serial port 700, via multiplexer 611 and tri-state driver 613 to the data slots of the data RAM bus 125.
  • Multiplexer 611 permits either data coming from serial port 700a or data generated as hereinafter described to be forwarded to driver 613.
  • Driver 613 is controlled as indicated such that data is only output on the data RAM bus 125 when the DFM 600 is enabled by the system-wide multiplexer clock scheme.
  • the organization of the data for output onto the data RAM bus as a twenty-four bit word is conducted by the serial port 700, as hereinafter described.
  • each DFM is arranged with buffers, counters, gates, etc. to generate data RAM FIFO addresses for the incoming data.
  • the DFM 600 has three registers 620, 622, 624, three counters 630, 632, and 634 associated with the three registers, an adder 636, a divide by two block 637, a multiplexer 638, seven logic gates 641, 642, 643, 644, 645, 646, and 647 (gates 642, 643, 645, and 647 being bus wide gates), and two delay blocks 648 and 649.
  • the three registers are respectively: the start of FIFO register 620 which stores the start location in the data RAM for the FIFO to be addressed by the particular serial port coupled to the particular part of the DFM; the index length register 622 which stores the number of buffers which comprise the FIFO (for the FIFO of Fig. 4b, the index length register would be set at four) , and the buffer length register 624 which stores the length of each buffer, i.e. the number of words that may be stored in each buffer (for the FIFO of Fig. 4b, the buffer length register would be set at eight).
  • the serial port 700a When a data word (twenty-four bits) is ready for sending to the data RAM for storage in a FIFO, the serial port 700a provides a ready signal which is used as a first input to AND gate 641.
  • the second input to AND gate 641 is a data enable signal which is the time division multiplexed signal which permits the DFM to place a word on the data RAM bus.
  • a high signal is output from the AND gate which causes driver 613 to output the data on the data RAM bus along with an address.
  • the address is that which is computed by the twelve bit adder 636, or a prewired address (e.g. one of addresses 0800 through 0813 Hex) , as will be described hereinafter.
  • the counter 634 associated with the buffer length register 624 is also incremented (after delay) .
  • the outputs of the buffer length register 624 and its associated counter 634 are provided to bus wide XNOR gate 643 which compares the values.
  • the output of XNOR gate 643 goes high, causing three input OR gate 644 to pass a high signal to the reset of counter 634.
  • the high signal from bus wide XNOR gate 643 is also fed to the counter 632 associated with the index length register 622, to the multiplexer 638, and to the multiplexer 611.
  • multiplexer 638 enables the prewired address to be placed in the address slots of the data RAM bus 125, along with one of two predetermined (or generated) data words which are generated as discussed below.
  • the placement of the prewired address and a data word on the bus at the end of buffer signal occurs upon the next data enable signal rec. ved by the DFM, which is before another word is assembled by the serial port 700a for sending to the data RAM 100.
  • a decoder 196 monitors the data RAM bus 125 for the particular prewired addresses of the DFMs; the triggering of these addresses occurring because of conditions in the DFM, i.e. the filling of buffers.
  • the decoder 196 in turn, can set a flag (the setting of the flag can be dependent on the value of the data accompanying the prewired address) on the trigger bus 198 which signals the GSPs 400 of the digital signal processor of the occurrence. In this manner, the GSPs 400 can determine that the data required to conduct an operation is available to the GSP, thereby causing the GSP to exit a wait loop or to change its execution course such as by branching.
  • the predetermined or generated data word placed on the bus after a FIFO buffer has been filled preferably uses a "1" as the msb of the data word if the FIFO buffer that has been filled causes the FIFO to be half filled (as described hereinafter) , or a "0" as the msb otherwise.
  • the remainder of the data word may be null information.
  • the data word may include the next location to which the DFM will write (i.e. the location computed by the twelve bit adder 636) which is inserted in appropriate locations of the data word.
  • This predetermined or generated data word is then passed via multiplexer 611 to driver 613 which places the data word on the bus at the same time the prewired address is placed on the data RAM bus 125.
  • counter 632 when an indication of a full buffer is output by bus wide XNOR gate 643, counter 632 is incremented. Counter 632 therefore tracks the number of the buffer in the FIFO that is being filled.
  • the number of the FIFO buffer being addressed (as determined by counter 632) is half of the FIFO length (as determined by the length stored in register 622, divided by divide by two block 637)
  • a flag is raised by the DFM via the bus wide XNOR gate 647.
  • the "mid buffer" flag indicates that the buffer in the FIFO being written to is halfway through the FIFO. Hence, if all previous buffers in the FIFO are still full with data, the FIFO is half full.
  • the mid buffer flag causes the generated data input to multiplexer 611 to be changed, such that the msb of the data is a "1" instead of a zero.
  • the msb of the data is a "1" instead of a zero.
  • a "clear counter” signal may also be generated by a oower up reset (PUR) signal which is generated by applying a jnal to a predetermined pin (not shown) of the digital signa processor, and by a SYNC signal which is generated by writing to address 0405H of the data RAM 100."
  • PUR oower up reset
  • SYNC SYNC signal
  • the input sectic . of one DFM can be synchronized to the output section of the same or another DFM. This synchronization is accomplished via a pin (not shown) on the digital signal processor which generates the "enbuf" in ⁇ ut into OR gate 644.
  • OR gate 644 provides a high signal which resets counter 634 in synchronization with the resetting of a similar counter in a DFM output section, details of which may be obtained by reference to parent application Serial No. (Docket #SSD-002) .
  • Fig. 4b an example of a FIFO associated with the DFM is seen.
  • the FIFOs associated with DFMs are contained in a preferably predetermined portion of the data RAM of the processor apparatus.
  • each buffer contains storage for eight data samples.
  • the FIFO of Fig. 4c has storage for thirty-two data samples.
  • a FIFO can contain a different number of buffers, and the buffers can store different numbers of data samples.
  • the size of the each FIFO associated with a DFM and the size of its buffers is either set automatically by intelligent software which calculates the requirements of the particular DFM, or by the user of the processor system during initial programming of the processor system.
  • the DFM is configured in its hardware to immediately generate and write a predetermined address to the address lines of data RAM bus 125.
  • the predetermined addresses to which the DFMs write is monitored by data RAM bus decoder 196.
  • the decoder 196 is logically comprised of an eleven input AND gate 2010, twenty six input NAND gates 2020 - 2033, and fifteen inverters 2050a - 2050o. -The first four bits of the twenty-four bit data address written to the address lines of the data RAM bus 125 are inverted by inverters 2050a - 2050d to select for hexadecimal "0".
  • the fifth bit of the address is passed directly to AND gate 2010, while the sixth through eighth bits are inverted by inverters 2050e - 205Og; the fifth through eighth bits for selecting the hex address "8".
  • the ninth through eleventh bits are inverted by inverters 2050h - 2050j to select in conjunction with a twelfth bit a hexadecimal "0" or "1", and the last five bits (the twelfth through sixteenth bits) are inverted by inverters 2050k - 2050o, and the uninverted and inverted states of the last five bits are provided in different combinations, along with the output of AND gate 2010, to the six input NAND gates to provi x.
  • an appropriate negative output on trigger bus 198 should any of addresses 0800 - 0813 be placed on the data bus 125 (i.e. received by the decoder 196) .
  • serial data flow into and out of the digital signal processor is primarily through the serial ports 700, while parallel data flows through the host port 800.
  • Serial data which is to be processed is sent into an input port 700 which is coupled to a DFM 600, which in turn forwards the data to appropriate locations (buffers) in the data RAM 100 via the time division multiplexed data RAM bus 125.
  • the DFM 600 also writes additional information to a predetermined data RAM location which is monitored by flag generating decoder 196.
  • Decoder 196 causes a flag or signal to be written on the trigger or flag bus 198 to inform the GSPs, and if desired the output sides of the DFMs of the occurrence of the event (buffer filled) .
  • event signalling systems for a digital signal processor apparatus. It will be appreciated by those skilled in the art that the method invention for signalling events occurring in a digital signal i rocessor apparatus is related directly to the event signalling system so described. It will also be appreciated that while particular embodiments have been descri/jed, it is not intended that the invention be limited thereto as it is intended that the invention be as broad in scope as the art will allow. Thus, while the decoder was described as decoding a certain number of particular predetermined addresses, it will be appreciated that the decoder could be a programmable decoder such that different addresses can be monitored, and the decoder can be arranged to decode any number of addresses.
  • the DFMs could be provided with logic circuitry and a program memory, such that the DFMs could generate address code in a manner similar to the GSPs. It will also be appreciated that while particular circuitry for the decoder and the address generating circuitry of the DFMs was set forth, it is well within the ability of those skilled in the art to provide other circuitry for accomplishing the same or similar functions. Therefore, it will be appreciated by those skilled in the art that yet other modifications could be made to the provided invention without deviating from its spirit and scope as so claimed.

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Abstract

Système signalant un événement pour un appareil de processeur de signaux numériques (10) qui comprend une RAM de données centrale (100), au moins un processeur de calcul (400), chaque processeur de calcul ayant un circuit d'occurrence des événements, une pluralité de processeurs d'entrée/sortie de données (600), et un bus de RAM de données (125) connecté à la RAM de données (100), au(x) processeur(s) de calcul (400) et aux processeurs d'entrée/sorte (600). Le système signalant les événements comprend un circuit générant un code d'adresse dans chaque processeur d'entrée/sortie de données (600) pour générer différents codes d'adresses prédéterminés pour chaque processeur d'entrée/sortie (600) et pour écrire les codes d'adresses prédéterminés sur le bus de RAM de données (125) lors de l'occurrence des événements recherchés. Les occurrences de codes d'adresses prédéterminés sur le bus RAM de données (125) sont examinées par un décodeur d'adresses (196) qui génère des signaux différents qui dépendent du code d'adresse prédéterminé qui a été trouvé. Les signaux provenant du décodeur d'adresses (196) son acheminés par un bus indicateur jusqu'au circuit d'occurrence des événements du ou des processeur(s) de calcul (400) et, si besoin est, jusqu'aux secteurs de sortie des processeurs d'entrée/sortie (600).
PCT/US1991/006713 1990-09-17 1991-09-17 Systeme de signalement d'evenement et procede pour un systeme de processeur comprenant une unite de memoire centrale Ceased WO1992005496A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US58350890A 1990-09-17 1990-09-17
US583,508 1990-09-17
PCT/US1991/003386 WO1991018342A1 (fr) 1990-05-18 1991-05-15 Architecture de processeur de signaux programmable
ATPCT/US91/03386 1991-05-15

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WO1992005496A1 true WO1992005496A1 (fr) 1992-04-02

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Publication number Priority date Publication date Assignee Title
US5278975A (en) * 1990-06-14 1994-01-11 Fujitsu Limited Synchronization control system in a parallel computer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3815104A (en) * 1973-01-18 1974-06-04 Lexitron Corp Information processing system
US4435759A (en) * 1981-06-15 1984-03-06 International Business Machines Corporation Hardware monitor for obtaining processor software/hardware interrelationships
US4477813A (en) * 1982-08-11 1984-10-16 Ball Corporation Microstrip antenna system having nonconductively coupled feedline

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3815104A (en) * 1973-01-18 1974-06-04 Lexitron Corp Information processing system
US4435759A (en) * 1981-06-15 1984-03-06 International Business Machines Corporation Hardware monitor for obtaining processor software/hardware interrelationships
US4477813A (en) * 1982-08-11 1984-10-16 Ball Corporation Microstrip antenna system having nonconductively coupled feedline

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