WO1994003921A3 - Bosses d'aplanissement pour l'interconnexion de groupements apparies d'electrodes - Google Patents

Bosses d'aplanissement pour l'interconnexion de groupements apparies d'electrodes Download PDF

Info

Publication number
WO1994003921A3
WO1994003921A3 PCT/US1993/006700 US9306700W WO9403921A3 WO 1994003921 A3 WO1994003921 A3 WO 1994003921A3 US 9306700 W US9306700 W US 9306700W WO 9403921 A3 WO9403921 A3 WO 9403921A3
Authority
WO
WIPO (PCT)
Prior art keywords
electrodes
bumps
planarizing
interconnecting
matching arrays
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1993/006700
Other languages
English (en)
Other versions
WO1994003921A2 (fr
Inventor
Stanley F Tead
Stephen J Znameroski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3M Co
Original Assignee
Minnesota Mining and Manufacturing Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Minnesota Mining and Manufacturing Co filed Critical Minnesota Mining and Manufacturing Co
Priority to EP93917226A priority Critical patent/EP0653105A1/fr
Priority to JP6505331A priority patent/JPH07509588A/ja
Priority to KR1019950700323A priority patent/KR950702746A/ko
Publication of WO1994003921A2 publication Critical patent/WO1994003921A2/fr
Publication of WO1994003921A3 publication Critical patent/WO1994003921A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)

Abstract

Afin de connecter un dispositif électronique comprenant une multiplicité d'électrodes à un autre dispositif électronique, on positionne des bosses métalliques entourées d'une résine sur des électrodes choisies. Les bosses sont ensuite façonnées au diamant de façon que les surfaces externes de toutes les bosses se trouvent sensiblement dans un même plan. La résine est ensuite enlevée.
PCT/US1993/006700 1992-07-30 1993-07-16 Bosses d'aplanissement pour l'interconnexion de groupements apparies d'electrodes Ceased WO1994003921A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP93917226A EP0653105A1 (fr) 1992-07-30 1993-07-16 Bosses d'aplanissement pour l'interconnexion de groupements apparies d'electrodes
JP6505331A JPH07509588A (ja) 1992-07-30 1993-07-16 電極配列を合わせる相互接続部のためのバンプの平坦化
KR1019950700323A KR950702746A (ko) 1992-07-30 1993-07-16 전극의 정합 어레이를 상호접속시키기 위한 범프의 평면화 방법(planarizing bumps for interconnecting matching arrays of electrodes)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US92255992A 1992-07-30 1992-07-30
US07/922,559 1992-07-30

Publications (2)

Publication Number Publication Date
WO1994003921A2 WO1994003921A2 (fr) 1994-02-17
WO1994003921A3 true WO1994003921A3 (fr) 1994-04-14

Family

ID=25447214

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1993/006700 Ceased WO1994003921A2 (fr) 1992-07-30 1993-07-16 Bosses d'aplanissement pour l'interconnexion de groupements apparies d'electrodes

Country Status (5)

Country Link
EP (1) EP0653105A1 (fr)
JP (1) JPH07509588A (fr)
KR (1) KR950702746A (fr)
CA (1) CA2139314A1 (fr)
WO (1) WO1994003921A2 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0316912A2 (fr) * 1987-11-18 1989-05-24 Casio Computer Company Limited Structure d'une électrode à protubérance d'un dispositif semi-conducteur et son procédé de fabrication
EP0426496A2 (fr) * 1989-11-03 1991-05-08 Minnesota Mining And Manufacturing Company Planarisation de substrats d'interconnexion par rotation d'un diamant
US5072520A (en) * 1990-10-23 1991-12-17 Rogers Corporation Method of manufacturing an interconnect device having coplanar contact bumps
JPH04116832A (ja) * 1990-09-06 1992-04-17 Matsushita Electron Corp バンプレベリング方法およびその装置
JPH04188734A (ja) * 1990-11-21 1992-07-07 Matsushita Electron Corp 半導体装置のバンプレベリング方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0316912A2 (fr) * 1987-11-18 1989-05-24 Casio Computer Company Limited Structure d'une électrode à protubérance d'un dispositif semi-conducteur et son procédé de fabrication
EP0426496A2 (fr) * 1989-11-03 1991-05-08 Minnesota Mining And Manufacturing Company Planarisation de substrats d'interconnexion par rotation d'un diamant
JPH04116832A (ja) * 1990-09-06 1992-04-17 Matsushita Electron Corp バンプレベリング方法およびその装置
US5072520A (en) * 1990-10-23 1991-12-17 Rogers Corporation Method of manufacturing an interconnect device having coplanar contact bumps
JPH04188734A (ja) * 1990-11-21 1992-07-07 Matsushita Electron Corp 半導体装置のバンプレベリング方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 16, no. 367 (E - 1245) 7 August 1992 (1992-08-07) *
PATENT ABSTRACTS OF JAPAN vol. 16, no. 508 (E - 1282) 20 October 1992 (1992-10-20) *

Also Published As

Publication number Publication date
EP0653105A1 (fr) 1995-05-17
KR950702746A (ko) 1995-07-29
JPH07509588A (ja) 1995-10-19
WO1994003921A2 (fr) 1994-02-17
CA2139314A1 (fr) 1994-02-17

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