WO1994010643A1 - Procede et appareil ameliores pour le traitement de donnees d'image - Google Patents

Procede et appareil ameliores pour le traitement de donnees d'image Download PDF

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Publication number
WO1994010643A1
WO1994010643A1 PCT/US1992/009461 US9209461W WO9410643A1 WO 1994010643 A1 WO1994010643 A1 WO 1994010643A1 US 9209461 W US9209461 W US 9209461W WO 9410643 A1 WO9410643 A1 WO 9410643A1
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Prior art keywords
signal
image
defining
src
signals
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Inventor
Robert Joseph Mical
David Lewis Needle
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3DO Co
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3DO Co
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Priority to AU30638/92A priority Critical patent/AU3063892A/en
Priority to PCT/US1992/009461 priority patent/WO1994010643A1/fr
Publication of WO1994010643A1 publication Critical patent/WO1994010643A1/fr
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—Three-dimensional [3D] image rendering
    • G06T15/50—Lighting effects

Definitions

  • the invention relates generally to image data processing.
  • the invention relates more specifically to a low cost method for providing shadowing, highlighting and other image processing functions in a system which processes images in the form of digital signals.
  • Patent Application Serial No. bearing the same title, same inventors and also filed concurrently herewith;
  • PCT Patent Application Serial No. entitled SPRYTE RENDERING SYSTEM WITH IMPROVED CORNER CALCULATING ENGINE AND IMPROVED POLYGON-PAINT ENGINE, by inventors Needle et al., filed concurrently herewith, Attorney Docket No. MDI04232, and also to U.S. Patent Application Serial No. , bearing the same title, same inventors and also filed concurrently herewith;
  • PCT Patent Application Serial No. entitled METHOD AND APPARATUS FOR UPDATING A CLUT DURING HORIZONTAL BLANKING, by inventors Mical et al., filed concurrently herewith, Attorney Docket No. MDIO4250, and also to U.S. Patent Application Serial No. , bearing the same title, same inventors and also filed concurrently herewith;
  • PCT Patent Application Serial No. entitled PLAYER BUS APPARATUS AND METHOD, by inventors Needle et al., filed concurrently herewith, Attorney Docket No. MDIO4270, and also to U.S. Patent Application Serial No. , bearing the same title, same inventors and also filed concurrently herewith.
  • the visual realism of imagery generated by digital video game systems, simulators and the like can be enhanced by providing special effects such as shadowing, ' highlighting and so forth.
  • shadowing For example, when the image of an airplane is to be displayed flying over a flat terrain on a sunny day, the realism of the overall scene is enhanced by generating a shadow image of the airplane within the image of the terrain. The effect appears more realistic when the terrain region onto which the shadow is projected becomes dimmed rather than completely blackened. The observer continues to see part of the texture of the terrain even though it is covered by the airplane's shadow. The effect is referred to as "shadowing.”
  • Highlighting is another example of realism-imparting effects.
  • an explosive device is displayed detonating near the airplane.
  • Visual realism is enhanced by momentarily increasing the brightness (highlighting) of the airplane's image to create the impression that light from the explosion is reflecting off the airplane's fuselage.
  • the effect appears more realistic when certain brightness and/or colorization relationships between - ' - different parts of the airplane (e.g. , cockpit, fuselage, wings) are maintained.
  • Home game systems such as the Sega "Genesis” have a two-source image merging system for creating shadowing and highlighting effects on-the-fly (in real time) .
  • sprite (rectangular block of bit-mapped data representing the airplane shadow region) is overlaid with a second source tile representing the underlying terrain. For every pixel position where the first (shadow) sprite intensity is non-zero, a digital signal representing the corresponding terrain intensity in the second tile is cut in half to thereby produce a "dimming" effect. The dimmed version of the terrain tile is then output as part of the video image. (The dimmed image data is not stored in memory however.)
  • the Sega "GenesisTM” system divides the shading value of all pixels within the airplane's sprite by two and then adds half the maximum shading value to each such pixel. This preserves the relative shading relation between parts of the airplane while making each brighter.
  • the augmented version of the airplane tile is then output as part of the video signal, but not saved. It is not possible to both shade and highlight a tile at the same time in the Sega "GenesisTM" system.
  • SUBSTITUTESHEET windows approaching from the outside of the chamber at an angle relative to the stained glass windows.
  • the scene is to be projected through, or displayed on, a two- dimensional window (hereafter, the observation plane) .
  • the position of the observation plane (the window through which the game player views the scene) is to rotate slowly about the hero, thus giving a three-dimensional quality to the displayed two- dimensional scene.
  • Realistic rendering of such a scene has to take into consideration the transformation of outside light as the light passes at various angles through the stained glass windows to the observation plane. It also has to take into account the reflection of internal lighting off the stained glass windows toward the observer's plane.
  • the villain throws a rock through one of the stained glass windows, the visual effects of the hole have to replace those of the removed window material. If the villain flings mud onto a window, the transparency and coloration of the affected window regions have to change accordingly.
  • a signal processing apparatus in accordance with the invention comprises one or a plurality of pixel- component processing units (e.g.
  • each pixel-component processing unit includes: (a) first input selector means [211] for receiving and selecting one of a first set of plural image-defining signals; (b) second input selector means [212] for receiving and selecting an image-defining signal either from the first set or from a second set of plural image-defining signals; (c) multiply-factor selector means [222] for receiving and selecting one of a set of plural multiply values; (d) multiplier means [225], coupled to the first input selector means and the multiply-factor selector means, for producing a multiplied signal [226] representing the product of the value of an image-defining signal selected by the first input selector means [211] and a multiply value [MV] selected by the multiply-factor selector means [222]; (e) first divider means [231], coupled to the output of the multiplier means, for producing a left-side pre-scaled signal [210o] representing the value of the multiplied signal produced by multiplier means [225
  • TE SHEET - 1 producing a post-scaled signal [275] representing the value of the sum signal produced by the adder means [260] divided by the value represented by a supplied third- divide factor defining signal [Dv2']; and (h) wrap limiter means [280] for producing an optionally-limited signal representing the output of the third divider means [270] where the value of said optionally-limited signal is equal to the value of the signal produced by the combination of the adder means [240] and the second divider means [250], optionally limited to predefined minimum and maximum values [0 and 31].
  • the signal processing apparatus of the invention can apply a variety of effects to supplied image signals including scaling them through a "grey-openacity” operation (defined in the below detailed description) , scaling them through a “color-openacity” operation (defined in the below detailed description) , summing or subtracting the signals of two sources to produce a "fredluscence” effect, and cross-multiplying one of the supplied signals against another on a pixel-by-pixel basis using a “doloresizing” operation (defined in the below detailed description) .
  • a method for defining the color or intensity of a destination pixel in accordance with the invention comprises the steps of: (a) receiving first and second source-image defining signals [SRC-A, SRC-B] ; (b) selecting and scaling one of the first and second source- image defining signals [SRC-A, SRC-B] in accordance with a selected scaling factor [MV/Dvl] where the selected scaling factor can be itself defined by contents [D-bit] of one [SRC-A] of the first and second source-image defining signals; and (c) optionally combining [240, 260] the scaled image-defining signal [210o] with a second [220o] of the first and second source-image defining signals [SRC-A, SRC-B] to thereby define the color or intensity of a destination pixel.
  • the above signal combining step can include adding and/or exclusive ORring together the signals to be merged.
  • FIGURE 1 (composed of subportions IA and IB) is a block diagram of an image processing and display system in accordance with the invention.
  • FIGURE 2 (composed of subportions 2A and 2B) is a schematic diagram illustrating a vector processing pipeline within the PPMP section of the system shown in Fig. 1.
  • FIG. 1 a block diagram of an image processing and display (IPAD) system 100 in accordance with the invention is shown.
  • IPAD system 100 A key feature of IPAD system 100 is that it is relatively low in cost and yet it provides mechanisms for handling complex image scenes in real time. This feature is made possible by including a Pen and Palette Manipulation Processor (PPMP) 200 on a single integrated circuit (IC) chip within the IPAD system 100.
  • PPMP Pen and Palette Manipulation Processor
  • FIG. 1 (which is composed of subfigures IA and IB, as indicated by the key) provides an overview of the IPAD system 100.
  • CMOS complementarymetal-oxide-semiconductor
  • An off-board power supply (not shown) delivers electrical power to the board.
  • the IPAD system 100 is functionally divided into a destination-pixels color determining section (also referred to as a source-to- destination color mapping section) and a destination- image geometry determining section (also referred to as a source-to-destination point-to-point mapping section) .
  • the color mapping section is charged with the task of receiving electrical or other signals representing the color and/or shading and/or illumination of the one or more pixels in one or more bit-mapped source images and converting these into electrical or other signals representing the color and/or shading and/or illumination of the one or more corresponding pixels in a bit-mapped destination image in accordance with user-supplied color- mapping control signals.
  • the PPMP unit 200 (Fig.s IB, 2A, 2B) resides within the color mapping section.
  • the point-to-point mapping section is charged with the task of receiving electrical or other geometry-control signals representing a source- to-destination point-to-point mapping and identifying specific pixels within a bit-mapped destination image whose colors and/or shadings and/or intensities are to be changed to reflect a painting-over of a geometric region within the destination image by colors derived
  • SHEET from a source image.
  • the shape and size of the painted- over region is defined by the geometry-control signals.
  • the IPAD system 100 includes a central processor unit (CPU) 110 (Fig. IA) , an addressable system memory which includes a video random- access memory unit (VRAM) 120, a display driver 150 (Fig. IB) and a video display unit 160 (Fig. IB) .
  • the video display unit 160 is located off board 99 and its circuitry can be implemented in technologies other than CMOS.
  • the link between board 99 and display 160 can be provided through a baseband connection or by way of an RF modulator/demodulator pair.
  • CPU 110 is preferably a RISC type ARM610 microprocessor available from Advanced RISC Machines Limited of Cambridge, U.K.
  • the CPU 110 is operatively coupled to the video random-access memory (VRAM) 120 such that the CPU 110 has read/write access to various control and image data structures stored within VRAM 120.
  • VRAM video random-access memory
  • the CPU type is immaterial.
  • a MOS Tech. 6502 would do just as well.
  • any means for loading VRAM 120 with a desired set of control instructions and image data will do just as well.
  • Once appropriate data is loaded into VRAM 120 (or other parts of system memory, e.g., DRAM) the color and point-to-point mapping sections take control of VRAM 120 (or other system memory parts) , fetch source image data and write back destination image data.
  • Direct memory access (DMA) hardware is provided for accessing contents of the VRAM 120 (or other parts of system memory) at high-speed within a so-called memory- address manipulator chip (MAMC) 101.
  • Data within VRAM 120 (or other parts of system memory) is read or written on a time-multiplexed basis.
  • the memory address manipulator chip (MAMC) 101 supplies memory address signals 12Oa to system memory at system-defined time slots.
  • a memory-read tag 120b or memory-write tag 12Oc accompanies each address signal.
  • Corresponding data signals flow into or out of system memory (VRAM 120) on a 32-bit wide D-bus 12Od.
  • the CPU 110 accesses data within the VRAM 120 (or other parts of system memory, not shown) by sending an access request to the memory address manipulator chip (MAMC) 101 and waiting for a grant from the MAMC 101 of a time slot on D-bus 120d.
  • the memory address manipulator chip (MAMC) 101 includes a set of so-called "geometry-control engines" 101c. These engines 101c include corner-calculating engines (not shown) that determine what pixel or pixels in a source image are to be mapped to a destination grid (bit-mapped destination image) and what the destination grid coordinates will be for the corners of each source pixel that is to be mapped to the destination grid.
  • the geometry-control engines 101c also include an address- translating means (not shown) for converting destination grid coordinate values into signals representing corresponding memory addresses of VRAM 120 (or other parts of system memory) .
  • the geometry-control engines 101c periodically control the ADDRESS, READ and WRITE control lines (120a, 120b, 120c) of VRAM 120 and that the geometry-control engines 101c respond to a supplied set of so-called "transparency-control signals" (T-bits output from IPS unit 103 of Fig. IA) by not performing what would otherwise be a write of a destination-pixel color-code signal (open signal) into VRAM 120 when a corresponding T-bit is active (logic true) . This creates the effect of a transparent hole in the rendered image.
  • T-bits output from IPS unit 103 of Fig. IA so-called "transparency-control signals”
  • the geometry-control engines 101c also respond to a supplied set of so-called "R-mode control signals" (R/W-bits) by converting what would otherwise be an address signal 120a tagged with a write flag 120c into an address signal 120a tagged with a read flag 120b when a corresponding R-bit is active (logic true) .
  • R-mode control signals R/W-bits
  • the VRAM 120 has the capacity to store 1 megabyte of data but it can be expanded to store 2, 4 or 16 megabytes of data. (A byte consists of eight bits of data.) One megabyte is a preferred but not absolute minimum storage capacity.
  • the system will work with a VRAM of smaller capacity also.
  • the CPU 110 reads and writes data from/into the VRAM 120 in the form of 32-bit wide "words" that are transferred over D-bus 12Od. Physically, the VRAM 120 is split into left and right banks each having its own independent address port and each having a 16-bit wide data port. This gives hardware devices, such a soon-to- be described CLUT/INT unit 140, simultaneous access to two separately addressable 16-bit "half-words". For most instances of concern here, it can be assumed that the same address is applied to both banks (not shown) of VRAM 120 and as such, VRAM 120 can be considered a unitary whole.
  • VRAM 120 is programmed to contain image-defining data in a variety of VRAM address regions, including regions 121, 123a and 123b. VRAM 120 also contains image-rendering control data (e.g. SCoB data) in regions such as 125 and 126. VRAM 120 further contains instruction code for execution by the CPU 110 in other regions (not shown) . Image-defining data within VRAM 120 is divided into two basic kinds, literal (unpacked) and non-literal (compressed) . There are two formats for literal image data: TLFB (Totally Literal Frame Buffer format) and TLNF (Totally Literal NonFrame-buffer format) .
  • TLFB totally Literal Frame Buffer format
  • TLNF totally Literal NonFrame-buffer format
  • TLFB and TLNF formats contain only pixel-shading information — there is no spryte-shape defining information. (The term "spryte" will be defined shortly) .
  • TLFB format is distinguished from TLNF format in that the former is structured to conform with the physical left/right bank addressing structure of VRAM 120 while the latter is not.
  • compressed data uses fewer bits per pixel for shade-definition than does literal data.
  • a key difference between the non-literal (compressed) image-defining data and the literal data of IPAD system 100 is that the former includes information for defining non-rectangularly shaped image areas (sprytes) while the latter is constrained to defining image areas as square or rectangular blocks.
  • spryte will be explained in detail shortly. For now it is sufficient to define a spryte as a collection of image lines wherein each image line can have a different length.
  • Regions 123a (Fig. IA) and 123b (Fig. IB) are shown to contain literal image data while region 121 (Fig. IA) is shown to contain non-literal image data.
  • Region 123b is designated as the "Current Frame Buffer” (cFB) by a system variable (by data in a hardware register called REGCTL2, not shown).
  • the system variable (cFB pointer) can be switched at any time to designate region 123a rather than 123b as being the cFB.
  • region 123a is sometimes referred to here as the "alternate Frame Buffer" (aFB for short) .
  • the non-literal image data in region 121 has to be "unpacked” from its compressed format into literal form before it can be written into desired portions of TLFB regions 123a and/or 123b, and thereafter used intelligently by the display hardware (140, 150, 160,. Fig. IB) to produce a displayed image.
  • Literal image data consumes more memory space per pixel than does nonliteral data but the former does not require unpacking prior to display.
  • Display driver 150 is a multi-format video display driver that is operatively coupled to VRAM 120 by way of a Color Look-Up Table unit (CLUT) and pixel interpolating (INT) unit 140 to produce NTSC format video signals and/or Super-VHS video signals and/or PAL (European Standard) video format.
  • CLUT converts VRAM-internal data (which is extracted over video-output lines 141, 142) from a 14 or 15 shading-bits-per pixel format (referred to hereafter as the "PEN" code) to a 24 shading-bits-per pixel format.
  • PEN shading-bits-per pixel format
  • the interpolator uses so-called horizontal and vertical subposition bits (SP) that are stored together with the PEN codes to optionally expand the received frame data from an apparent 320-by- 240 pixel (P) format to an apparent 640P-by-480P format.
  • SP horizontal and vertical subposition bits
  • P apparent 320-by- 240 pixel
  • 640P-by-480P apparent 640P-by-480P format.
  • Data within cFB 123b can also be displayed in its non- expanded 320P-by-240P formats.
  • Display driver 150 periodically fetches TLFB- formatted display data (e.g. at a rate of 60 fields a
  • the video display unit 160 e.g., color television monitor or color liquid crystal display panel
  • each pair of frames (a frame consists of two fields) is divided into four interlaced fields (FIELDS 1, 2, 3 and 0).
  • the four fields are sequentially flashed to the eyes of an observer (not shown) over time to create the illusion of an animated scene.
  • the viewer may be wearing stereoscopic eyeglasses (e.g., liquid crystal shutters, not shown) which alternatively block light from reaching one or the other of the viewers left and right eyes so as to create a three-dimensional effect.
  • the stereoscopic image is appropriately distributed across FIELDS 0-1 and 2-3 for such instances.
  • the cFB pointer (not shown) has designated region 123b as the "current frame buffer” (cFB) .
  • the video display driver 150 is shown to be conceptually receiving its data from the designated cFB region 123b.
  • Any region of VRAM 120 can serve as the cFB.
  • Data transfer lines 111 through 117 represent respective transfers of data over D-bus I20d between VRAM 120 and a corresponding other component of IPAD system 100. They are to be viewed as conceptual rather than physical constructs. The transfers actually occur over D-bus 120d.
  • VRAM data is selectively "routed" between certain components and selected regions of VRAM 120.
  • implied data routers 101a, 101b (Fig. IA) and lOld (Fig. IB) are shown interposed between some of the data- transfer lines (e.g., Ill, 113, 116) and the data sending or receiving component.
  • the implied functions of routers 101a,b,d are instead performed by the memory address manipulator chip (MAMC) 101. Time-multiplexed utilization of the system address bus 120a and system D-bus 12Od is used to route data between different hardware locations. Implied routers
  • SUBSTIT 101a, 101b and lOld are therefore to be viewed as being simply direct connections from the system D-bus 12Od to the designated component.
  • Their implied functions, however, which are performed by the MAMC 101 are respectively: a selective routing 101a of data from a specified first source-image region (e.g., 121) of VRAM 120 to a data-unpacking unit 102; a selective routing 101b of data from a specified second source-image region (e.g., 123a or 123b) of VRAM 120 to a "B-FIFO" unit 105b; and a selective routing 10Id of data from a set of oPEN- code storing registers 109 to a specified destination region (e.g., 123b or 123a) of VRAM 120.
  • the cFB region defines a 320-by-240 matrix of square pixels.
  • the color and/or intensity of each cFB pixel is represented by a 16-bit-wide data field.
  • the 16-bit wide data field is elsewhere referred to as a PEN code.
  • the PEN code is decoded by the CLUT/INT unit 140 to define the final color and/or shading and/or illumination value of each displayed pixel.
  • 5 of the 16 PEN bits define one out of 32 possible Red gun intensities
  • 5 of the bits define one out of 32 possible Green gun intensities
  • 4 (or 5 depending on whether a two or one SP-bits per pixel interpolation mode is selected) of the bits define one out of 16 (or one of 32, depending on mode) possible Blue gun intensities.
  • H and V subposition bits (SPpj and SPy) • They are used by the image interpolating portion of unit 140 for visual field expansion.
  • the format of the cFB 123 is 320 x 240 pixels, it is possible to expand it into an apparent 640 x 480 pixels format by judiciously weighting and copying the shading value of each original pixel in the 320 x 240 format to a selected one of 4 corresponding pixel spaces (pixettes) in the 640 x 480 format. The remaining three pixel spaces (pixettes) in the higher resolution image are similarly filled through the use of an interpolation algorithm.
  • area Y3 is referred to as a "nontransparent" portion of the tbr-Spryte 121a.
  • the painted Sp-region, RY3, is shaped the same as the non-transparent portion Y3 of the tbr-Spryte 121a to indicate that, when spryte rendition completes, the pixels of Sp-region RY3 will have been derived (mapped) from pixel information contained in the tbr-Spryte 121a.
  • image data from VRAM region 121 flows along a data-transfer path 111 by way of implied data-router 101a, into unpacking unit 102, and then through an unpacked-code processing-unit (IPS) 103, and then into an A-FIFO 105a, which is followed by the PPMP unit 200 (Fig. IB) , a demultiplexer 108, a set of oPEN codes storing registers 109 and implied destination-router lOld, into region 123b of the VRAM 120; in the recited order.
  • IPS unpacked-code processing-unit
  • a conventional "sprite” consists of a rectangularly-shaped area of image data such as rectangular region X2 shown within buffer area 123a (Fig. IA) .
  • Conventional systems create the illusion of animation by periodically changing the relative position of their current rectangular sprites on the display screen. The internal data contents of the sprites are also changed over time. It has been found through experience that internal change of data contents within a conventional sprite predominantly take place within non-rectangular subportions (e.g., RY1, RY2) of the rectangular areas (e.g., XI, X2) . No changes take place in the other N.C. subportions of each rectangular area. Time and memory is wasted in conventional systems by repeatedly rendering the nonchanging (N.C.) subportions.
  • the present system 100 utilizes an image construct that is referred to here as a "spryte”. (Note: the pronunciation is the same as “sprite” but the spelling is different.)
  • a "spryte” is defined as a compilation of horizontal scan-line segments 129 extending from and to the right of a vertical (hypothetical) spryte edge line 128.
  • the top of the spryte edge line is defined by a spryte corner position 127.
  • the total number of horizontal lines 129 which collectively define a spryte is given by a spryte line count
  • SUBSTITUTE SH that is stored in a hardware register (not shown) .
  • a VCNT control word is defined in a below Table 1.6 entitled, SPRYTE PREAMBLE WORDS) .
  • the horizontal scan lines 129 which define a single spryte (e.g. tbr-Spryte 121a) can be each of a different length. Their lengths can vary from zero pixels to the maximum number of pixels per line allowed in the system (1024 max pixels per spryte row in one embodiment of the invention) .
  • Each horizontal scan line 129 of a spryte can include a plurality of "transparent-code" pixels (T's) and/or a plurality of "non-transparent code" pixels (N's) .
  • the right end of each horizontal scan line 129 is defined either by an End-of-Line (EOL) terminator code or a line length count stored within a line-length counter (not shown) .
  • EOL End-of-Line
  • Non-transparent pixel codes can be used to overwrite the PEN codes of corresponding pixel positions in a rendition destination area such as RY3.
  • Transparent-pixel codes are used as position holders (or shape-definers) and they are not used to overwrite the PEN codes of corresponding pixel positions in a rendition destination area (e.g. the area outside of RY3) .
  • a reference spot 122 (Fig. IB) , corresponding to spryte top-left corner 127 (Fig. IA) , is defined in the destination area 123b.
  • the geometry-control engines 101c of MAMC unit 101 are charged with the task of generating an address signal [XPOS, YPOS] that points to location 122 of VRAM 120.)
  • T's Transparent-pixel
  • Y3 For each Transparent-pixel (T's) found in the source spryte Y3, a corresponding one or more destination pixels (or fractional destination pixels, depending on whether image expansion or compression is also taking place) are
  • destination region RY3 is filled with image data originating from nontransparent portion Y3 of tbr.-Spryte 121a.
  • Each literal image defining region e.g., cFB 123b or alternate frame buffer region 123a
  • Each spryte-filled region e.g., RY1, RY2, RY3 can have a different outline.
  • the hardware of system 100 is specially designed for rendering one or more lines of each source spryte in minimal time and for using a minimal amount of integrated-circuit die area.
  • the spryte-rendering hardware includes the soon-to-be detailed PMPP unit 200 and other components, some of which have already been mentioned (e.g., unpacker 102, IPS unit 103, A-FIFO 105a, demultiplexer 108 and OPEN codes storing registers 109) .
  • Each to-be-rendered spryte (e.g. tbr-Spryte 121a) is associated with a Spryte-rendition Control Block (SCoB) such as the one illustrated at 126 (Fig. IB).
  • SCoB 126 for example, is associated with source spryte region 121a and destination region X3 (a subregion of 123b that includes rendition starting point 122) .
  • the VRAM 120 includes a SCoB Associating Register File (SCARF, not shown) which links each to-be-rendered spryte (e.g., 121a) to a SCoB.
  • SCARF SCoB Associating Register File
  • a SCoB can be generally described as a 15-word wide by 32-bits deep region of VRAM 120 (some fields of the SCoB are less than 32 bits deep, as will be seen shortly) .
  • the SCoB contains source-to-destination color- mapping control words and/or flag bits plus source-to- destination point-to-point mapping control words and/or bits. Two of these control words define the X-by-Y positioning of the spryte rendering spot 122 relative to a (0,0) Universe origin of a displayable scene.
  • Table 1.0 describes these and other parameters in more detail.
  • Starting point 122 of a spryte rendition is defined in Table 1.0 by the two 32-bit wide variables, XPOS and YPOS.
  • Spryte rendition takes place by stepping through a linked list having one or more SCoB's. After a first source spryte is mapped to, and painted onto a destination grid area defined by its SCoB, the spryte- rendering engine processes the next SCoB, if any, and renders its source spryte onto its designated destination surface.
  • the linked list can be circular if desired so that the process is repeated iteratively.
  • Pen Index Palette PIP
  • Horizontal position in 640-max pixels format in the destination grid of the upper left corner of the to-be rendered SPRYTE, including 16 bits which represent a fraction (noninteger) position-defining portion.
  • PPMP control word (two halfwords: 16, 16).
  • FLAGS Data Structure FLAGS (These flag bits control specific fetching and rendering operations of the spryte-rendering engine. The data specific control bits are found in the preamble word of the source data.)
  • B21 YOXY Translate the XY values to a system memory address value and write the corresponding data to the hardware.
  • the PPMP control word has two 16-bit wide halves. One half is used when the
  • 0 MxF (source is SCoB)
  • 1 MUL (source is IPS)
  • 2 IPNM (source is IPS)
  • 3 xx (multiply by default value, 1 or 0).
  • Bits Function AVO Invert the output of the second divider in the PMPP and set the carry-in of the adder.
  • AVI Enable the sign-extend function for the signals flowing down the second math side of the PMPP (Post possible XOR).
  • AV2 Disable the wrap-limiter function. (Use the 5 LSB's of the 8-bit adder output and ignore possibility that it wrapped above decimal 31 or below decimal zero.)
  • B29:B28 B0POS B0 oPEN selector for output of PMPP. (This bit can also function as a subposition defining bit that is used by the pre-display interpolater.)
  • the first 6 words of a SCoB (FLAGS, NEXTPTR, SOURCEPTR, PIPPTR, XPOS, YPOS) are always read out of VRAM by the DMA engine (inside the memory address manipulator chip (MAMC) and generally placed into corresponding hardware registers.
  • the remainder of the SCoB words are optionally downloaded into the hardware.
  • the hardware registers are left in their pre-existing states if the corresponding SCoB words are not downloaded.
  • the optionally downloaded 7 SCoB words are be divided into the following successive groups: (a) Size and slope data (4 words), (b) Perspective or skew-control data (2 words: DDX & DDY), and finally (c) the PPMP control word (1 word). These 7 SCoB words are read out of VRAM as one burst regardless of which specific ones have been requested.
  • the preamble word or words are read out of VRAM. This is not optional.
  • Non-totally literal Sprytes require 1 word preamble. Totally literal Sprytes require 2 words of preamble. These preamble words may be located at the end of the SCoB words (but before the PIP) or at the start of the image data. The normal location for these words is at the start of the image data, but totally literal Sprytes that are in frame buffer format will want to not damage their rectangular space with 2 extra words. We are using a stand alone bit for the selection just to keep is all simple.
  • Non-totally literal Sprytes can be compacted to save both memory space and rendering time.
  • Each source scan line of data has its horizontal word size specified as part of the data.
  • Totally literal Sprytes have a rectangular format that is specified in the preamble of the data. ⁇ END OF TABLE 1.5 >
  • B15->B6 VCNT Vertical number of source data lines in this image data -1. (10 bits)
  • B5 Reserved set to 0.
  • VCNT line count -1.
  • the LINEAR bit only applies when the BPP type is 8 bits per pixel or 16 bits per pixel. In those cases, there are enough PIN bits to provide a 15 bit IPN without using the PIP. Since the PIN bits are spread linearly across the IPN, and it will result in a linear translation from PIN to IPN, the mode is called 'LINEAR'. The only 2 valid uses are for LINEAR 8 and LINEAR 16 (as opposed to 'normal' 8 or 16).
  • the REP8 bit only has an effect in the 8 bit source data size.
  • the BPP control bits decode as follows:
  • B31->B24 WOFFSET(8). Word offset from one line of data to the next (-2) (8 bits). bits 23- > 16 of offset are set to 0.
  • B25->B16 WOFFSET(IO). Word offset from one line of data to the next (-2) (10 bits). bits 31->26 of offset are set to 0.
  • BIO- > BO TLHPCNT Horizontal pixel count (-1) (11 bits).
  • the source data has the frame buffer format of the screen as a source format. Vertically adjacent pixels in the rectangular display space are horizontally adjacent in the 2 halves of a memory word. This is useful for 16 BPP totally literal.
  • the unpacker will disable the 'B' FIFO data requests and alternately place pixels from the source into both FIFOs. Left 16 bits go to 'A' FIFO, right 16 bits go to 'B' FIFO.
  • the data requests for 'A' FIFO will be made in a request 'pair' to insure the reduction of page breaks and '6 tick latencies'.
  • the hardware will lock the corner engines (regardless of the LCE bit).
  • TLHPCNT is the number of pixels in the horizontal dimension (-1). This is the number of pixels that will be attempted to be rendered for each horizontal line of the Spryte. This value is used by the data unpacker. A '0' in the value will attempt 1 pixel. A '-1' in the value will attempt many pixels. There is no 'zero pixel count' value.
  • WOFFSET is the offset in words of memory from the start of one line of data to the start of the next line (-2). If the BPP for this Spryte is 8 or 16, use WOFFSET(IO), else use WOFFSET(8). This number is a zero for the minimum sized Spryte (2 words).
  • the DMA engine will also use WOFFSET as the length value in the normal data fetch process. If WOFFSET and TLHPCNT are set badly, WOFFSET may expire first and the DMA engine will not cope properly. ⁇ END OF TABLE 1.6 >
  • the first one or two bytes are the word offset from the start of this line of source data to the start of the next line of data (-2).
  • bits 31-> 16 are used.
  • the actual offset has a maximum size of 10 bits.
  • the rest of the bits in the 2 bytes are set to 0. 10 bits of word offset is 2048 pixels at 16BPP. 8 bits of word offset at 6 BPP is 1365 pixels. The requirement is 1280 pixels.
  • This offset is used by the DMA controller to both calculate the start of the next line of data (by adding it to the start of the current line), and to set the maximum length (by subtracting 1 and placing it in the DMA length register) of the current DMA transfer.
  • This offset value ( 1 or 2 bytes) is not used by the data unpacker. It will arrive at the data unpacker at the start of each line of a packed Spryte and must be discarded.
  • the next data after the offset is comprised of 1 control byte and 0 or more bits of PIN data.
  • the number of bits used for each PIN is specified by BPP.
  • the Spryte rendering process is started from the CPU by writing a meaningless value to the 'SPRSTRT' address in the memory address manipulator chip
  • the Spryte process is stopped cold when the CPU writes to 'SPRSTOP'. All intermediate states of the engines have been RESET. The data pointers are now WRONG. Spryte processing is dead. Except, of course, for the SPRPAUS flipflop.
  • Spryte processing is not overlapped in the hardware.
  • One Spryte is allowed to totally complete prior to starting the next Spryte in the list. This total completion includes the processing of trailing transparent pixels and the outputting of the last data values to memory.
  • the CPU can request that the Spryte rendering engine stop operating at the end of the current Spryte but not reset itself by writing to 'SPRPAUS'. This will set a 'SPRPAUS' flipflop that will cause the Spryte rendering engine to set its 'PAUSE' flipflop at the end of the current Spryte.
  • the PAUSE flipflop is set by this mechanism (not by other means)
  • the SPRPAUS flipflop will be cleared.
  • the SPRPAUS event is only a one shot thing. Obviously this can only be done if the CPU already has access to the system bus.
  • SPRPAUS can be set by the CPU even if the Spryte engine is off. When an interrupt is present, the PAUSE flipflop is held in a 'set' condition. This will allow the Spryte rendering engine to pause cleanly and allow the CPU to notice the interrupt.
  • the CPU can reset the PAUSE flipflop by writing to 'SPRCNTU'. If the Spryte engine was on but paused it will now continue. If not, it won't. This is also when the CPU might avail itself of the SPRPAUS function.
  • the CPU could just issue the SPRCNTU. If there are no Sprytes left, the Spryte engine will turn itself off and no harm done.
  • SCoB data structure (Table 1.0) includes a PPMP control word (PPMPC) . This 32 bit control word is routed out of memory 120 and split into two halves.
  • PMPC PPMP control word
  • Fig. IB shows the two PPMC halves of SCoB 126 as signals PPMPCa and PPMPCb. These are conveyed as indicated by data-transfer line 117 and loaded into respective first and second PPMP control registers, CRA and CRB (131 and 132 respectively) .
  • a PPMP control multiplexer (CMUX) 133 selects one of the PPMPa and PPMPCb half-words that have been prestored in registers 131 and 132 and forwards the selected PPMPC half-word to the Pen and Palette Manipulation Processor (PPMP) 200.
  • CMUX PPMP control multiplexer
  • the FLAGS word within the SCoB data structure includes a D-mode override field (DOVER) .
  • DOVER D-mode override field
  • This 2 bit-wide control field is also shown in Fig. IB as being routed out of memory 120 by way of data-transfer line 117 for storage in an external register (not shown) and application to the select control of a 4-input multiplexer (DMUX) 134.
  • the output of DMUX 134 drives the select control of the PPMP control multiplexer, CMUX 133.
  • a dynamic select-control bit (D-bit) which develops on a soon-to-be described Source-A bus couples to a first input of DMUX 134 and passes through DMUX 134 to control CMUX 133 when DOVER 00.
  • D-mode This condition is referred to as D-mode.
  • the D-bit of the SRC-A bus dynamically selects one or the other of the A and B inputs of CMUX 133 to be the output of that multiplexer 133.
  • the data which arrives at the SRC-A input side of the PMPP unit 200 can dynamically alternate the PMPP control word that is then used to control operations within the PMPP unit 200.
  • DMUX 134 In addition to the D-bit, two other inputs of DMUX 134 respectively receive a logic zero ("0") and a logic one ("1") .
  • the color-mapping section of IPAD system 100 is referred to here as a color-engine 170 (shown beginning near the top of Fig. IA) .
  • the color-engine 170 has a pipelined architecture.
  • One or more source color- defining signals e.g. , those carried by data-transfer lines 111, 112 and 113 in Fig. IA
  • the source color-defining signals are transformed as they flow
  • the PPMP unit 200 (Fig. IB) defines a midstream part of the overall pipelined architecture of color-engine 170.
  • source pixel color and/or shade and/or intensity information is stored in a compressed format within this region 121 in order to minimize the amount of storage area consumed by region 121. This helps to minimize the size and cost of VRAM 120. It also reduces the amount of time needed to. transfer 111 such data out of VRAM 120 over D-bus 120d and into a first upstream unit 102 of color-engine 170.
  • the first upstream unit, unpacking unit 102 includes a front-end capture FIFO 102a which captures the transferred data off the D-bus 120d, stores it and shifts it downstream for subsequent decompression by an internal decompression sequencer (not shown) of unit 102.
  • a run-length (RL) compression scheme is utilized for encoding the data held in nonliteral storage region 121. If a particular scan line of the video display 160 is to include a horizontal sequence of, for example, two pixels having a particular red shade (R) , three following pixels having a particular green shade (G) , five subsequent pixels having a particular mixed color shade (M) , and 100 further pixels containing a particular blue shade (B) , with the first red shade (R) pixel being positioned seven places to the right of a reference point (e.g., 127), then compressed code is programmed into region 121 specifying each shade (R, G, M) or transparency (T) in conjunction with a repeat value specifying the number of sequential pixels that are to be colored with that shade or treated as a transparency (e.g.
  • the routing (101a) is controlled by one of the plural geometry-control engines 101c inside the memory address manipulator chip (MAMC) 101.
  • the geometry- control engines 101c determine which locations of VRAM 120 will be accessed one after the next and when each specific location is to be accessed.
  • the implied source-A router 101a is conceptually shown to be fetching packed data (e.g., 7T,2R,3G,5M,100B,EOL) from region 121 as indicated by data-transfer line 111.
  • Unpacking unit 102 converts the stream of non- literal image information (e.g.
  • 2R 3G 5M 100B that it receives, from a compressed format in which one —and usually more— pixels are defined by each 32-bit word delivered over D-bus 12Od, into a somewhat less compressed stream of color/shade definitions.
  • These decompressed color/shade definitions are represented by a stream of signals that move out of the unpacking unit 102 over a plurality of system clock ticks.
  • the decompressed color/shade defining signals are referred to here as PIN's (PEN Index Numbers) .
  • Each PIN signal represents a particular color and/or shading that is to be "initially" assigned to a corresponding pixel of a destination image area. (The assignment is provisional and subject to many possible
  • SUBSTITUTE H changes as the signal moves downstream through color- engine 170 and as corresponding geometry-defining signals (not shown) move downstream in parallel through the geometry-control engines 101c.)
  • the "2R" non-literal code is now decompressed into a serial sequence of two separate “R” shade specifications.
  • the "J3G” non-literal code is now decompressed into three separate “G” shade specifications, and so forth.
  • the bit- widths of the individual decompressed shade specifications of each given spryte can be set according to a number of different Bits Per source Pixel (BPP) definitions.
  • BPP Bits Per source Pixel
  • the IPAD system 100 of Fig.s IA, IB allows a BPP of anywhere from one to sixteen bits per source pixel.
  • the decompressed R code for example, might be 4 bits wide when derived form one spryte and 6 bits wide when derived from a different source spryte.
  • the allowed PIN bit widths of one embodiment of the invention include: 1, 2, 4, 6, 8 and 16 bits per pixel.
  • the decompressed PIN signals are next supplied to a Indexed PIN Selecting unit (IPS) 103.
  • the IPS unit 103 can also convert received codes so that two input codes that initially represent two different colors are converted into an output code that represents a same color.
  • palette mapping is undone back to one where the outputs are again different, image areas that displayed as having the same color suddenly take on different colors.
  • the mapping function also makes it possible to convert any given color or shade code into a transparency code, so that an image area that is to be solidly colored can first be displayed as transparent. (This effect is useful for example, to show mud splattered onto a windshield. The splattered areas are first transparent and then they are suddenly mud colored.)
  • PIN Index Palette unit (PIP) 104 is included within IPS unit 103 for performing this palette mapping function.
  • the PIP 104 is a 32-word deep, 16-bit wide register stack which receives up to five of its address bits from the PIN's and if the PIN is less than five bits long, further address bits are derived from a preselected SCoB (e.g. 125) within the VRAM 120.
  • SCoB e.g. 125
  • the PIP 104 For each received PIN code, the PIP 104 outputs a 29-bit wide pixel shading code which is referred to as an IPN (Initial PEN Number) .
  • IPN Initial PEN Number
  • the "initial" portion of the IPN acronym once again indicates here that each pixel shading value is subject to further change as it flows further downstream into a subsequent FIFO (first-in, first-out buffer) 105a and then through the Pen and Palette Manipulation Processor (PPMP) 200.
  • FIFO first-in, first-out buffer
  • PPMP Pen and Palette Manipulation Processor
  • SUBSTITUT first-out buffer 105a is also referred to as the A-FIFO 105a because its output is connected to a Source-A bus that supplies data to the PPMP 200.
  • the structure of an individual IPN code is shown at 155. Its 29-bit width is divided out into a plurality of fields having respective widths of 1, 5, 5, 5, 1, 3, 3, 3, 1, 2 bits.
  • the most-significant one of the illustrated bits contains the earlier-mentioned D-bit.
  • the next five bits (B27:23) contain a code representing an initial red gun intensity (R j ) .
  • the next five bits (B22:18) contain a code representing an initial green gun intensity (G j ) .
  • the next five bits (B17:13) represent an initial blue gun intensity (B j ) .
  • the next bit (B12) of the IPN code word 155 defines the earlier-mentioned transparency code. It is referred to as the T-bit.
  • the T-bit is stripped out of the data output flow of IPS unit 103 and diverted to the geometry- control engines 101c.
  • T-bit When the T-bit is set to logic one (“1") , it instructs the memory address manipulator chip (MAMC) 101 to NOT overwrite a color code in a corresponding pixel of the destination grid with a new color.
  • the original code in the destination area e.g., 123b
  • T-bit When T-bit is set false (to "0") it allows the MAMC 101 to proceed with writing to memory. Other mechanisms however may block the write operation for other reasons (e.g. , the write is outside an allowed boundary) .
  • Bits Bll:9 of the IPN data structure 155 define a 3- bit wide alternate multiplier (MULR) that is used by an R-pipe section 201 of the PPMP 200.
  • Bits B8:6 define a 3-bit wide alternate multiplier (MULG) that is used by a G-pipe section 202 of the PPMP 200.
  • Bits B5:3 define an alternate multiplier (MULg) that is used by a B-pipe section 203 of the PPMP 200.
  • Bit B2 defines an R-mode (R/W) signal which, when active, tells the DMA hardware that a special "read" operation is to be performed within a stream of memory write operations.
  • the special read operation initiated by the active R/W signal invokes the loading of a color code from a totally literal frame buffer region (such as 123a or more preferably the cFB, 123b) into a 16-bit wide FIFO-B 105b of the color-engine 170.
  • the signal which sent the active R/W signal wraps back from the downstream end of FIFO-A 105a, through a "DOLO" register 106 (which provides a 1 clock tick delay) into an upstream end of IPS unit 103.
  • the wrapped-back signal then returns through IPS unit 103 to an upstream end of FIFO-A 105a.
  • the wrap-back delay is adjusted so that the returned, R-mode invoking signal enters FIFO-A 105a roughly at the same time that the other color signal, that had been fetched from memory because the R/W bit was active in the first signal, enters FIFO-B 105b.
  • the two signals then exit in synchronism from the respective downstream ends of FIFO-A 105a and FIFO-B 105b for processing within PPMP unit 200.
  • the last two bits (B1:0) of the illustrated IPN data structure 155 are respective vertical and horizontal subposition bits which are used by the CLUT/INT unit 140 to perform a pre-display interpolation process.
  • bit positions (B28:0) have been recited above for the IPN data structure 155, it is to be understood that the bit positions can be varied as desired.
  • the basic idea is to show that 18 bits define functional portions D, R j , G j B j and SP, in the 29-bit wide IPN data structure 155, and that a next-described
  • SUBSTIT data structure 156 has a roughly similar 16 bit organization that includes corresponding functional portions: SP V , R Q , G Q B Q and SP H .
  • the IPN data structure 155 is 29-bits wide, the transparency-indicating bit (T-bit) is stripped off and sent to the geometry-control engines 101c before the remainder of the IPN bits enter FIFO-A 105a.
  • FIFO-A 105a is therefor only 28-bits wide.
  • the R-mode (R/W) bit is stripped off and wrapped back to DOLO register 106 and MAMC 101.
  • the IPN signal portion which thereafter enters PPMP unit 200 (Fig. IB) is thus only 27-bits wide.
  • tPEN's totally-literal PEN's
  • MAMC memory address manipulator chip
  • R-mode is not necessarily the only way of loading B- FIFO 105b.
  • Implied source-B router 101b is shown to indicate conceptually that tPEN data can come from any desired region of VRAM 120.
  • the tPEN data entering FIFO-B 105b should have functional portions: SP V , R 0 , G 0 B Q and SP H , arranged as shown at 156 with respective bit-widths 1, 5, 5, 5or4, Oorl.
  • first-in/first-out buffers 105a and 105b are synchronized to the system clock (CLK) and respective signals that move simultaneously out of FIFO-A 105a and FIFO-B 105b thereafter march side-by- side, in a timing sense, through pipelined sections of the subsequent PPMP unit 200.
  • Upstream signals which enter the input sides of respective FIFO's 105a and 105b do not have to be time-aligned to one another. It is the order in which they accumulate at the downstream ends of respective FIFO's 105a and 105b that determines what FIFO-A output signal will march together with what FIFO-B output signal through PPMP unit 200.
  • a vertical subposition bit SP V occupies the most- significant bit position (B15) of the 16 tPEN code bits.
  • a red-shading part (R 0 ) consumes the next 5 of the 16 tPEN code bits.
  • a green-shading part (G Q ) consumes another 5 of the tPEN code bits.
  • a blue-shading part (B Q ) consumes either 4 or 5 of the tPEN code bits depending on whether a following, horizontal subposition part (SP H ) of the tPEN code 156 that, depending on mode, consumes either 1 or 0 bits.
  • the downstream CLUT/INT unit 140 can operate in either a mode which requires 2 SP bits to be varying on a pixel-by-pixel basis or a mode which needs only one SP bit changing on a pixel-by-pixel basis. If the 2 SP bits mode is chosen, the SP H portion of tPEN signal 156 is 1-bit wide rather than zero bits wide, and the 4-bit B Q portion of tPEN data structure 156 is padded further downstream, as it enters PPMP unit 200, with a least- significant logic zero ("0") to make the blue field (B Q ) the same bit-width as the R Q and G Q fields. If the 1-SP bit mode is chosen, the B Q field is a full 5-bits wide and the SP H bit is not present in the tPEN data structure 156.
  • Each tPEN signal 156 preferably starts its life as a totally-literal PEN code stored in a totally-literal region (e.g. 123a or 123b) of VRAM 120.
  • the format can be TLFB or TLNF.
  • the implied source-B router 101b fetches tPEN's from a box-shaped area (e.g., XI, or X2 or X3) of the literal-image defining regions (e.g., 123a, 123b) in accordance with commands issued by the memory address manipulator chip (MAMC) 101.
  • Control signals e.g., XI, or X2 or X3
  • SUBS IT sent from the memory address manipulator chip (MAMC) 101 determine the source address.
  • the source address can be anywhere in VRAM 120. Regardless of the source region, the output of FIFO-B 105b is referred to as the secondary or "Source-B" input signal of PPMP unit 200 and the output of FIFO-A 105a is referred to as the primary or "Source-A" input signal of PPMP unit 200.
  • Nonliteral image region 121 is not well suited because its image codes are compressed. Image data from nonliteral image region 121 is preferably routed into the Source-A side of PPMP unit 200 by way of unpacking unit 102. (The unpacking unit 102, incidentally, can receive literal data by setting its BPP value to 16 bits per pixel.)
  • An example of a more-suited source area for the input of FIFO-B 105b is a box-shaped spryte (e.g. XI) within totally-literal region 123a, as indicated by data- transfer line 113.
  • Another example of a more suited source area is box-shaped spryte X3 within region 123b, as indicated by data-transfer line 114.
  • box-shaped spryte X3 within region 123b serves as tPEN signal source and region 123b also serves as the destination area into which color-output codes (oPEN's) of PPMP unit 200 are to be written, a recursive condition can be established in which the output of one operation of PPMP unit 200 becomes the Source-B input for a subsequent operation of the PPMP unit 200.
  • oPEN's color-output codes
  • the IPN (Source-A) and tPEN (Source-B) code signals are simultaneously output from their respective A- and B-FIFO's (105a and 105b) at a system clock rate of for example, 25 MHz, and placed onto respective Source-A and Source-B input buses of the PPMP unit 200.
  • the memory address manipulator chip (MAMC) 101 determines which IPN code signal will be output concurrently with each tPEN code signal.
  • the two subposition bits, SP, of IPN data structure 155 and/or the one or two subposition bits, SP V and/or SP H , of tPEN data structure 156 are not altered by PPMP unit 200, but just the same, two pre-selected ones of these bits step through an ancillary pipeline section 204 of the PPMP 200 so that they remain in synchronized step with the corresponding color code signals that step through pipelined sections 201 (R) , 202 (G) and 203 (B) of PPMP unit 200.
  • one or two SP bits output by ancillary pipeline section 204 merge further downstream into a 16-bit wide oPEN signal that is output by the PPMP unit 200 and stored (116 or 115) back into memory 120.
  • the stored one or two SP bits are later retrieved by the CLUT/INT unit 140 and used to form the ultimately displayed image on video display unit 160.
  • S B and B output groups are produced by the respective R, G, and B pipe sections, 201, 202 and 203 of PPMP 200.
  • the PPMP produced oPEN signals are next routed by a subsequent, "corner-selecting" demultiplexer 108 into one of a plurality of 16-bit wide, oPEN-codes storing registers 109.
  • the corner-selecting demultiplexer 108 and the set of codes storing registers 109 function as a means of determining specifically where in a designated destination region (e.g., 123b) of VRAM 120, the produced oPEN codes will be stored.
  • the details of this output routing mechanism are not germane to understanding the functions of PPMP unit 200.
  • the implied destination router lOld preferably routes and writes the oPEN codes to a preselected, totally-literal (TLFB) destination area (e.g. 123a or 123b) within the VRAM 120.
  • TLFB totally-literal
  • Control signals sent from the geometry-control engines 101c determine whether and which specific destination pixel or pixels will be "over- painted” with the color represented by each produced oPEN signal.
  • One possible destination for the oPEN write operations is the earlier-mentioned, nonbox-shaped region RY3 within region 123b, as indicated by data-transfer line 116.
  • Another possible destination for the written back oPEN codes is region RY2 (Fig. IA) within totally- literal region 123a, as indicated by data-transfer line 115.
  • any appropriately-sized region of VRAM 120 can serve as one or the other or both of the Source-A and Source-B data-supplying regions.
  • a same or other region can serve as the destination area into which the PPMP produced oPEN signals are written. Note that a recursive form of spryte rendition is made possible by setting the destination area of the PPMP output codes to be the same as one or both the source areas (Source-A or Source-B) that supply input data to the PPMP unit 200.
  • implied source-B router 101b would follow data-transfer line 114 to fetch tPEN codes from box-shaped region X3 while the implied destination router lOld would follow data-transfer line 116 to overwrite oPEN codes into part or all of the same box-shaped region X3.
  • the over-write or "paint-over" region can be uniquely shaped as indicated by the non- rectangular, rendered area, RY3.
  • Multiple, cascaded effects such as shadowing and highlighting can then be applied to a single spryte-rendered region (e.g. RY3) .
  • the PPMP unit 200 comprises three pipelined sections, 201, 202 and 203. These are also referred to hereafter respectively as the R-pipe unit, the G-pipe unit and the B-pipe unit. Each of pipe units 201, 202 and 203 has a similar two-stage internal structure. One exception is the R-pipe unit 201 which includes a black-converter unit 295 (Fig. 2B) not found in the G-pipe and B-pipe units.
  • Pipelining techniques are used, but not necessary, for the operations of PPMP unit 200 to compensate for delays found in present-day silicon technology. Two ticks of the system clock (25MHz) have been found to be required when using 0.9 micron CMOS technology for converting an IPN and/or tPEN input signal into a corresponding oPEN output signal. (Faster technologies such as ECL may be used, if desired, to do the same logical operation in one clock cycle.)
  • the upstream end of the R-pipe unit 201 receives the 5 R j bits of each IPN signal from the Source-A bus and
  • R-pipe unit 201 SUBSTITUTE the 5 R 0 bits of each tPEN signal from the Source-B bus.
  • the upstream end of the R-pipe unit 201 also receives the 3 MULp-defining bits of each IPN signal from the Source-A bus.
  • G-pipe 202 similarly receives the 5 G Q bits of each tPEN signal, the 5 G j bits of each IPN signal, and the 3 MULg-defining bits of each IPN signal.
  • B-pipe 203 correspondingly receives the 5 B Q bits of each tPEN signal, the 5 B j bits of each IPN signal, and the 3 MUL ⁇ -defining bits of each IPN signal. All three pipes 201-203 receive the PPMP control word (16 bits) output by CMUX 133.
  • Each of the R, G and B pipes (201, 202, 203) outputs a corresponding 5 bits for use in the resultant oPEN code signal.
  • the data structure shown at 156 (Fig. IA) is used.
  • the least significant bit of the B-field in the oPEN code is selected, depending on mode, either as the output of the B-pipe unit 203 or another code derived from the B0POS field of the spryte-rendering engine control word. (See above Table 1.4.)
  • the most significant bit B15 of the oPEN code is set in accordance with the B15POS field of the spryte-rendering engine control word. (See above Table 1.4.)
  • the three-section structure (201, 202, 203) of PPMP 200 is provided as a matter of convenience for image manipulations operating in a three color-vector space (e.g. R,G,B) rather than as a necessity.
  • a three color-vector space e.g. R,G,B
  • manipulations in a two color-vector space e.g., YCC
  • a two-section structure (201, 202) for PPMP 200 will suffice.
  • image data is supplied serially rather than as parallel vectors; as is done for example in the Composite Video Broadcast Standard (CVBS)
  • a one-section structure (201) for PPMP 200 will suffice for processing the image data.
  • Pipes 202 and 203 have similar structure with the exception that R-related connections are replaced with corresponding G-related and B-related connections and the G and B-pipe units do not include black-detector (NOR gate) 296 and black-converter unit 295 (Fig. 2B) .
  • NOR gate black-detector
  • Fig. 2B black-converter unit
  • the R-pipe unit 201 can be visualized as receiving a plurality of control signals at its side (e.g., SI, MXF, MS, etc., which are discussed later) and three input signals at its top.
  • the three top signals are shown in left to right order as: a 16-bit wide portion 207 of the IPN signal; a 16-bit wide tPEN signal portion whose structure is shown at 208; and a 5- bit wide AV signal whose structure is shown at 209.
  • IPN signal portion 207 is output from the A-FIFO 105a (Fig. IA) at the same time that tPEN signal portion 208 is output from the B-FIFO 105b.
  • the 5-bit wide AV signal 209 comes from CMUX 133 (Fig. IB) and is part of the 16-bit wide PPMPC control signal output by CMUX 133. (See above Tables 1.2 and 1.3.)
  • the 5 R- j - bits of IPN signal portion 207 are placed on a corresponding 5-bit wide SRC-A bus portion of R- pipe 201.
  • the 5 R Q bits of tPEN signal portion 208 are
  • R-pipe unit 201 is comprised of a primary input selector (multiplexer) 211, a secondary input selector (multiplexer) 212, and a third input selector (multiplexer) 213 for receiving the respective input signals of busses SRC-A, SRC-B and SRC-C and routing them in accordance with a supplied set of select control signals, SI, S2 and USEAV.
  • the R-pipe unit 201 further includes a multiply- factor selector (multiplexer) 222, a multiplier 225, a left-side divider 231, and a right-side divider 233, for performing pre-addition scaling.
  • the R-pipe unit 201 also includes a set of five exclusive OR gates (represented by one XOR symbol) 240 and ancillary logic 241-246 for performing pre-addition negation or other processing as will be detailed shortly.
  • a group of pipeline registers 250-255 synchronize the signals entering the second pipeline stage of R-pipe unit 201 with a system clock signal (CLK) before supplying them to a subsequent adding unit 260, third divider 270 and wrap-limiting unit 280.
  • the third divider 270 is provided for performing post-addition scaling.
  • the wrap limiter 280 is provided further downstream for selectively allowing or preventing magnitude wrap-around to occur (out of decimal range 0- 31) in the signal output by the adding unit 260.
  • Register 290 is shown to indicate the timing point at which the output PPMP unit 200 is resynchronized to the next tick of the 25MHz system clock.
  • the primary input selector 211 supplies one or the other of the corresponding 5 R j bits from the SRC-A bus or 5 R Q bits from the SRC-B bus to a first, 5-bit wide input port of digital multiplier 225.
  • a second input port of digital multiplier 225 is 3-bits wide and receives a digital multiplying value (MV) from multiply-factor selector 222.
  • the MV signal represents a multiplying factor in the integer range, one to eight (xl:x8) .
  • multiplier 225 produces a 7-bit wide digital signal representing the 8-bit product of MV and the output of first selector 211, with the least significant bit always forced to zero. (Note that no wire is necessary for the least significant bit because the next stage, left-side divider 231, automatically truncates it.)
  • Multiplier 225 is formed of combinatorial logic circuitry which completes the multiplication in less than one tick of the system clock.
  • Fig.s 2A and 2B show divided-arrow symbols surrounding and approaching the input nodes of respective signals: SI, MxF, MS, DV1, DV2 (Fig. 2B) , S2 (Fig. 2A) and AV.
  • the divided-arrow symbols indicate that the output of CMUX 133 (Fig. IB) is the source of these symbol-surrounded signals.
  • the 16-bit wide output of CMUX 133 is broken out as follows: SI (1-bit wide), MxF (3-bits wide) , MS (2-bits wide) , Dvl (2-bits wide) , S2 (2-bits wide), AV (also called the SRC-C signal, 5-bits wide) , and Dv2 (1-bit wide) .
  • the Rj signal are referred to here as the IPNM signal because they originate from the IPN signal. (Although not shown, in an alternate embodiment the remaining 2-LSB's (least-significant bits) of the R- j - signal are used to select a divide factor used by right-side divider 233.)
  • MUL j -. field of the IPN code signal 155 (MUL j ⁇ is labeled as M R in Fig. IA) is delivered to the B input port of selector 222.
  • the output 226 of multiplier 225 is shifted right by one, two, three or four bit positions in divider 231 in accordance with a 2-bit wide left-side divide command signal Dvl supplied from CMUX 133.
  • left-side pre-addition scaling subcircuit 210 (or left pre-add subcircuit 210 for short) . Its 7-bit wide output is referenced as 210o.
  • the left pre-add subcircuit 210 can perform a number of interesting image-signal processing functions.
  • the simplest processing function is selecting either SRC-A or SRC-B to be the primary image source for rendering a particular destination pixel and scaling the value of the input color code (IPN or tPEN) by a scaling factor.
  • the PPMP control word in the associated SCoB (126, Fig. IB) is configured with a multiplier selection code (MS) that selects input port C of selector 222.
  • MS multiplier selection code
  • the SCoB multiply factor (MxF) is set to a desired value in the times-1 (xl) through times-8 (x8) range.
  • the Dvl signal is preferentially set to place divider 231 in a divide by 8 mode.
  • the MxF/DvlB scaling factor is constant across all three color vectors (R, G, B) when the MS multiplexer control is set to select input port C of multiply-factor selector 222 in all three pipes (201,
  • first input selector 211 can be switched dynamically at every tick of the system clock
  • the D-bit of the IPN signal 207 is then used as the control for modulating the SI signal output by
  • the PIN's which come out every clock cycle from unpacker 102 define the D-bit of IPN signal 207 on a source pixel-by-source pixel basis.
  • One method of defining the D-bit is by appropriate programming of the PIP unit 104 (which is a look-up RAM) within IPS 103.
  • the PIP unit 104 which is a look-up RAM
  • the D-bit output from IPS unit 103 alternates every one or more machine cycles and it is used to switch the value of primary selector signal SI between logic one ("1") and logic zero ("0") .
  • the output 210o of the left-side subcircuit will then be a 50%/50% or other "dither-type blend" of the PEN codes
  • a more interesting set of effects is imparted to the output video signal when the MS signal is alternated by the D-bit to choose one of input ports A (IPNM) and B (MUI-p) in selector 222 as the multiplier value (MV) .
  • IPNM IPNM
  • B MUI-p
  • MV multiplier value
  • the corresponding IPNM and MUL fields in the IPN signal 207 can then act as source pixel-by-source pixel scaling factors for the R j field in the tPEN signal 208.
  • the MUL G and MUL ⁇ fields interact in the same way with the 3 MSB's of their respective G j and B y signals. Scaling then occurs on an independent color-vector-by-color-vector basis. (This effect is referred to as color-type openacity) .
  • the three most significant R j bits of the IPN signal 207 (the IPNM portion) will then act as the multiplying value (MV) for the five R Q bits of the tPEN signal 208.
  • the tPEN signal 208 (Source-B) can represent the image of an object behind a stained glass window, while the IPN signal 207 (Source-A) can represent the stained glass window.
  • the stained glass window is to function as a filter which attenuates the G and B content of the passed-through image while it accentuates the R content of the passed-through image, the corresponding IPN signal 207 will contain a relatively large R scaling factor and relative small G and B scaling factors.
  • Doloresizing Such cross-source manipulation (where Source-A manipulates the signal of Source-B or vice versa) is referred to here as “doloresizing”. Note that to obtain reliably repeatable doloresizing, the desired Source-A and Source-B signals need to arrive in repeatable synchronism from the outputs of respective first- in/first-out units 105a and 105b.
  • the Dolo register 106 and R-mode bit of Fig. IA are used to provide self- initiated synchronism. (An active R/W bit in an IPN signal self-initiates the fetch of a corresponding tPEN signal and the wrap-back through register 106.)
  • the left-side divide- by scaling factor Dvl can be similarly defined by the contents of the IPN signal portion 207, on a source pixel-by-source pixel basis and/or color-by-color basis (R, G, B) .
  • DOVER 00
  • the D-bit controls the CMUX 133 and thus determines whether the Dvl signal will be sourced from the CRA register 131 or CRB register 132.
  • the scaling effect is referred to as grey openacity.
  • color openacity When scaling is applied on a color-by- color basis, this is referred to as color openacity.
  • one image shading value on the Source-A or Source-B side serves as the scaling factor for a second image shading value on the other of the Source-A and Source-B sides, this is referred to as a doloresizing operation.
  • D-bit When the D-bit is used for dynamically switching the selection made by the CMUX 133 on a source pixel-by- source pixel basis, this is referred to as a D-mode operation. In D-mode operations, one or more corresponding fields in the two PPMP control half-words respectively stored in registers CRA 131 and CRB 132
  • SUB (Fig. IB) are set differently while remaining corresponding fields of the two PPMPC half-words are set to be the same.
  • the D-bit is then used to switch between those PPMPC fields that are set differently in the two half-words.
  • Right-side subcircuit 220 is comprised of secondary input selector (multiplexer) 212, third input selector (multiplexer) 213 and right-side divider 233.
  • the S2 selection signal (which is supplied by CMUX 133) is used to select one of four basic sources as the output of secondary input selector 212. These sources are: (a) the 5-bit R--. color field from the IPN signal 207; (b) the 5-bit R Q color field from the tPEN signal 208; (c) the 5-bit AV signal 209; and (d) a 5-bit wide zero signal. (More accurately, there is no "0" input port D on multiplexer 212. Instead, a select of that hypothetical port forces a default zero on the output of multiplexer 212.)
  • the D-bit may be used to switch one or both of the AV signal 209 and S2 signal on a source pixel-by-source pixel basis and on an across-the-colors basis.
  • the 5-bit wide output of secondary input selector 212 connects to right-side divider 233.
  • Right-side divider 233 receives a 2-bit wide DV3 control signal (or more precisely, bits UV4 and UV3 of the UV0:4 signal output by third input selector 213) which is also referred to as the UV4:3 signal.
  • the received UV4:3 instructs the divider to shift the output of selector 212 right by zero, one or two bit positions and thereby effect a divide by 1, 2 or 4 on the output of the secondary input selector 212.
  • the right-side addition- prescaled signal output by the right-side divider 233 is referenced as 220o. (It is the output of right-side subcircuit 220.)
  • the DV3 control signal is formed from two bits (UV3 and UV4) of a 5-bit wide UV signal output by the third input signal selector 213.
  • selector 213 uses the AV signal 209 as its output.
  • selector 213 uses a set of fixed default values (e.g., all zeroes) for UV as its output.
  • selector 213 is expanded to have three input ports and the two least significant bits (2 LSB's) of the R j signal are coupled to the third input port.
  • a decoder (not shown) which is responsive to unique code combinations present on the USEAV and SRC-C lines controls the selection of this expanded version (not shown) of selector 213 to determine when the two least significant bits of the R j signal will define the UV3 and UV4 bits.
  • the left-side and right-side prescaled signals, 210o and 22Oo can be merged in a number of ways including, adding them together, subtracting one from the other and developing an exclusive OR of parts of the two signals.
  • each of AND gates 241 is connected to a respective one of the seven output lines of divider 231 (signal 220o) .
  • the inverting inputs of all seven AND gates 241 are connected to receive an exclusive-OR permission signal, PXOR from the
  • a first noninverting input of each of AND gates 242 is connected to a respective one of the five least-significant output lines (5 LSB's) of divider 231. (The remaining 2 MSB's are not connected to AND gates 242.)
  • AND gates 242 output zero signals to the five OR gates 243.
  • XOR exclusive OR gates
  • Respective second inputs of the five XOR gates 240 are coupled to the respective five output lines of divider 233 (signal 220o) .
  • a UV0 signal supplied from multiplexer 213 forces the outputs of all five OR gates 243 to logic high ("1") when UV0 goes high.
  • XOR gates 240 output the l's complement (the binary inversion) of the 5-bit wide, right-side signal 22Oo to a 5-bit wide pipeline register 252.
  • the UV0 signal which is also referred to as the "negate” signal can be optionally used to form a 7-bit wide, 2's complement of the 5-bit value output by right- side divider 233.
  • the UVO (negate) signal connects by way of a 1-bit wide pipeline register 254 to the carry- in input of adding unit 260.
  • XOR gates 240 invert the 5 bits of the right-side prescaled signal 220o and the high carry-in signal increments the result.
  • UV1 serves as a sign-extend enabling signal which is applied to a first noninverting input of AND gate 245.
  • the most significant bit (MSB) output by XOR gates 240 connects to a second noninverting input of AND gate 245.
  • the output of AND gate 245 drives one input of OR gate 246.
  • the output of OR gate 246 connects to a 1-bit wide pipeline register 253.
  • the one-bit output of register 253 simultaneously drives the two MSB input lines of port-B of adder 260 to thereby define the two most significant bits of a 7-bit wide input (B) of adding unit 260.
  • UV1 XTEND enable
  • MSB output of XOR gates 240 When UV1 (XTEND enable) is high and the MSB output of XOR gates 240 is high, the two most significant bits of adder input-B are also driven high. If the MSB output of XOR gates 240 is low, the two most significant bits of adder input-B are also driven low.
  • Adder 260 is thereby supplied with a 7-bit wide signed value at its input port-B even though pipeline register 252 and preceding units 240, 233, 212 and their interconnect busses are only 5-bits wide.
  • UV1 connects to an inverting input of another AND gate 244 while UVO connects to a noninverting input of the same AND gate 244.
  • AND gate 244 drives an input of
  • the output of XOR gates 240 can be switched on a source pixel-by-source pixel basis between two of four possible combinations by setting different values for UVO and UV1 in CRA 131 and CRB 132.
  • the left-side signal 210o starts as the 7-bit value
  • 0100000 and the right-side signal 220o starts as the
  • UV1 is switched from logic zero ("0") to logic one (“1") .
  • Adder output 265 0000001
  • the contents of register 251 represents a decimal value of +32.
  • the combined contents of registers 252-254 represent a decimal value of -31.
  • Adder 260 therefore produces a 7-bit wide output signal 265 representing a decimal value of +1.
  • UVO Negate
  • UV1 (Xtend) is true (equal to logic one)
  • the contents of register 251 represents a decimal value of +32.
  • the combined contents of registers 252-254 now represent a decimal value of +1.
  • Adder 260 therefore produces a 7-bit wide output signal 265 representing a decimal value of +33.
  • two further pipeline registers, 250 and 255 are provided for respectively receiving a post-addition scaling signal Dv2 from CMUx 133 and a clip-disable signal UV2 from selector 213.
  • Pipeline registers 250- 255 capture their respectively received signals just before a first system clock cycle comes to an end and output the captured signals at the beginning of a subsequent second system clock cycle in synchronism with clock signal CLK.
  • the positioning of the pipeline registers 250-255 is dependent on the speed of the preceding logic circuits, as should be well known in the art. If faster logic is used, it may be possible to move the clock resynchronization point further down Fig. 2B, to a position below adding unit 260 for example.
  • Adder 260 generates an 8-bit wide output signal 265 representing the sum of the two 7-bit wide signals presented respectively at its A and B input ports.
  • the most significant bit (MSB) of adder output signal 265 sets high.
  • the MSB of adder output signal 265 connects to a noninverting first input of AND gate 285 (also referred to as clip-logic unit 285) to indicate to that logic unit 285 that the output of adder 260 has exceeded the 7-bit boundary.
  • An inverting second input of AND gate 285 connects to the output of register 253. In the case where the output of register 253 is logic zero ("0") and the MSB of adder output signal 265 is logic one ("1") , AND gate 285 outputs a true CLIP+/- signal.
  • AND gate 285 outputs a false (“0") CLIP+/- signal.
  • the 8-bit wide adder output signal 265 is supplied to a post-addition scaling unit (right shifter) 270.
  • Shifter 270 performs either no shift or a 1-bit position right shift in accordance with a Dv2' signal supplied to it from CMUX 133 by way of pipeline register 250.
  • Adder output signal 265 is thereby divided either by a one or a two.
  • the 8-bit output 275 of divider 270 is next supplied to an intensity wrap-around limiting unit 280.
  • Wrap- limiting unit 280 has a 5-bit wide output port 287. If Clip-disable (UV2) is true, the wrap-limiting unit 280 simply passes the five least-significant (5 LSB's) of 8- bit signal 275 to its output port 287.
  • the wrap-limiting unit 280 tests the divider output signal 275 for a greater than +31 condition. If the 8-bit wide divider output signal 275 represents a value greater than 31, the 5-bit wide binary output 287 of wrap-limiting unit 280 is set to represent +31, otherwise the five least-significant (5 LSB's) of 8-bit signal 275 are passed through to its output port 287.
  • the 5-bit wide output signal, (oPEN R ) of register 290 next enters a black-converter unit 295. (This happens only in the R-pipe unit 201, not in the G-pipe unit 202 or B-pipe unit 203.)
  • a user-defined background color which could also be, but is not necessarily all zeroes.
  • the 5-bit wide oPENR' output of black-converter unit 295 serves as the R color field of the 16-bit wide oPEN signal.
  • the respective 5-bit color field oPENG is output from the G-pipe register (not shown) corresponding to register 290.
  • the least significant bit of the oPEN B field is truncated off if the 2-SP bits mode is active.
  • the B-pipe unit 203 is selected as the place where B value precision is sacrificed because it was found that the human eye is least sensitive to variances
  • the 15 R ⁇ G ⁇ B ⁇ -bits of the IPN code signal pass through the PPMP unmodified in the Basic mode.
  • BBP PIN source data type
  • the 3 MSB's of an 8-bit PIN code are transferred out of the IPS as a single MUL multiplier (grey openacity) to be applied against the 15-bit RJGTB field of the IPN code output from the PIP (SRC-A).
  • 8-bit PIN source serve as address inputs to the PIP.
  • An 8-bit wide PIN code therefore translates into 8 intensity levels of 32 independent colors.
  • the PPMP control bits are set to:
  • the D-bit sourced from a 6-bit wide PIN signal selects one of two common multipliers to be applied across the 15-bit R G B field of an IPN signal (SRC-A).
  • the remaining 5 LSBs of the 6-bit PIN signal serve as address inputs to the PIP.
  • a 6-bit wide PIN signal therefore translates into two intensity levels of 32 independent colors.
  • the PPMPCb control bits are set to:
  • the D-bit sourced from a 6-bit wide PIN signal modulates the S2 value between the A and D inputs of selector 212, thereby selecting the second adder input to be either zero or the IPN signal.
  • the remaining 5 LSBs of the 6-bit PIN source serve as address inputs to the PIP. This doubles the range of 32 independent but appropriately selected colors.
  • the PPMPCa bits are set to:
  • a 9-bit wide field (B13:5) of a 16-bit type PIN is used to form three sets of 3- bit wide individual multipliers (MULR, MULQ, MULg) which are respectively applied to the three RQGQBQ field components of a 15-bit wide tPEN signal sourced from the cFBD.
  • the 5 LSBs (B4:0) of the 16-bit PIN source serve as address inputs to the PIP.
  • the IPN outputs from the PIP are added to the result of the multiply. Both the openacity and the coior add value are selectable on a per- pixel basis.
  • Bit B14 of the PIN is unused.
  • Bit B15 of the PIN is the D-bit.
  • the PPMPCa control bits (the first PPMPC half-word) are set as required for the doloresizing effect.
  • the PPMPCb control bits (the second PPMPC half-word) are set to:
  • the 3 MSBs of an 8-bit wide PIN code are used as the common multiplier to the 15-bit tPEN from the cFBD.
  • the remaining 5 LSBs of the 8-bit PIN source serve as the address inputs to the PIP.
  • the IPN outputs from the PIP are added to the result of the multiply. Both the filter ratio and the color add value are selectable on a pixel-by-pixel basis.
  • the PPMPCa control bits are set as required for the Doloresizing effect.
  • the PPMPCb control bits are set to:
  • Multicolor reflective glass of uniform transparency with colored scaled amount of background light added Grey openacity with Per-pixel Colored background addition:
  • the 3-bit wide MxF field from the SCoB is used as the common multiplier to the 15-bit RQGQBQ field in the tPEN signal from the cFBD.
  • the 15-bit IPN is added to the result of the multiply. This allows any size source data for the per- pixel colored add value.
  • the PPMPCa control bits are set as required for the Doloresizing effect.
  • the PPMPCb control bits are set to:
  • the 3 MxF bits from the SCoB are used as the common multiplier to the 15- bit tPEN signal (from cFBD).
  • the IPN is not used.
  • the D-bit is set to be the inversion of the transparent bit (T-bit). This allows a shadow to be created from an existing SPRYTE without the need to create a separate mask SPRYTE in VRAM 120. Memory space is then conserved.
  • the PPMPCa control bits(0) are set to (who cares, it is transparent).
  • the PPMPCb control bits are set to:
  • the 3 MxF bits from the SCoB are used as the common multiplier to the 15- bit :PEN signal (cFBD).
  • the D-mode bit is taken from the IPN, the rest of the
  • IPN is not used on the shadow. This allows a shadow to be created from a l- bit per pixel source (mask). This allows for an attached shadow.
  • the PPMPCa control bits(0) are set as required.
  • the 15-bit RGB portion of the IPN signal is added to the 15-bit RGB portion of the tPEN signal (cFBD). This allows any size of source data for the per- pixel colored add value. Requires the use of several PIP entries. To achieve this mode, the PPMPCa control bits(0) are set as required. The PPMPCb control bits are set to:
  • the 15-bit IPN is multiplied by the 3 MSBs of an 8-bit PIN source and then added to the 15-bit cFBD. This allows the use of a single PIP entry.
  • the PPMPCa control bits(0) are set as required.
  • the background and the source are added together and the result is divided by 2. This allows for interframe averaging. Any size source data can be used.
  • the PPMPCa control bits(O) are set as required.
  • the PPMPCb control bits are set to:
  • the 3 MSBs of each component (R, G, B) of the 15-bit IPN are used as the multiplier for each corresponding component (R, G, B) of the tPEN signal (cFBD). This results in a 0.125 through 1 range of multiplication values with 8 variation steps.
  • the PPMPCa control bits(0) are set as required.
  • the PPMPCb control bits are set to:
  • Multicolor Spotlight Per-pixel Color filter with cFBD adder:
  • the 3 MSBs of each component of the 15-bit IPN are used as the multiplier for each component of the tPEN signal (cFBD).
  • the original cFBD value is then added to the result of the multiply. This results in a 1.125 through 2 range of multiplication values with 8 steps.
  • the PPMPCa control bits(O) are set as required.
  • the PPMPCb control bits are set to:
  • the 3 MSBs of each component of the 15-bit IPN are used as the multiplier for each component of the tPEN (cFBD).
  • a 5-bit SCoB value (AV) is then added equally to each component at the result of the multiply. This results in a 0.125 through 1 range of multiplication values with 8 steps and a fixed offset.
  • the PPMPCa control bits(0) are set as required.
  • the PPMPCb control bits are set to:
  • the 3 MSBs of each component of the 15-bit IPN are used as the multiplier for each R, G, B-component of the tPEN signal (cFBD).
  • a 5-bit SCoB value (AV) is then added equally to each component at the result of the multiply.
  • the final results is divided by 2. This results in a 0.065- > 0.5 range of multiplication with 8 steps and a fixed offset.
  • the PPMPCa control bits are set to (as required).
  • the PPMPCb control bits are set to:
  • the disclosed hardware can be judiciously used by a programmer/artist to create a sense of realism and true- time animation in machine-generated, bit-mapped images.
  • the following is a nonexhaustive list of artistic "effects" which may be created within such images.
  • the programmer/artist uses the source data of a first spryte to create a destination rendering that looks like the shadow of the source spryte.
  • the shadow appears to be projected on top of the surface of a background image (i.e. a darkening of the background in the shape of the spryte's image.)
  • the source spryte's image data is transparent there will be no effect on the frame buffer, because the entire rendering of a pixel is terminated if it is transparent. But wherever the image data is not transparent the frame buffer data values will be divided by 2 (or whatever chosen value) before being written back to the frame buffer.
  • the background image is darkened by the shape of the source spryte.
  • Another copy of the source spryte can be rendered in an area above the shadow to create the impression that it is casting the shadow onto the background surface.
  • the shadow can be made to be fainter or deeper from one pixel to the next. This is used to create a penumbra effect, where the shadow is faint around the edge and deepens toward the center.
  • the source image of the spryte acts as a spotlight that brightens (increases the value of) the colors of the frame buffer.
  • This effect is achieved in the same way that the Shadow effect is created, except that the primary source scalar is set to augment the current frame buffer data, rather than diminish it.
  • the programmer/artist can create an effect which looks like flames are illuminating a background scene.
  • the programmer/artist creates a spryte animation that looks like fire. Also, the programmer creates an orange Spotlight spryte, perhaps one with a penumbra. With judicious placement of the orange fire Spotlight, especially if multiple rendering of the orange Spotlight are employed and distributed about the background surface, the effect is of a fire that casts an orange glow on the surrounding objects.
  • the programmer/artist uses the per-pixel D-Mode selection that comes out of the IPS.
  • the PPMP is set to select the current frame buffer data as the primary source and the spryte image data as the secondary source.
  • the current frame buffer data values are diminished by a fixed amount (diminish it by half for stained glass, diminish it by one eighth for a wind ⁇ shield) and then add the per-pixel color value coming from the IPS (various colors and saturations for stained glass, dark green fading to black for the windshield) .
  • the Doloresizing mode is applied repeatedly when rendering partial cloud images, resulting in clouds that are soft-edged and have a gray density and translucency that is variable - in a word, realistic.
  • An added advantage of this type of spryte is that it can be stored in a memory area requiring a low number of bits per pixel. Rather than have a small number of very detailed clouds it's preferable to have a larger number of moderately detailed clouds. The result is less storage required and better looking clouds. Although the description of this technique refers to clouds, the effect can be used for any imagery where partial; and shifting, if appropriate, opacity is desired.
  • This effect modifies an image in a way that makes it look as if the image is on a surface that is rippling, or is beneath a rippling clear material (e.g. water) that causes refraction of the image.
  • a rippling clear material e.g. water
  • the spryte engine's ability to render from any buffer to another is employed.
  • Several renderings are done to the offscreen alternate frame buffer, of stages of the rise, crest and fall of the ripple, each stage with an appropriate distortion and pixel offset.
  • the result of each offscreen rendering is then transferred to the current frame buffer, using the spryte engine a second time. With careful modeling of physics and a fine enough ripple resolution, the effect is compelling.
  • the artist can arrange pixels that form a Doloresizing border around the outside of a spryte image. This makes for softer spryte imagery that blends softly into the frame buffer.
  • the programmer/artist gets a wide range of control over the color and brightness of the image's pixels.
  • the programmer keeps a copy of the spryte's original PIP.
  • a new PIP is created starting from the original.
  • the spryte is set to use the modified PIP, not the original.
  • This technique allows a scalar to be applied to each RGB component separately. However, if the scalar is the same across all three RGB components the effect is of a modification of illumination rather than color.
  • 3D effects By using the rectilinear image distortion capabilities of the spryte system's geometry engines in a uniform way, a way that's tied to a database that defines a 3-dimensional universe, it's very easy to create 3-dimensional bitmapped renderings of scenes.
  • the four corners of the spryte image map to the x and y coordinates of four points in the 3-dimensional universe. This allows a programmer to create the illusion of bitmap images being projected onto 3-dimensional surfaces.
  • an image can be made to project onto the walls, floors, and objects of a scene.
  • One usage of the independent setting of subposition bits is to create a font that's balanced at a subpixel level. This can be used to create smooth imagery even though the initial imagery is more jagged.
  • the PPMP design can be modified as mentioned earlier so that selector 213 supplies a signal derived from part of the IPN signal 207 or tPEN signal 208 to define the Dv3 divide factor used by divider 233.
  • Right-side pre-scaling unit 233 can be expanded to provide, in addition to the three scaling factors, 1/1, 1/2 and 1/4, a fourth scaling factor (e.g.
  • input port D of selector 212 can be coupled to receive, instead of zero, a different control signal.
  • source- image data can reside in addressable parts of system memory other than VRAM 120.
  • System memory can include a slower SRAM section, DRAM, RAMBUSTM and so forth.

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  • Image Processing (AREA)

Abstract

Procédé et appareil pour le traitement de données d'image, permettant de produire des effets améliorant le réalisme des images, tels que des ombrages, la mise en surbrillance, le filtrage de couleurs, le rendu des réflexions en couleurs, etc. L'appareil de traitement d'images ci-décrit comprend trois unités de traitement indépendantes pour le traitement des composantes rouge (201), vert (202) et bleu (203) d'un ensemble de signaux définissant l'image. L'appareil permet soit une mise à l'échelle d'intensité homogène pour toutes les trois couleurs soit une mise à l'échelle d'intensité effectuée couleur par couleur. Les effets peuvent être modifiés en temps réel pixel par pixel, et on peut également utiliser un signal pour commander l'effet appliqué à un deuxième signal.
PCT/US1992/009461 1992-11-02 1992-11-02 Procede et appareil ameliores pour le traitement de donnees d'image Ceased WO1994010643A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU30638/92A AU3063892A (en) 1992-11-02 1992-11-02 Improved method and apparatus for processing image data
PCT/US1992/009461 WO1994010643A1 (fr) 1992-11-02 1992-11-02 Procede et appareil ameliores pour le traitement de donnees d'image

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1992/009461 WO1994010643A1 (fr) 1992-11-02 1992-11-02 Procede et appareil ameliores pour le traitement de donnees d'image

Publications (1)

Publication Number Publication Date
WO1994010643A1 true WO1994010643A1 (fr) 1994-05-11

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PCT/US1992/009461 Ceased WO1994010643A1 (fr) 1992-11-02 1992-11-02 Procede et appareil ameliores pour le traitement de donnees d'image

Country Status (2)

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AU (1) AU3063892A (fr)
WO (1) WO1994010643A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997028654A3 (fr) * 1996-02-01 1997-10-09 Rt Set Ltd Systeme d'incrustation couleur en studio
WO2001067430A1 (fr) * 2000-03-09 2001-09-13 Auteuil Participation Et Conseil Procede pour le codage d'images
CN116936041A (zh) * 2023-09-18 2023-10-24 天河超级计算淮海分中心 一种医学影像文件处理方法、电子设备及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4774678A (en) * 1985-03-07 1988-09-27 Sony Corporation Video signal processing
US4849745A (en) * 1984-06-15 1989-07-18 Kabushiki Kaisha Toshiba Multiple memory image display apparatus
US4907171A (en) * 1986-03-28 1990-03-06 Kabushiki Kaisha Toshiba Image size converter
US5051927A (en) * 1987-03-03 1991-09-24 Minolta Camera Kabushiki Kaisha Image editing apparatus for transferring a partial image from one locale to another

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849745A (en) * 1984-06-15 1989-07-18 Kabushiki Kaisha Toshiba Multiple memory image display apparatus
US4774678A (en) * 1985-03-07 1988-09-27 Sony Corporation Video signal processing
US4907171A (en) * 1986-03-28 1990-03-06 Kabushiki Kaisha Toshiba Image size converter
US5051927A (en) * 1987-03-03 1991-09-24 Minolta Camera Kabushiki Kaisha Image editing apparatus for transferring a partial image from one locale to another

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997028654A3 (fr) * 1996-02-01 1997-10-09 Rt Set Ltd Systeme d'incrustation couleur en studio
WO2001067430A1 (fr) * 2000-03-09 2001-09-13 Auteuil Participation Et Conseil Procede pour le codage d'images
FR2806227A1 (fr) * 2000-03-09 2001-09-14 Auteuil Participation Et Conse Procede pour le codage d'images
CN116936041A (zh) * 2023-09-18 2023-10-24 天河超级计算淮海分中心 一种医学影像文件处理方法、电子设备及存储介质
CN116936041B (zh) * 2023-09-18 2023-12-22 天河超级计算淮海分中心 一种医学影像文件处理方法、电子设备及存储介质

Also Published As

Publication number Publication date
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