WO1994011902A1 - Cadre de montage et composant a semi-conducteurs l'utilisant - Google Patents

Cadre de montage et composant a semi-conducteurs l'utilisant Download PDF

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Publication number
WO1994011902A1
WO1994011902A1 PCT/JP1993/001677 JP9301677W WO9411902A1 WO 1994011902 A1 WO1994011902 A1 WO 1994011902A1 JP 9301677 W JP9301677 W JP 9301677W WO 9411902 A1 WO9411902 A1 WO 9411902A1
Authority
WO
WIPO (PCT)
Prior art keywords
leads
outer leads
lead frame
lead
base film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP1993/001677
Other languages
English (en)
Japanese (ja)
Inventor
Fumio Kuraishi
Kazuhito Yumoto
Mamoru Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP6511935A priority Critical patent/JPH07506935A/ja
Priority to EP93924830A priority patent/EP0621982A1/fr
Publication of WO1994011902A1 publication Critical patent/WO1994011902A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/435—Shapes or dispositions of insulating layers on leadframes, e.g. bridging members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H10W40/77—Auxiliary members characterised by their shape
    • H10W40/778—Auxiliary members characterised by their shape in encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/453—Leadframes comprising flexible metallic tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42—Fillings
    • H10W76/47—Solid or gel fillings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present invention relates to a lead frame and a semiconductor device using the same lead frame .
  • This invention also relates to a process for making such a lead frame.
  • a TAB tape can be made by forming a thin conductive film on an electrically insulative base film and etching the conductive film to form a desired conductive pattern .
  • the thickness of such conductive patterns can be reduced to about several tens of ⁇ .
  • the lead frame is hermetically sealed with resin to obtain a
  • the lead frame is also hermetically sealed with resin to obtain a semiconductor device product.
  • a TAB tape includes a plurality of leads which are made of
  • An object of the present invention is to provide a lead frame and a semiconductor device using the same lead f rame, in which the lead frame can be easily handled, as if it was a lead frame using a TAB tape or thin material, so that a semiconductor device product using such a lead frame can easily be mounted on a printed circuit board.
  • a lead frame adapted to be used for a semiconductor device comprising: a plurality of inner leads made of a thin conductive material for easily f orming af ine pattern of said inner leads; and a
  • a semiconductor device comprising: (a) a lead frame adapted to be used for a semiconductor device comprising: a plurality of inner leads made of a thin conductive material for easily forming af ine pattern of said inner leads; and a plurality of outer leads formed formed with said respective inner leads, said outer leads being coated with metal layers to increase the thickness thereof, so that a desired strength of said outer leads is obtained; (b) a semiconductor chip electrically connected to said inner leads; and (c) a resin for hermetically sealing said semiconductor chip and a part of said lead f rame including said inner leads.
  • a semiconductor device comprising: (a) a lead frame comprising: an insulating base f ilm having a device hole at a central position thereof and window holes located apart from said device hole; a conductive pattern formed on said insulating base film, said conductive pattern including a plurality of inner leads and a plurality of outer leads formed formed with said respective inner leads, so that each said inner lead extends inward into said central device hole and each said outer lead extends outward from said inner lead over said window hole; and said inner leads being relatively thin, but said outer leads being coated with metal layers to increase the thickness that, so that a desired strength of said outer leads is obtained; (b) a semiconductor chip mounted on and electrically connected to said inner leads within said central opening; and (c) a resin for hermetically sealing said semiconductor chip and a part of said lead frame
  • a semiconductor device comprising :( a) a lead frame comprising: an insulating base film having window holes located apart from a central position of said base film; a conductive pattern formed on said insulating base film, said conductive pattern including a plurality of inner leads and a plurality of outer leads, formed with said respective inner leads, so that each said inner lead extends toward said die-pad and each said outer lead extends outward from said inner lead over said window- hole; and said inner leads being relatively thin, but said outer leads being coated with metal layers to increase the thickness thereof, so that a desired
  • FIGS. 1A-ID are plan views of some embodiments of a lead frame according to the present invention.
  • Figures 2A-2D are plan views of embodiments of a semiconductor device using a lead frame shown in
  • Figure 3 is a cross-sectional view of a
  • Figure 4 is a cross-sectional view of a
  • Figures 5A-5C are cross-sectional views of some variations of a lead frame according to the present invention.
  • Figures 6A-6D are cross-sectional views of some variations of an inner lead-bonding type semiconductor device according to the present invention.
  • Figure 7 is a cross-sectional view of an embodiment of a wire-bonding type semiconductor device according to the present invention.
  • Figure 8 is a cross-sectional view of another embodiment of a wire-bonding type semiconductor device according to the present invention.
  • Figures 9A-9D are cross -sectional views of some variations of a potted type semiconductor device
  • Figure 10 is a cross-sectional view of another embodiment of a potted type semiconductor device
  • Figure 11 is a cross -sectional view of an embodiment of an inner lead-bonding type semiconductor device having a heat spreader or heat sink;
  • Figure 12 is a cross-sectional view of an embodiment of a wire-bonding type semiconductor device having a heat spreader
  • Figure 13 is a cross-sectional view of another embodiment of a wire-bonding type semiconductor device having a heat spreader.
  • Figs .1A ID are plan views of some embodiments of a lead frame composed as a TAB tape according to the present invention .
  • the TAB tape s an electrically insulating flexible base film 10, made of a material such as a polyimide, and an electrically conductive pattern formed on a surface of the base film .
  • the conductive pattern having a desired pattern can be formed by any consistent known method, such as by etching the conductive thin film attached on the base film 10. Any known method can be used, such as a sputtering, vapor deposition, or adhering a copper foil onto the base film using any suitable adhesive.
  • the base film 10 of the (inner lead bonding type) TAB tapes shown in Figs .1A and IB is first provided with a device hole 12 at the central position of the TAB tape, four window holes 14 located apart from the device hole and symmetrically arranged to each other, and sprocket holes 16 equidistant ly and regularly arranged at the edges of the TAB tape .
  • a copper foil is then adhered to the base film 10 and etched to obtain a desired
  • the conductive pattern insulating inner leads 18 having the respective inner tips extending inward to the inside of the device hole 12 and the corresponding outer leads 20 extending outward from the respective inner leads 18 and over the window holes 14,
  • the outer leads 20 are cut at the outer edge of the window holes 14,, as shown line P in Fig, lA f after a semiconductor chip (not shown) is mounted on the TAB tape and hermetically sealed with resin (not shown).
  • the (wire-bonding type) TAB tape shown in Figs .1C and ID is substantially the same as the TAB tape shown in Figs .1A and IB, except that the base film 10 has no central device hole, but a conductive die pad 28 is formed at the central position of the TAB tape, Such a conductive die pad 28 can be formed simultaneously with the conductive pattern comprising inner and outer leads 18 and 20 *
  • tie bar 20a is provided for continuously connecting the outer leads.
  • tie bar 20a can also be formed simultaneously with the conductive pattern comprising inner and outer
  • tie bars 20a are cut out to separate the adjacent outer leads 20 from each other, as shown lines Q in Figs ⁇ IB and ID, after a semiconductor chip (not shown) is mounted on the TAB tape and
  • FIGs 2A-2D semiconductor devices using lead frames of Figs 1A -. ID, respectively r are shown
  • Fig -.. 3 is a cross -sectional view of the (inner lead bonding type) TAB tape shown semiconductor device of Fig 2A or 2B .
  • Fig. 4 is a cross-sectional view of the (wire-bonding type) semiconductor device of Fig. 2C or 2D.
  • the conductive part of the outer lead is increased, in such a manner that the outer lead has a thickness substantially the same as the outer lead of a conventional met l lead frame-resulting, in the embodiment of this
  • the foil is etched to obtain a desired
  • the width of the outer lead 20 can also be
  • the thickness of the inner leads 18 i.e., the thickness of the copper foil
  • the thickness of the outer leads 20 can be thus increased to about 125 ⁇ .
  • solder resist 22 is coated on the inner leads 18 at a position of the inner leads 18 corresponding to a clamp position of a mold (not shown) which is used, at a later stage, for hermetically sealing the semiconductor device with a resin 26, in such a manner that the gaps between the adjacent inner leads 18 are filled with the resist to prevent the sealing
  • the semiconductor chip 24 is mounted on the TAB tapes, in such a manner that the s emi conductor chip 24 is connected to the inner leads 18 by a simultaneous bonding via bumps 18a provided on the surfaces of the semiconductor chip 24. Then, the TAB tape is clamped by the mold (not shown) in the direction of thickness between the base film 10 and solder resist 22 and a resin 26 is then filled in the mold to obtain a hermetically sealed semiconductor device.
  • a wire-bonding type TAB tape the die pad 28 and the inner leads 18 are mutually supported by the base film portion 30, which maintains the micro-pattern of inner leads 18 to prevent any movement thereof .
  • a semiconductor chip 24 is mounted on the die pad 28 of the TAB tape and, then, the t
  • the outer leads 20 can be prevented from being easily deformed or bent.
  • Fig. 7 is a cross -sectional view of a wire-bonding type semiconductor device, in which the semiconductor chip 24 is mounted on the lower surface of the die pad 28 and connected to the inner leads 18 by the bonding wires 18b through the second window holes 14a, as
  • Fig, 7 shows an embodiment in which the solder resist 22 is coated on the inner
  • solder resist 22 can be coated after the copper-plating as the embodiment of Fig, 6B, or such a solder resist 22 may either be coated before or after the copper-plating, as the
  • Fig. 8 is a cross-sectional view of another wire- bonding type semiconductor device, in which the
  • solder resist 22 is coated on the inner leads 18 before the copper- plating, in the same manner as the embodiment of Fig, 6A, such a solder resist 22 can be coated after the copper- plating as the embodiment of Fig .6B, or either before or af ter the copper-plating as the embodiment of Fig .6C .Also, there may be no such solder resist (22) as the embodiment of Fig .6D.
  • insulating base f ilm 10 made of such as a polyimide, is replaced by a metal plate, the conductive pattern
  • Fig .12 (wire-bonding type) is substantially the same as the embodiment of Fig .7, except that a heat spreader 34 is disposed in the same manner as the embodiment of Fig .12 ⁇
  • spreader 34 in this embodiment isolated a central convex portion which contacts the die-pad 28 opposite the semiconductor chip 24, an intermediate upper portion exposed to the outside, and a peripheral portion which contacts the solder resist 22 ⁇
  • Fig .13 is substantially the same as the embodiment of Fig .8, except that a heat spreader 34 is disposed in the same manner as the above-mentioned embodiments ⁇
  • the heat spreader 34 in this embodiment cross a central convex portion which contacts the base f ilm 10 opposite the die- pad 28 and the semiconductor chip 24, an intermediate bottom portion exposed to the outside, and a peripheral portion which also contacts the same base film 10
  • a metal plate made of copper or 42% copper alloy with an electrically insulating layer on the surface thereof is used as a base film .However, such a base film of metal plate can also be used in the embodiments other than those of Figs .8 and 10.
  • the lead frame can be made in accordance with a similar process for making a TAB tape, in which a copper foil is f irst formed on a base insulating f ilm and then a conductive pattern is formed by etching the copper foil .
  • the lead frame can also be made in accordance with a process in which a lead pattern is f irst formed and then the lead pattern is supported by an insulating film .
  • the lead frame thus made can be used to mount a semiconductor chip thereon and can be handled in the same manner as a conventional lead f rame, A semiconductor device product sealed with a resin can also be easily- handled,
  • "lead frame" used for mounting thereon a semiconductor chip is also referred to as "TAB tape"
  • the outer leads can be plated partially with copper, in the embodiments as mentioned above .However, in practice, the following methods can be employed, in consideration of the bonding characteristic at the inner lead portions and the mounting characteristic at the outer lead portions .In any case, copper can be used as a base material to increase the thickness of the outer leads.
  • the outer leads are plated with copper or solder to increase the thickness that .
  • the entire lead surfaces including inner and outer leads are plated with nickel as an under layer, then all of the leads are plated with a gold, and then only the outer lead portions are subjected to plating to increase the thickness agree-In this case, to increase the thickness, 'the outer leads may be plated with copper r plated with solder after plated with copper, or plated with solder in place of copper ⁇ Thus r the portions of the outer leads plated with copper or solder, which is exposed to the outside.
  • Both inner and outer leads are plated with palladium to form protective layers .
  • all the lead surfaces, including inner and outer leads are plated with palladium .
  • the copper foil is plated with nickel as an underlayer
  • the outer lead portions are subjected to plating to increase the thickness that, and then the entire lead surface including inner and outer leads are plated with palladium-In this case, after the outer lead portions are plated with copper to increase the thickness thereof, solder may further be plated thereon.
  • Both inner and outer leads are plated with tin to form a protective layer .
  • tin can be plated directly on the copper material without an underlayer, only the outer lead portions are first plated with a copper or solder to increase the thickness
  • the outer lead portions may be first plated with copper and then plated with solder to increase the thickness thereof and then the entire lead surface including inner and outer leads may be plated with tin.
  • the thickness of the inner leads can be any thickness of the inner leads.
  • this method is particularly suitable for making a TAB tape having fine patterns
  • the thickness of the plated layer can advantageous ly be selected in such a manner that the thickness of the plated gold is 0, 3 to 5 ⁇ , the thickness of the plated nickel is 1 to 20 ⁇ / the thickness of the plated palladium is 0 .1 to 0.5 ⁇ , and the thickness of the plated tin is about 0 .5 ⁇ .
  • the thickness of the plated layer for increasing the thickness of the outer leads may be 50 to 70 ⁇ .
  • the base copper material has a thickness of about several tens of ⁇ ⁇ the entire thickness of the outer lead including the plated underlayer or the like may thus be about ⁇ .
  • the outer leads are subjected to plating to increase the thickness that, the thickness of the outer leads 20 may be increased by any other method, such as sputtering, vapor deposition, or the like method.

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

Dans un cadre de montage destiné à être utilisé pour un composant à semi-conducteurs, une pluralité de fils intérieurs (18) sont constitués d'un matériau conducteur mince permettant la formation aisée d'un motif fin des fils intérieurs. Une pluralité de fils extérieurs (20) sont formés d'une seule pièce avec les fils intérieurs respectifs. Les fils extérieurs sont revêtus de couches métalliques pour augmenter leur épaisseur, ce qui permet d'obtenir la résistance souhaitée des fils extérieurs. Une puce (24) est connectée électriquement aux fils intérieurs. Cette puce et une partie du cadre de montage comprenant les fils intérieurs sont scellées hermétiquement avec une résine (26) et, ainsi, on obtient un composant à semi-conducteurs.
PCT/JP1993/001677 1992-11-17 1993-11-16 Cadre de montage et composant a semi-conducteurs l'utilisant Ceased WO1994011902A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP6511935A JPH07506935A (ja) 1992-11-17 1993-11-16 リードフレーム及びそれを用いた半導体装置
EP93924830A EP0621982A1 (fr) 1992-11-17 1993-11-16 Cadre de montage et composant a semi-conducteurs l'utilisant

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP33253192 1992-11-17
JP4/332531 1992-11-17
JP5/63738 1993-03-23
JP6373893 1993-03-23

Publications (1)

Publication Number Publication Date
WO1994011902A1 true WO1994011902A1 (fr) 1994-05-26

Family

ID=26404868

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1993/001677 Ceased WO1994011902A1 (fr) 1992-11-17 1993-11-16 Cadre de montage et composant a semi-conducteurs l'utilisant

Country Status (3)

Country Link
EP (1) EP0621982A1 (fr)
JP (1) JPH07506935A (fr)
WO (1) WO1994011902A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996007204A1 (fr) * 1994-08-26 1996-03-07 National Semiconductor Corporation Boitier composite ultra-mince pour circuits integres
WO2004015769A1 (fr) * 2002-08-05 2004-02-19 Osram Opto Semiconductors Gmbh Procede pour realiser un cadre electriquement conducteur et procede pour realiser un composant semi-conducteur qui peut etre monte en surface, et strie de cadre conducteur
US6995029B2 (en) 2002-08-05 2006-02-07 Osram Opta Semiconductors Gmbh Fabricating surface mountable semiconductor components with leadframe strips

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4688647B2 (ja) * 2005-11-21 2011-05-25 パナソニック株式会社 半導体装置とその製造方法
JP5971531B2 (ja) * 2014-04-22 2016-08-17 大日本印刷株式会社 樹脂封止型半導体装置及びその製造方法
WO2026018399A1 (fr) * 2024-07-18 2026-01-22 Ａｓｔｅｍｏ株式会社 Module semi-conducteur et procédé de fabrication de module semi-conducteur

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT315947B (de) * 1971-03-26 1974-06-25 Interelectric Ag Verfahren zum Herstellen eines Systemträgers für integrierte Schaltkreise
JPS62196840A (ja) * 1986-02-24 1987-08-31 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
US4707724A (en) * 1984-06-04 1987-11-17 Hitachi, Ltd. Semiconductor device and method of manufacturing thereof
JPS63239829A (ja) * 1987-03-27 1988-10-05 Hitachi Ltd 電子装置
JPH02250364A (ja) * 1989-03-23 1990-10-08 Toppan Printing Co Ltd リードフレーム及びその製造方法
JPH04102341A (ja) * 1990-08-22 1992-04-03 Shinko Electric Ind Co Ltd Ｔａｂテープの製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT315947B (de) * 1971-03-26 1974-06-25 Interelectric Ag Verfahren zum Herstellen eines Systemträgers für integrierte Schaltkreise
US4707724A (en) * 1984-06-04 1987-11-17 Hitachi, Ltd. Semiconductor device and method of manufacturing thereof
JPS62196840A (ja) * 1986-02-24 1987-08-31 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JPS63239829A (ja) * 1987-03-27 1988-10-05 Hitachi Ltd 電子装置
JPH02250364A (ja) * 1989-03-23 1990-10-08 Toppan Printing Co Ltd リードフレーム及びその製造方法
JPH04102341A (ja) * 1990-08-22 1992-04-03 Shinko Electric Ind Co Ltd Ｔａｂテープの製造方法

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 12, no. 49 (E - 582) 13 February 1988 (1988-02-13) *
PATENT ABSTRACTS OF JAPAN vol. 13, no. 044 (E - 710) 31 January 1989 (1989-01-31) *
PATENT ABSTRACTS OF JAPAN vol. 14, no. 576 (E - 1016) 21 December 1990 (1990-12-21) *
PATENT ABSTRACTS OF JAPAN vol. 16, no. 340 (E - 1238) 3 April 1992 (1992-04-03) *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996007204A1 (fr) * 1994-08-26 1996-03-07 National Semiconductor Corporation Boitier composite ultra-mince pour circuits integres
US6184575B1 (en) 1994-08-26 2001-02-06 National Semiconductor Corporation Ultra-thin composite package for integrated circuits
WO2004015769A1 (fr) * 2002-08-05 2004-02-19 Osram Opto Semiconductors Gmbh Procede pour realiser un cadre electriquement conducteur et procede pour realiser un composant semi-conducteur qui peut etre monte en surface, et strie de cadre conducteur
US6995029B2 (en) 2002-08-05 2006-02-07 Osram Opta Semiconductors Gmbh Fabricating surface mountable semiconductor components with leadframe strips
CN100533723C (zh) * 2002-08-05 2009-08-26 奥斯兰姆奥普托半导体有限责任公司 电引线架的制造方法,表面安装的半导体器件的制造方法和引线架带
US7695990B2 (en) 2002-08-05 2010-04-13 Osram Opto Semiconductors Gmbh Fabricating surface mountable semiconductor components with leadframe strips

Also Published As

Publication number Publication date
JPH07506935A (ja) 1995-07-27
EP0621982A1 (fr) 1994-11-02

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