WO1994015280A3 - Architecture informatique destinee au transfert de donnees parallele dans des langages informatiques declaratifs - Google Patents

Architecture informatique destinee au transfert de donnees parallele dans des langages informatiques declaratifs Download PDF

Info

Publication number
WO1994015280A3
WO1994015280A3 PCT/EP1993/003636 EP9303636W WO9415280A3 WO 1994015280 A3 WO1994015280 A3 WO 1994015280A3 EP 9303636 W EP9303636 W EP 9303636W WO 9415280 A3 WO9415280 A3 WO 9415280A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
data transfer
heap
stack
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP1993/003636
Other languages
English (en)
Other versions
WO1994015280A2 (fr
Inventor
Robert Milikowski
William Gerard Vree
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EUROP I OF TECHNOLOGY
Original Assignee
EUROP I OF TECHNOLOGY
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EUROP I OF TECHNOLOGY filed Critical EUROP I OF TECHNOLOGY
Publication of WO1994015280A2 publication Critical patent/WO1994015280A2/fr
Publication of WO1994015280A3 publication Critical patent/WO1994015280A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4496—Unification in logic programming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Les calculs effectués par des machines de réduction de graphes réalisant une réduction de graphe paresseuse impliquent de ré-écrire un tel graphe de façon répétitive jusqu'à l'obtention d'un résultat final. A cette fin, une mémoire est divisée en sections d'entreposage et de pile faisant l'objet d'accès fréquents entraînant un embouteillage car le transfert de données est commandé par une unité centrale de traitement (CPU) et transite par un seul bus de données. On résout ce problème en utilisant plusieurs modules (13, 14, 16, 17) comprenant chacun une section de mémoire d'entreposage ou de mémoire de pile, une unité arithmétique/logique (ALU) et une charnière (dispositif de commutation) destinée à coupler la section de mémoire à un réseau de bus (15) du système ou à une mémoire d'instruction à très longs mots d'instruction (VLIW) (21, 22, 23). Le transfert de données entre l'entreposage et la pile peut alors s'effectuer en parallèle sans recourir à un circuit de traitement global (20), lequel effectue toutes les opérations de calcul conventionnelles qui n'impliquent aucun transfert de données et commande aussi le fonctionnement de l'ensemble du programme stocké dans la mémoire VLIW. De façon générale, cette architecture convient spécialement au parallélisme concernant le niveau des instructions où beaucoup de ces dernières concernent des opérations liées à la mémoire.
PCT/EP1993/003636 1992-12-18 1993-12-20 Architecture informatique destinee au transfert de donnees parallele dans des langages informatiques declaratifs Ceased WO1994015280A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP92311586 1992-12-18
EP92311586.9 1992-12-18

Publications (2)

Publication Number Publication Date
WO1994015280A2 WO1994015280A2 (fr) 1994-07-07
WO1994015280A3 true WO1994015280A3 (fr) 1994-09-01

Family

ID=8211582

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1993/003636 Ceased WO1994015280A2 (fr) 1992-12-18 1993-12-20 Architecture informatique destinee au transfert de donnees parallele dans des langages informatiques declaratifs

Country Status (1)

Country Link
WO (1) WO1994015280A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6577316B2 (en) * 1998-07-17 2003-06-10 3Dlabs, Inc., Ltd Wide instruction word graphics processor
US6542989B2 (en) * 1999-06-15 2003-04-01 Koninklijke Philips Electronics N.V. Single instruction having op code and stack control field

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL9100598A (nl) * 1991-04-05 1992-11-02 Henk Corporaal Move: een flexibele en uitbreidbare architectuur voor het ontwerpen van processoren.

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL9100598A (nl) * 1991-04-05 1992-11-02 Henk Corporaal Move: een flexibele en uitbreidbare architectuur voor het ontwerpen van processoren.

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
HIDEKAZU YAMADA ET AL.:: "A Feed-Forward General Purpose Computer", SYSTEMS, COMPUTERS, CONTROLS,, vol. 14, no. 4, July 1984 (1984-07-01), WASHINGTON, US,, pages 81 - 89, XP000211913 *
L. AUGUSTSSON:: "BWM: a concrete machine for graph reduction", FUNCTIONAL PROGRAMMING: PROCEEDINGS OF THE 1991 GLASGOW WORKSHOP,, 12 August 1991 (1991-08-12), PORTREE, UK,, pages 36 - 50 *
M. BEEMSTER ET AL.:: "Experience with a Clustered Parallel Reduction Machine", FUTURE GENERATION COMPUTER SYSTEMS,, vol. 9, no. 3, September 1993 (1993-09-01), NL,, pages 175 - 200, XP000412031 *
R. MILIKOWSKI ET AL.:: "The G-hinge - A VLIW processor for graph reduction", TECHNICAL REPORT CS-92-21, DEPARTMENT OF COMPUTER SYSTEMS, FACULTY OF MATHEMATICS AND COMPUTER SCIENCE, UNIVERSITY OF AMSTERDAM,, May 1993 (1993-05-01), AMSTERDAM, NL,, pages 1 - 14 *
R. MILIKOWSKI ET AL.:: "The G-line: a distributed processor for graph reduction", PARLE '91 PARALLEL ARCHITECTURES AND LANGUAGES EUROPE: PARALLEL ARCHITECTURES AND ALGORITHMS,, vol. I, 10 June 1991 (1991-06-10), EINDHOVEN, NL,, pages 119 - 136 *
ROBERT P. COLWELL ET AL.:: "A VLIW Architecture for a trace scheduling compiler", PROCEEDINGS OF THE SECOND INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS (ASPLOS II),, 5 October 1987 (1987-10-05), PALO ALTO, CA, US,, pages 180 - 192, XP000042316 *

Also Published As

Publication number Publication date
WO1994015280A2 (fr) 1994-07-07

Similar Documents

Publication Publication Date Title
US3787673A (en) Pipelined high speed arithmetic unit
US20080180450A1 (en) Split Embedded DRAM Processor
NZ334674A (en) System for allowing I/O processor to operate under different transfer algorithms
CN101398753A (zh) 用于执行扫描运算的系统、方法及计算机程序产品
ATE203114T1 (de) Datenstapel und austauschbefehl
EP0375950A3 (fr) Méthode et mise en oeuvre sous forme matérielle d'instructions de transfert de données complexes
JPH11316686A (ja) コンピュ―タシステムのｂｉｏｓデ―タ格納装置及びその駆動方法
DK9981A (da) Overfoeringsmaskine - universal computer
JPS63240664A (ja) 高速処理計算機
JPH06222920A (ja) レジスタファイルのグループを共有する演算ユニットを持つデータプロセッサ
WO1994015280A3 (fr) Architecture informatique destinee au transfert de donnees parallele dans des langages informatiques declaratifs
Halin et al. The ETH multiprocessor project: Parallel simulation of continuous systems
JPH02148223A (ja) レジスタ退避復活装置
EP0299075A4 (fr) Unite de traitement possedant au moins un coprocesseur.
Männer et al. The Heidelberg POLYP—A flexible and fault-tolerant poly-processor
Shu et al. A multiple-level heterogeneous architecture for image understanding
JPS57113144A (en) Stored program computer
Imamura et al. Eigen-G: GPU-based eigenvalue solver for real-symmetric dense matrices
US20250378036A1 (en) Machine learning acceleration architecture
JPS6478361A (en) Data processing system
Houzet VLSI Implementation of the Real-Time Image Processing Parallel Architecture GFLOPS
Dorta et al. Parallelizing dense linear algebra operations with task queues in llc
Poon et al. Fifth workshop on computer architecture for non-numeric processing: A flexible image processor using array elements
Atwah et al. An associative dynamic convex hull algorithm
Vafaie et al. Application of petri-nets in the hermes data flow machine: an overview

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP US

Kind code of ref document: A1

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

CFP Corrected version of a pamphlet front page
CR1 Correction of entry in section i

Free format text: PAT.BUL.15/94 UNDER PUBLISHED REPLACE "A1" BY "A2"

AK Designated states

Kind code of ref document: A3

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase