WO1996005657A1 - Dispositif electronique de comptage - Google Patents

Dispositif electronique de comptage Download PDF

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Publication number
WO1996005657A1
WO1996005657A1 PCT/GB1994/001744 GB9401744W WO9605657A1 WO 1996005657 A1 WO1996005657 A1 WO 1996005657A1 GB 9401744 W GB9401744 W GB 9401744W WO 9605657 A1 WO9605657 A1 WO 9605657A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
counter
counter device
counts
count
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/GB1994/001744
Other languages
English (en)
Inventor
Christopher William Haythornthwaite
David William Clark
Ian David Griffiths
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GENESIS GROUP Ltd
Original Assignee
GENESIS GROUP Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to GB9302078A priority Critical patent/GB2274935A/en
Priority claimed from GB9302078A external-priority patent/GB2274935A/en
Application filed by GENESIS GROUP Ltd filed Critical GENESIS GROUP Ltd
Priority to AU73481/94A priority patent/AU7348194A/en
Priority to PCT/GB1994/001744 priority patent/WO1996005657A1/fr
Publication of WO1996005657A1 publication Critical patent/WO1996005657A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
    • H03K21/403—Arrangements for storing the counting state in case of power supply interruption

Definitions

  • This invention relates to an electronic counter device suitable for use as a replacement for the electro-mechanical counters currently used in gaming machines, vending machines, product counting on production lines, and the like.
  • An example of the type of machine currently employing electro ⁇ mechanical counters is the gaming machine which is generally provided with one or more counters or meters to enable the operation of the machine to be monitored. For example, the numbers of coins or tokens of specified types inserted into the machine can be recorded, together with numbers of coins or tokens paid out in prizes. This information can be used to assess the profitability of the machine, and its pay-out ratio for example. With the increasing sophistication of the machines, there is a need for more detailed information to be recorded. In addition, it is increasingly necessary to take measures against fraud by tampering with the operation of the machine and the meters.
  • the present invention seeks, in its various aspects, to provide an electronic counter device which overcomes these disadvantages.
  • an electronic counter device comprises a counter input for receiving an electrical signal representing successive counts, means for accumulating the counts received at said input, display means for displaying the count or a value derived therefrom, a clock for outputting the current date and time, a non-volatile memory, and means for storing the instantaneous count, date and time in the non-volatile memory in response to detection of any one of a plurality of predetermined events.
  • the predetermined events include: an attempt to download data to the counter with the incorrect protocol; an input signal rate exceeding the specified rate; and a loss of system power supply for more than a predetermined period, for example 500ms.
  • the display may also include a plurality of dedicated icons to indicate events such as those specified above and detection of tampering.
  • the counter device comprises means for separately accumulating a plurality of counts.
  • all the accumulated counts are stored in the non-volatile memory along with the date and time in response to detection of any of the predetermined events.
  • Another aspect of the invention provides an electronic counter device in data communication with an external device, the counter device comprising means for receiving data representing counts and for accumulating values derived from the counts, and communication means for transmitting data to and receiving data messages from the external device, the data messages comprising data representing counts or data relating to the derivation of values from the counts, the external device being arranged to transmit discrete data messages to the counter device continually with a time interval therebetween no greater than a predetermined value and the external device and counter device being arranged to perform at least one handshake therebetween in association with the transmission of each data message, the failure of any handshake interrupting repetition of the data messages, thereby indicating an error.
  • the handshake preferably comprises the transmission by one device of a predetermined value, followed by the return by the other device within a predetermined time limit of a predetermined response value.
  • the handshake comprises performance by the counter device of a checksum calculation on the data message and transmission of the result to the external device.
  • Figure 1 is a block circuit diagram of a counter device
  • Figure 2 is a diagram illustrating the relative clock and data pulse timings in accordance with standard protocol
  • Figure 3 is an expanded section of the diagram of Figure 2.
  • Figure 4 is a flow chart illustrating the operation of the counter device in accordance with the second aspect of the invention.
  • the counter device comprises five count input ports la to le, each having its respective input buffer 2a to 2e through which counts are input to a microcontroller 3 as pulses complying with the specification set out in the Table below.
  • the microcontroller 3 outputs values related to the counts to a display 4, for example a 40 digit, 7 segment LCD display, capable of displaying an 8-digit value for each of the five inputs.
  • the microcontroller is supplied with operating power via a power supply unit 5, which also removes excessive interference from the input supply, for example voltage spikes, caused by the proximity of other electro-mechanical components of the host machine.
  • the power supply unit also detects a failure in the supply and enables a battery backup support 6 to maintain operation of the counter device for a sufficient time to permit the counts to be stored for retrieval when power is restored.
  • a non-volatile memory for example in the form of an Electrically-Erasible Programmable Read Only Memory or EEPROM 7, is used to store the counts, or the related values, together with time and date in the event of a power failure, loss of communications or detection of any attempt to tamper with the counter device by downloading incorrect data.
  • the EEPROM having a limited capacity, it is used as a ring buffer, with the oldest data overwritten by the newest.
  • a bidirectional serial channel 9 provides an alternative communication with the computer in the host machine or with an external device.
  • Figures 2 and 3 illustrate a simple serial protocol designed to be driven from existing meter drive circuitry common to all types of gaming machines, for example. Up to 5 internal counters and 3 external satellite counters may be addressed, but only one count can be added to any counter at any time. Connection is made between the existing +12V and two counter inputs. The first input is used as a twin edge clock source and a source of ground potential, while the second input is the data stream and also provides a ground potential. Both inputs are used as the current feedback sense path. When the device is not in use, the two inputs are both inactive, open circuit and are pulled high by resistors (not shown) in the device.
  • two synchronisation pulses are sent by driving both inputs low simultaneously with a pulse timing indicated in Figures 2 and 3.
  • the inputs are then driven low simultaneously for a minimum period of 40ms and a maximum period of 45ms. This period between the end of the synchronisation pulses and the start of the clocking cycle is called the start period.
  • the low to high transition of the first input (designated as the clock signal) causes the level on the output designated as the data output to be read into the device approximately 5ms later (this settling time allows for systems where these outputs cannot change simultaneously). Thereafter, each change in the state of the clock input marks the next data bit to be read.
  • the data bit will be deemed to be set (i.e. logical TRUE or 1), and if the data input voltage is high at this time, then the data bit is deemed to be clear (i.e. logical FALSE or 0).
  • logical TRUE a maximum time period between active edges of the data clock of 20ms, and any interval longer than this constitutes a timeout. If a timeout does occur, the current data frame is ignored, and a new data frame cannot start until the synchronisation pulses and start period as hereinbefore defined have been received.
  • the data input after the start period has ended has the following significance:
  • a parity bit This bit is set if an odd number of the three data bits and the test meter bit described in 1 and 2 are set.
  • both inputs are driven low for at least 105ms to confirm this transaction.
  • the meter load is developed across the +12V DC line and the inputs allowing the current to be sensed at the host system. If the meter circuit detects that a test phase has been initiated, it will increase the supply load during this test phase by the equivalent amount of the mechanical metering system, if the metering system is functioning correctly. If the host is issuing a meter count message, then an increase in the supply current equivalent to the normal mechanical metering system will be simulated by this meter. This will be sensed by the host in the same way that mechanical meter integrity is checked.
  • the inputs When the current sense pulse ends, or after 106ms if detection by the host system is not possible, the inputs return to their inactive high state and any active supply load will be removed.
  • the timing relationship between the inputs is shown in Figures 2 and 3.
  • the maximum current drawn by the counter device during non-pulse periods will be less than 1mA.
  • active pulse or test periods it is the same as for a mechanical meter. Data is valid between 4ms and 8ms from the point at which the clock input voltage is at 50% of its maximum value on the rising or falling clock edge.
  • the input circuit is arranged to reject spikes of up to 2ms, and by inference will also delay the clock edge by up to 2ms.
  • the clock and data transmissions should therefore be as near as possible coincident, or the clock should lag the data transmission by no more than ' 2ms.
  • the interval between each successive cycle defined as the time between the start of two successive start periods, must not be less than 300ms.
  • connection 9 (Fig 1) between the host computer and the counter device can use 2 TTL compatible signal lines (and a common ground) to transfer data.
  • One line is data received (DRX) and the other is data transmitted (DTX).
  • Data is suitably transmitted in a serial format in accordance with the data timing protocol of RS232C (but with TTL voltage levels as per RS423).
  • communication with an internal device can be by optical or radio coupling.
  • the value displayed by the counter device for each counter may be a simple count, it may alternatively be a value derived therefrom. For example, if each count represents number of a particular value of coin paid into the gaming machine, a separate counter display for each input may show the total monetary value of each type of coin, with another counter indicating the aggregate value of all the coins, for example.
  • a transaction will be initiated by the host computer by transmitting SOH (OlHex) to the counter device, which will respond within a predetermined period with a VERIFY byte which is generated randomly or pseudorandomly. If the VERIFY byte is received, the host computer returns a KEY byte which it generates from the VERIFY byte by any suitable encoding algorithm. The counter device compares the returned KEY byte with the VERIFY byte it sent using the same stored algorithm, and if the KEY byte is correct, the counter device responds with ACK (06Hex). If the KEY is wrong, the counter device does not return ACK and so the host computer returns to the sign-on error handler.
  • the counter device is arranged to flag an error if, say, two wrong KEY bytes are received consecutively, and to close down and ignore all further serial input for a predetermined period, for example one hour.
  • the sign-on error handler permits only three attempts at signing on, for example.
  • the host computer maintains a timer which will ensure that a message is sent at regular predetermined intervals, for example of three seconds, whether or not the counter needs to be addressed. This will make it very difficult to tamper with the system, since both the host computer and the counter device will detect a break in communications, and can thus give an indication of an attempt to tamper with the system.
  • the message timer will be reset after ACK has been received, and the host computer will then check to see if a message needs to be sent to the counter device. If not, it checks that a message has been sent within the previous three seconds (or whatever the maximum interval set is to be). If no message has been sent within this period, the host computer initiates the sign on procedure by sending SOH.
  • the host computer sends the data byte to the counter device, for example in the form previously described in which the three least significant bits give the address of the meter to be incremented and the remaining bits constitute the data.
  • the counter device calculates the check sum of this message and transmits that check sum to the host computer. If the host computer confirms that this check sum is correct, it transmits ETX (03Hex) to the counter device, which responds by transmitting EOT (04Hex) to the host computer. If the host computer receives EOT within the specified response time, it resets its message timer and restarts the main loop. If the received check sum is incorrect, the host computer transmits NUL (OOHex) to the counter device, and after receiving EOT from the counter device, resets the message timer and resends the message to the counter device.
  • ETX 03Hex
  • EOT 04Hex
  • the host computer If at any time during this transaction the host computer does not receive a handshake message within the response period set, it transmits nothing for one second and then executes a suitable communications time out error handler and initiates the sign on loop by sending SOH.
  • the one second delay allows the counter device to attempt to recover from the partial message transaction, and to set an internal software flag to record the aborted message transaction.
  • the process repeatedly returns to the main loop start until three seconds have elapsed from the sending of the last message, when there is a return to the sign on procedure.

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  • Pinball Game Machines (AREA)

Abstract

Dispositif électronique de comptage ('e.c.d.') comprenant: (i) des moyens d'entrée destinés à saisir les données représentant des comptes successifs; (ii) des moyens de cumul des comptes saisis à l'aide desdits moyens d'entrée; (iii) au moins un écran destiné à afficher le compte cumulé ou une valeur dérivée de celui-ci; iv) une mémoire électronique non volatile; (v) des moyens de stockage du compte cumulé dans ladite mémoire en réponse à une reconnaissance de données ou de signaux résultant d'un ou de plusieurs événement(s) extérieur(s) prédéterminé(s), par exemple une panne de courant; ce dispositif de comptage est conçu aux fins d'émulation d'un compteur électromécanique classique et permet ainsi, lors de son utilisation, de remplacer celui-là de façon plus sûre et inviolable.
PCT/GB1994/001744 1993-02-03 1994-08-09 Dispositif electronique de comptage Ceased WO1996005657A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB9302078A GB2274935A (en) 1993-02-03 1993-02-03 Electronic counter
AU73481/94A AU7348194A (en) 1993-02-03 1994-08-09 Electronic counter device
PCT/GB1994/001744 WO1996005657A1 (fr) 1993-02-03 1994-08-09 Dispositif electronique de comptage

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9302078A GB2274935A (en) 1993-02-03 1993-02-03 Electronic counter
PCT/GB1994/001744 WO1996005657A1 (fr) 1993-02-03 1994-08-09 Dispositif electronique de comptage

Publications (1)

Publication Number Publication Date
WO1996005657A1 true WO1996005657A1 (fr) 1996-02-22

Family

ID=26302382

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1994/001744 Ceased WO1996005657A1 (fr) 1993-02-03 1994-08-09 Dispositif electronique de comptage

Country Status (1)

Country Link
WO (1) WO1996005657A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2357909A1 (fr) * 1976-07-09 1978-02-03 Heliowatt Werke Procede de controle automatique de compteurs
GB2019065A (en) * 1978-03-24 1979-10-24 Pitney Bowes Inc Electronic counter with non-volatile memory
EP0089087A1 (fr) * 1982-03-16 1983-09-21 Koninklijke Philips Electronics N.V. Système de communication, comprenant un ordinateur central, des stations d'accès et des stations extérieures, et incorporant un test cryptographique contre la falsification d'une station extérieure; et des stations extérieures utilisables dans un tel système
EP0244642A2 (fr) * 1986-05-09 1987-11-11 Curtis Instruments, Inc. Système de mesure d'opérations cumulées à état solide

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2357909A1 (fr) * 1976-07-09 1978-02-03 Heliowatt Werke Procede de controle automatique de compteurs
GB2019065A (en) * 1978-03-24 1979-10-24 Pitney Bowes Inc Electronic counter with non-volatile memory
EP0089087A1 (fr) * 1982-03-16 1983-09-21 Koninklijke Philips Electronics N.V. Système de communication, comprenant un ordinateur central, des stations d'accès et des stations extérieures, et incorporant un test cryptographique contre la falsification d'une station extérieure; et des stations extérieures utilisables dans un tel système
EP0244642A2 (fr) * 1986-05-09 1987-11-11 Curtis Instruments, Inc. Système de mesure d'opérations cumulées à état solide

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