WO1998038774A2 - Circuit d'attaque de ligne a impedance de sortie adaptative - Google Patents

Circuit d'attaque de ligne a impedance de sortie adaptative Download PDF

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Publication number
WO1998038774A2
WO1998038774A2 PCT/IB1998/000137 IB9800137W WO9838774A2 WO 1998038774 A2 WO1998038774 A2 WO 1998038774A2 IB 9800137 W IB9800137 W IB 9800137W WO 9838774 A2 WO9838774 A2 WO 9838774A2
Authority
WO
WIPO (PCT)
Prior art keywords
line driver
output terminal
current
coupled
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB1998/000137
Other languages
English (en)
Other versions
WO1998038774A3 (fr
Inventor
Bram Nauta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Philips AB
Philips Norden AB
Original Assignee
Koninklijke Philips Electronics NV
Philips AB
Philips Norden AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV, Philips AB, Philips Norden AB filed Critical Koninklijke Philips Electronics NV
Priority to DE69826806T priority Critical patent/DE69826806T2/de
Priority to EP98900652A priority patent/EP0913042B1/fr
Priority to JP52923498A priority patent/JP3830535B2/ja
Priority to KR1019980708476A priority patent/KR20000064978A/ko
Priority to PCT/IB1998/000137 priority patent/WO1998038774A2/fr
Publication of WO1998038774A2 publication Critical patent/WO1998038774A2/fr
Publication of WO1998038774A3 publication Critical patent/WO1998038774A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/026—Arrangements for coupling transmitters, receivers or transceivers to transmission lines; Line drivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching

Definitions

  • the invention relates to a line driver, more particularly to a line driver with adaptive output impedance.
  • a line driver is known from the International Patent Application published under No. WO 95/02931.
  • a line driver is an electronic buffer amplifier designed to have an output impedance matched to the characteristic impedance of a transmission line. Transmission lines are widely used for conveying electric signals. To minimise reflections the source and load impedances of the transmission line should be equal to the characteristic impedance of the transmission line.
  • a standard value for video applications is 75 ohms.
  • a buffer amplifier designed to drive a 75 ohm transmission line should have an output impedance of 75 ohms in order to minimise reflections. The buffer sees a load resistance of 75 ohms, i.e. the impedance of the terminated transmission line.
  • Figure 1 shows a first known approach to implement such a buffer.
  • the buffer provides a low-impedance voltage source VS with a series resistor Rs having a value equal to the characteristic impedance of the transmission line TL in order to implement the correct output impedance of the line driver.
  • This type of line driver is often used in digital-to-analog converters (DAC) where the output voltage is controlled by a digital input signal.
  • DAC digital-to-analog converters
  • An disadvantage of this first known structure is that the voltage source VS has to deliver twice the desired output voltage. This becomes a problem where the available supply voltage drops while the signal levels remain unchanged; e.g. a 1.5Vpp output voltage at 3V supply voltage is barely possible.
  • Figure 2 shows a second known approach.
  • the voltage source with series resistance is replaced by a current source CS with a parallel resistance Rs.
  • a current source CS with a parallel resistance Rs In this structure no voltage is lost, but half of the current delivered by the current source CS is wasted in the parallel resistance Rs.
  • This technique is often used in DACs where the output current is digitally controlled. It appears that both known solutions are not attractive since either voltage or current is wasted. Therefore it can be appreciated that a line driver with specified output impedance which matches the impedance of a transmission line and which does not require twice the output voltage or twice the output current is desirable.
  • a line driver comprising: a line driver input terminal for receiving an input signal, - a line driver output terminal for connecting a load, a current mirror having a current gain n, comprising: a first transistor having a main current path inserted between a voltage supply terminal and a reference node, and a second transistor having a main current path inserted between the voltage supply terminal and the line driver output terminal, respective control electrodes of the first transistor and second transistor being connected to receive substantially the same control voltage, a reference resistor coupled to the reference node and having a resistance substantially equal to n times the characteristic resistance of the load, a first operational transconductance amplifier having differential input terminals coupled to the line driver input terminal and to the reference node, and having an output terminal coupled to the respective control electrodes of the first transistor and the second transistor, and a second operational transcon
  • the voltage at the reference resistor is substantially equal to the input voltage.
  • the input signal is converted to a current through the reference resistor.
  • An n times amplified current flows through the load. Since the resistance of the reference resistor is n times the resistance of the load the voltage across the load is equal to the input voltage. No signal voltage is wasted.
  • the supply voltage can be low and should allow only for a proper voltage drop across the second transistor. Moreover, hardly any signal current is wasted, except for a relatively small current which flows through the first transistor and the reference resistor.
  • the second OTA senses any unwanted reflected voltages at the line driver output terminal and converts these reflected voltages to a current which flows from the output terminal of the second OTA into the output terminal of the first OTA.
  • the current flowing into the output terminal of the first OTA in turn generates a differential voltage at the differential input terminals of the first OTA, which voltage has the same amplitude but the reverse sign as the reflected voltage.
  • the reverse reflected voltage is added to the input voltage and thus counteracts the reflected voltage, and the line driver behaves like a source with an output impedance equal to the load impedance.
  • the linearity of the line driver may be increased in an embodiment which further comprises a first bias current source coupled to the reference node, for supplying a first bias current, and a second bias current source coupled to the line driver output, terminal for supplying a second bias current having a value which is substantially equal to n times the value of the first bias current.
  • the accuracy of the resistance of the reference resistor may be insufficient in certain integrating processes.
  • the line driver may further comprise a first bias current source coupled to the reference node, for supplying a first bias current, and a second bias current source coupled to the line driver output terminal, for supplying a second bias current having a value which is substantially equal to n times the value of the first bias current, or alternatively it may comprise means for adjusting the current gain n of the current mirror in response to a low-frequency voltage difference between the line driver input terminal and the line driver output terminal.
  • the voltage difference between the reference node and the line driver output terminal may be used for adjusting the resistance of the reference resistor or for adjusting the current gain of the current mirror.
  • Figure 1 shows a circuit diagram of a conventional line driver with voltage source and series resistor
  • Figure 2 shows a circuit diagram of a conventional line driver with current source and parallel resistor
  • Figure 3 shows a circuit diagram of a first embodiment of a line driver according to the invention
  • Figure 4 shows a circuit diagram of a second embodiment of a line driver according to the invention
  • Figure 5 shows a circuit diagram of a third embodiment of a line driver according to the invention.
  • Figure 6 shows a part of a circuit diagram of an alternative to the third embodiment of Figure 5.
  • FIG. 3 shows the circuit diagram of an embodiment of a line driver according to the invention.
  • the line driver has a line driver input terminal 2, which receives an input signal Vin.
  • the input signal Vin may be a video signal, an audio signal, a telephone signal, a digital data signal etc., provided with an appropriate DC bias.
  • the line driver further has a line driver output terminal 4 for connecting a load 6 via a transmission line TL.
  • the transmission line is optional and can be omitted if so desired.
  • the resistance RL of the load 6 is equal to the characteristic impedance of the transmission line TL, for example 75 ohms.
  • the line driver further comprises a reference node 8 to which a reference resistor 10 is connected.
  • the main current path of a first PMOS transistor Ml is inserted between the reference node 8 and a positive supply terminal 12 and the main current path of a second PMOS transistor M2 is inserted between the line driver output terminal 4 and the positive supply terminal 12.
  • the control electrodes or gates of the transistors Ml and M2 are interconnected and receive the same control voltage.
  • the transistors Ml and M2 thus form a current mirror or current amplifier, i.e. there is a fixed ratio (current gain) between the current through the first transistor Ml and the current through the second transistor M2.
  • a suitable design for example by proportioning the geometries of the first and second transistors Ml and M2 in the ratio l:n, the current ratio can be fixed at the same factor n as mentioned before in relation to the resistances of the reference resistor 10 and the load 6.
  • a typical value for the current gain n is in the range from 10 to 40.
  • a first operational transconductance amplifier (OTA) Al has its non-inverting input terminal 14 coupled to the reference node 8, and has its inverting input terminal 16 coupled to the line driver input terminal 2.
  • the output terminal 18 of the first OTA Al drives the interconnected control electrodes of the transistors Ml and M2.
  • the first OTA Al has a transconductance gm, which means that the current supplied at output terminal 18 is equal to gm times the voltage difference between the non-inverting input terminal 14 and the inverting input terminal 16. Assuming that the gain in the system of OTA Al and transistor Ml is adequate, the signal voltage at the reference node 8 is substantially equal to the input voltage Vin at the line driver input terminal 2.
  • a supply voltage as low as 3V is sufficient to drive 1.5Vpp in a 75 Ohm load.
  • the output impedance of the second transistor M2 is high and would not match with the characteristic impedance RL of the terminated transmission line TL.
  • a second OTA A2 is added to emulate the correct output impedance RL at the line driver output terminal 4.
  • the second OTA A2 is preferably assumed to be equal to the first OTA Al and preferably has the same transconductance gm.
  • the second OTA A2 has its inverting input terminal 20 coupled to the line driver input terminal 2 and its non-inverting input terminal 22 to the line driver output terminal 4.
  • the output terminal 24 of the second OTA A2 is coupled to the output terminal 18 of the first OTA Al.
  • the differential input voltage for the second OTA A2 is zero and the second OTA A2 has no further effect. In the case of reflections, however, the second OTA A2 comes into action. Assuming that the reflected voltage is equal to dVout, the output voltage is now Vout +d Vout and the second OTA A2 sees a differential voltage dVout at its input terminals 20 and 22. In response to this voltage difference the second OTA A2 generates an output current gm*dVout, which can only flow into the output terminal 18 of the first OTA Al.
  • the current imposed at output terminal 18 causes a differential voltage -dVout at the input terminals 14 and 16 of the first OTA Al.
  • the voltage across the reference resistor 10 is now Vin -d Vout and the resulting current il through the reference resistor 10 is copied with a gain n to the line driver output terminal 4.
  • the line driver thus has an output impedance equal to the characteristic impedance RL.
  • Figure 4 shows a modified version of the line driver of Figure 3.
  • a first bias current source 26 is connected to the reference node 8 and provides a bias current Idc through the first transistor Ml.
  • a second bias current source 28 is connected to the line driver output terminal 4 and provides a bias current n*Idc through the second transistor M2. The addition of the two bias current sources 26 and 28 enhances the linearity of the line driver, while slightly more power is consumed.
  • Figure 5 shows an embodiment in which the reference resistor is an electronically variable resistor RV with a resistance control terminal 30 for varying the resistance of the reference resistor 10.
  • the resistance control terminal 30 is driven by an output 32 of a differential amplifier A3, which has one of its inputs, for example a non- inverting input 34, connected to receive the input voltage Vin and the other input, for example an inverting input 36, connected to receive the output voltage Vout.
  • the amplifier A3 preferably has a small bandwidth and tunes the DC resistance Rl of the variable resistor RV to the desired value n*RL. The tuning may be useful where the accuracy of the reference resistor 10 is a problem due to process variations or where a load with a different resistance is connected.
  • the non-inverting input 34 of amplifier A3 may alternatively be connected to receive the voltage at the reference node 8 instead of at the line driver input terminal 2, as indicated in Figure 5 with a dashed line.
  • the current gain n can be tuned by making the current gain of the current mirror M1/M2 variable.
  • Figure 6 illustrates a possible solution for making a variable current gain n.
  • a variable resistor RV2 is connected in series with the source of transistor Ml.
  • the control terminal 40 of the variable resistor RV2 is connected to the output 32 of the differential amplifier A3.
  • the input terminals 34 and 36 of the differential amplifier A3 are connected as shown in Figure 5. Again the alternative connection to the reference node 8 is indicated with a dashed line.
  • a further resistor 42 may be connected in series with the source of transistor M2 for reasons of symmetry.
  • bipolar transistors may be employed, in which case the base, emitter and collector of a bipolar transistor replace the gate, source and drain of a unipolar transistor.
  • the current mirror configuration can be a more sophisticated or elaborated one. Resistors may be inserted in series with the sources of the transistors Ml and M2; cascode transistors may be inserted in series with the drains of the transistors Ml and M2 etc. In principle, any current mirror configuration with a current gain n can be used for this purpose, but it will be appreciated that complex current mirror configurations generally need more supply voltage to operate properly.
  • a line driver comprising a first transistor Ml, a first OTA Al and a reference resistor 10 for converting an input voltage Vin to a first current il through the first transistor Ml.
  • the current i2 flows to a load 6 via a transmission line TL.
  • the transmission line TL is optional.
  • the impedance of the load 6 is equal to the characteristic impedance RL of the transmission line TL.
  • the impedance seen by the line driver is equal to RL.
  • a second OTA A2 counteracts reflected signals dV in the output signal Vout caused by mismatch between the output impedance of the current mirror Ml, M2 and the impedance seen by the line driver.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)

Abstract

Un circuit d'attaque de ligne comprend un premier transistor (M1), un premier amplificateur opérationnel à transconductance (A1) et une résistance de référence (10), de façon à transformer une tension d'entrée (Vin) en un premier courant (i1) traversant le premier transistor (M1). Un second courant i2=n*i1 traverse un second transistor (M2) qui forme un miroir de courant 1:n avec le premier transistor (M1). Le courant i2 se dirige vers une charge (6), si nécessaire via une ligne de transmission (TL). L'impédance de la charge (6) est égale à l'impédance caractéristique (RL) de la ligne de transmission (TL). L'impédance vue par le circuit d'attaque de ligne est donc égale à RL. Un second amplificateur opérationnel à transconductance (A2) s'oppose aux signaux réfléchis dans le signal de sortie (Vout) du fait du décalage entre l'impédance de sortie du miroir de courant (M1, M2) et l'impédance vue par le circuit d'attaque de ligne.
PCT/IB1998/000137 1997-02-25 1998-02-02 Circuit d'attaque de ligne a impedance de sortie adaptative Ceased WO1998038774A2 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE69826806T DE69826806T2 (de) 1997-02-25 1998-02-02 Leitungstreiber mit adaptiver ausgangsimpedanz
EP98900652A EP0913042B1 (fr) 1997-02-25 1998-02-02 Circuit d'attaque de ligne a impedance de sortie adaptative
JP52923498A JP3830535B2 (ja) 1997-02-25 1998-02-02 適応出力インピーダンスを有するラインドライバ
KR1019980708476A KR20000064978A (ko) 1997-02-25 1998-02-02 적응 출력 임피던스를 가지는 라인 구동기
PCT/IB1998/000137 WO1998038774A2 (fr) 1997-02-25 1998-02-02 Circuit d'attaque de ligne a impedance de sortie adaptative

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP97200525.0 1997-02-25
PCT/IB1998/000137 WO1998038774A2 (fr) 1997-02-25 1998-02-02 Circuit d'attaque de ligne a impedance de sortie adaptative

Publications (2)

Publication Number Publication Date
WO1998038774A2 true WO1998038774A2 (fr) 1998-09-03
WO1998038774A3 WO1998038774A3 (fr) 1998-11-26

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PCT/IB1998/000137 Ceased WO1998038774A2 (fr) 1997-02-25 1998-02-02 Circuit d'attaque de ligne a impedance de sortie adaptative

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1039702A1 (fr) * 1999-03-25 2000-09-27 Nortel Networks Limited Adaptation d'impédance pour circuits d'attaque de lignes
EP1122922A1 (fr) * 2000-02-04 2001-08-08 STMicroelectronics, Inc. Circuit d'attaque de ligne à impédance de sortie adaptative

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW239239B (fr) * 1993-07-14 1995-01-21 Philips Electronics Nv
US5585763A (en) * 1995-03-30 1996-12-17 Crystal Semiconductor Corporation Controlled impedance amplifier

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1039702A1 (fr) * 1999-03-25 2000-09-27 Nortel Networks Limited Adaptation d'impédance pour circuits d'attaque de lignes
US6665399B1 (en) 1999-03-25 2003-12-16 Nortel Networks Limited High-efficiency line driver
EP1122922A1 (fr) * 2000-02-04 2001-08-08 STMicroelectronics, Inc. Circuit d'attaque de ligne à impédance de sortie adaptative

Also Published As

Publication number Publication date
WO1998038774A3 (fr) 1998-11-26

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