WO1999014896A1 - Atm repeater - Google Patents
Atm repeater Download PDFInfo
- Publication number
- WO1999014896A1 WO1999014896A1 PCT/JP1998/004195 JP9804195W WO9914896A1 WO 1999014896 A1 WO1999014896 A1 WO 1999014896A1 JP 9804195 W JP9804195 W JP 9804195W WO 9914896 A1 WO9914896 A1 WO 9914896A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- information
- transfer destination
- search
- associative memory
- hop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/02—Topology update or discovery
- H04L45/10—Routing in connection-oriented networks, e.g. X.25 or ATM
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/742—Route cache; Operation thereof
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
- H04L45/7453—Address table lookup; Address filtering using hashing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
- H04L49/309—Header conversion, routing tables or routing tags
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5619—Network Node Interface, e.g. tandem connections, transit switching
- H04L2012/562—Routing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5665—Interaction of ATM with other protocols
- H04L2012/5667—IP over ATM
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
Definitions
- the present invention has been applied to, for example, computer networks and LANs.
- the present invention relates to a relay device provided for performing a routing process of a packet, and more particularly to an ATM relay device using an ATM switch.
- a relay device generally called a router is:
- a hop-no-hop transfer mode is provided as one of the modes for routing a packet.
- the IP address is input to the network layer. Extract the destination IP address and control information from the packet data, determine the destination based on the extracted destination IP address and control information, and respond to this destination In this mode, a bucket is sent to the line to be processed. Conventionally, this processing is realized by software processing by a processor.
- FIG. 1 is a circuit block diagram showing a schematic configuration of a conventional ATM relay device.
- output line information (Next hop) is stored in advance in association with the destination IP address, and the destination IP address is stored by processor 1 in advance.
- the IP subnetwork or host to which the dress belongs is searched, and the output line connected to the destination IP subnetwork or host is determined. Be done.
- the processor 1 controls the ATM switch 3 so that the packet is transferred to this output line, and the received packet is transmitted by the SAR 2 to the ATM cell. Then, the packet is transmitted from the ATM switch 3 to the output line.
- the present invention is applied to a network layer.
- the node is routed using at least associative memory (content addressable memory).
- ⁇ A transfer destination search circuit composed of an air circuit is provided, and the transfer destination search circuit extracts the header information from the bucket buckets transferred from the upstream line. A process for searching for a transfer destination based on this header information is performed.
- the extraction of the header information and the search processing of the transfer destination related to the hop-by-hop transfer are performed by the hardware processing. For this reason, the speed of hop-by-hop transfer can be increased as compared with a conventional apparatus that performs the same processing by software processing by a processor. In addition, since there is no need to prepare a high-speed processor, it is possible to reduce the cost of the apparatus.
- the present invention further comprises a processor for performing a transfer destination search for hop-by-hop transfer by software, wherein the transfer destination search circuit further includes a bucket. If the transfer destination information corresponding to the header information extracted from the information cannot be obtained, the above-mentioned header information is given to the above-mentioned processor, and the transfer destination check by software is performed. It is characterized by performing search processing.
- the process is performed.
- the above transfer destination is searched by software processing of the server.
- header information extraction and transfer destination search processing related to hop-by-hop transfer are performed by the hardware processing of the transfer destination search circuit and by the processor. This is done in cooperation with software processing.
- transfer destination information related to relatively frequent communication is registered in the transfer destination search circuit, and transfer destination information related to infrequent communication is registered in the processor.
- Buckets related to rarely arriving communications can be transferred by software processing of the client.
- the present invention provides an associative memory for reading out pointer information corresponding to header information extracted from a node and a header in a transfer destination search circuit;
- a compression search memory which is compressed by a predetermined compression algorithm such as a function and reads out pointer information corresponding to the compression information. Then, the associative memory is accessed first to search for pointer information corresponding to the header information, and the header is accessed by accessing the associative memory. If the pointer information corresponding to the information could not be retrieved, it is also possible to access the compressed retrieval memory and retrieve the corresponding pointer information. .
- associative memory has a high operation speed, but has a small storage capacity and is expensive.
- a relatively inexpensive and large-capacity SRAM or DRAM is used for the compressed search memory. Therefore, the associative memory does not store the transfer destination information of all the communications that are expected to be transferred by hop-by-hop, and relates to some communications that are particularly frequently communicated. By storing only the transfer destination information and storing the remaining information in the compressed search memory, the storage capacity of the associative memory can be reduced to reduce the cost of the device.
- the associative memory when reading out pointer information from the associative memory in the transfer destination search circuit, first, a plurality of pieces of predetermined information included in the header information are used as key information.
- the associative memory is accessed, and when the pointer information corresponding to the access is not retrieved, the information of the plurality of information included in the first information is obtained. Access the associative memory with some information as key information That this and also features a record, Ru.
- Figure 1 is a block diagram showing the schematic configuration of a conventional ATM repeater. It is a mouth drawing.
- FIG. 2 is a block diagram showing an embodiment of the ATM relay device according to the present invention.
- FIG. 3 is a block diagram showing a configuration of a transfer destination search circuit in the relay device shown in FIG.
- FIG. 4 is a diagram showing an example of the configuration of the associative memory in the transfer destination search circuit shown in FIG.
- FIG. 5 is a diagram showing an example of the configuration of a HASH search pointer table in the transfer destination search circuit shown in FIG.
- FIG. 6 is a diagram showing an example of the configuration of a forwarding table in the transfer destination search circuit shown in FIG.
- FIG. 7 is a flowchart showing an IP address search procedure by associative memory in the transfer destination search circuit shown in FIG. 3 and its contents.
- FIG. 8 is a flow chart showing an IP address search procedure using a HASH search pointer table in the transfer destination search circuit shown in FIG. 3 and its contents.
- FIG. 2 is a circuit block diagram showing one embodiment of the ATM relay device according to the present invention.
- the ATM repeater of this embodiment includes a processor 11, a cell splitting / assembling unit (SAR) 13, an ATM switch 14, A transfer destination search circuit 12 is provided in addition to the frame memory 15. Since this transfer destination search circuit 12 is all composed of hardware, as shown in FIG. 3, an associative memory 21, a HASH search pointer table 22, and a It is composed of a forwarding table 23, a search control section 24 and a controller.
- SAR cell splitting / assembling unit
- the associative memory 21 stores in advance header information and pointer information relating to communication with relatively high communication frequency.
- Fig. 4 shows an example of the stored information.
- the destination IP address, source IP address, destination port number, and source port number that constitute the header information are searched. It is stored as a key, and pointer information is stored in association with this header information. This pointer information is used as a key when searching a forwarding table 23 described later.
- the associative memory 21 performs a search using the input header information as a search key, and if the matching header information is stored, the associative memory 21 corresponds to the header information. It has a search function to output pointer information.
- the HASH search pointer table 22 is used when searching for the transfer destination by the HASH function.For example, the destination IP address and the Pointer information is stored. FIG. 5 shows an example of the stored information.
- FIG. 6 shows an example of the stored information.
- the forwarding information includes VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier). And QOS flag (Quality of Service Flag) are stored.
- the search control unit 24 is composed of, for example, a logic circuit, and stores the IP address once stored in the frame memory 15. Extracts header information from the kit data. Then, based on the extracted header information, the associative memory 21 and the HASH search pointer table 22 are selectively accessed to access the corresponding pointer information. Search for. In addition, based on the searched pointer information, the for- ding table 23 is accessed to search for the corresponding for- ding information.
- the processor 11 has a hop-by-hop transfer destination search function by software processing as in the past, and the processor 11 has a transfer destination search circuit 12. If the transfer destination could not be searched, execute the above search function to search for the transfer destination.
- the transfer destination search circuit 12 uses the search control unit 24 to extract the header information from the IP packet data. Extract. Then, the search control unit 24 determines the destination IP address, the source IP address, the destination port number, and the source port number contained in the header information. Using the number as a key, search for forwarding information (forwarding information) as follows.
- FIG. 7 is a flowchart showing the operation procedure and operation contents.
- the search control unit 24 searches for all information included in the header information, that is, the destination IP address, the source IP address, the destination port number, and The source port number is input to the associative memory 21.
- the associative memory 21 searches for header information that matches all of these pieces of information, and finds the header information that matches. The corresponding pointer information is returned to the search controller 24.
- step S71 the process proceeds from step S71 to step S76, where the search control unit 2 4 accesses the forwarding table 23 based on the pointer information and obtains the corresponding forwarding information (VPI, VCI, Q ⁇ S flag, etc.). .
- the SAR 13 and the ATM switch 14 operate in accordance with the forcing information, and the IPs stored in the frame memory 15 are thereby operated.
- the packet data is divided into cells by the SAR 13 and then transmitted from the ATM switch 14 to the output line.
- the ATM switch 14 provides the information for cut-through transfer. After that, cells of the same packet arriving from the line on the upstream side are transferred through this path through this path.
- step S72 in which the destination IP address and the source IP address of the information included in the header information are included. Address, enter the destination IP address and the source IP address in the associative memory 21.
- the associative memory 21 searches for the matching header information and searches for a match.
- the pointer information corresponding to the obtained header information is returned to the search control unit 24.
- the key information is reduced, and the search is performed again using the associative memory 21.
- the process moves from step S73 to step S76, and as described above, the coding table is changed. 2 Acquire the corresponding forging information from 3rd party.
- the associative memory 21 stores the pointer information corresponding to the header information with a higher priority according to a predetermined priority. Is returned to the search control unit 24.
- step In S74 the search control unit 24 further reduces the key to only the destination IP address, inputs this destination IP address to the associative memory 21 and sets the associative memory.
- the library 21 searches for the matching header information and returns the pointer information corresponding to the matching header information to the search control section 24. If matching header information can be searched, the corresponding forwarding information from the coding table 23 in step S76 is obtained. Get information.
- the matching header information could not be retrieved even after that, it matches the one that was masked from the MSB side of the destination IP address in consideration of the subnet mask. Enter the header information again in the associative memory 21 and search. Then, if a matching header IIB information is found, in step S76, the corresponding forwarding information is obtained from the forwarding table 23.
- FIG. 8 is a flowchart showing the operation procedure and operation contents.
- a HASH function is a compression algorithm that maps a 32-bit destination IP address, for example, to a sequence of fewer bits than the corresponding 32 bits. It is a function.
- the destination IP address masked by the mask length is input to the HASH function in step S82.
- step S83 the destination IP address of the HASH search pointer table 22 shown by the output of this HASH function is referred to.
- step S84 if the destination IP address stored in the HASH search pointer table 22 matches the masked destination IP address, step S84
- the process proceeds to step S87, where the HASH detection is performed.
- the corresponding pointer information stored in the search pointer table 22 is read out, and the focusing table 23 is activated using the pointer information as a key. Then, obtain the corresponding foraging information (VPI, VCI, QOS flag, etc.).
- the subnet mask is set. In consideration of the mask, the mask length is shortened by 1 bit in step S85, and the destination IP address is reduced by the shortened mask length in step S81. Mask from the MSB side force. Then, the masked destination IP address is input to the HASH function in step S82, and the HASH search pointer table 2 indicated by the output of the HASH function is input. Refer to the second destination IP address. Then, if the destination IP address stored in the HASH search pointer table 22 and the masked destination IP address before input to the HASH function match. As described above, the corresponding forwarding information is obtained from the forwarding table 23.
- the mask length is further reduced by one bit in step S85, and the further shortened mask causes the destination to be reduced. Re-mask the IP address and enter it into the HASH function. Then, referring to the destination IP address of the HASH search pointer table 2 2 indicated by the output of the HASH function, the masked destination IP before inputting to the HASH function. If a destination IP address that matches the address is found, the corresponding fowarding table from 23 Get logging information. However, if this is not found, the mask length is further shortened and the above HASH search operation is repeated.
- step S 8 6 Move to the processing queue of processor 11 from this, and leave it to the search by the software processing of processor 11.
- the processor 11 is provided with the transfer destination search circuit 12 constituted by hardware in addition to the processor 11. Then, in the transfer destination search circuit 12, header information is extracted from the received IP packet data, and then the header information is used as a key to associative memo. If a search is performed using the Hash search pointer 21 and the corresponding foregrounding information cannot be obtained by the search of the associative memory 21, then the pointer table 2 for the HASH search is used. Then, a search using the HASH function is performed using (2), and if the forwarding information can be obtained by these searches, the above information is obtained based on the forwarding information. IP no. Performs a hop-by-hop transfer of the packet data.
- the operation of extracting header information and the operation of searching for coding information related to the hop-by-hop transfer are performed by hardware processing of the transfer destination search circuit.
- the speed of the hop-by-hop transfer can be increased as compared with the case where the above operations are executed by the software processing of the processor 11. Can be done.
- the ability to search by associative memory 21 and the HASH search boy By using the search with the counter table 22 together, the memory of the associative memory 21 is compared with the case where all the searches are performed only by the associative memory 21. The capacity can be reduced, and thereby the cost of the device can be reduced. In this case, the information related to the most frequently used communication is searched by the associative memory 21 and the other information related to the communication is searched by the HASH search pointer 22. With such a configuration, particularly high-speed hop-by-hop transfer can be realized for communication with high communication frequency.
- a search is first performed using all information included in the header information as a key, and the corresponding information is searched. If it is not possible, the key information of each piece of information included in the above header information is gradually reduced, and the search is performed. Therefore, the more frequently the communication, the more information in the header information is used to quickly and reliably search for the transfer destination.
- the packet can be transferred.
- the processor 11 determines whether the forwarding information cannot be obtained as a result of the search using the associative memory 21 and the pointer table 22 for the HASH search. If the forwarding information cannot be obtained as a result of the search using the associative memory 21 and the pointer table 22 for the HASH search, the processor 11 The destination IP address is not entered in the associative memory 21 and the HASH search pointer table 22 because the search by software processing is performed. Although high-speed transfer cannot be performed even with extremely low-rate communication, hop-by-hop transfer can be performed without fail. Also, associating the destination IP address of all communications with memory 21 and HASH search Since there is no need to enter an entry in the pointer table 22 for use, the configuration of the associative memory 21 and the pointer table 22 for HASH search can be simplified.
- the present invention is not limited to the above embodiment.
- a search for the transfer destination is first performed by the transfer destination search circuit 12, and the search cannot be performed by the transfer destination search circuit 12.
- the search by the client 11 is left to the search.
- the waiting queue in the transfer destination search circuit 12 reaches a predetermined amount or more, a part of the queue is sent to the processor 11 to search for the transfer destination. It may be configured in this way. In this way, the search processing by the transfer destination search circuit 12 and the search processing by the port processor 11 are performed in parallel when the traffic is increased. As a result, more efficient hop-by-hop transfer processing can be realized.
- circuit configuration of the transfer destination search circuit, the transfer destination search processing procedure and the processing contents in the transfer destination search circuit can be variously modified without departing from the gist of the present invention.
- the network layer can be used.
- a transfer configured by a hardware circuit using at least associative memory.
- a forward search circuit is provided, and the transfer destination search circuit is used to transfer data from the upstream line.
- High-speed processing is achieved by extracting header information from the transmitted bucket and performing a process of searching for a destination based on the header information. It is possible to realize high-speed hop-by-hop transfer without using a loader, thereby providing a low-cost and high-performance ATM relay device.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Description
Claims
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP98943030A EP0939518A4 (en) | 1997-09-17 | 1998-09-17 | Atm repeater |
| US09/308,133 US6580707B1 (en) | 1997-09-17 | 1998-09-17 | ATM repeater using hardware implemented transfer destination searching to reduce processor load |
| CA002271879A CA2271879C (en) | 1997-09-17 | 1998-09-17 | Atm repeater |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9/252161 | 1997-09-17 | ||
| JP25216197A JPH1198143A (ja) | 1997-09-17 | 1997-09-17 | Atm中継装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1999014896A1 true WO1999014896A1 (en) | 1999-03-25 |
Family
ID=17233342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP1998/004195 Ceased WO1999014896A1 (en) | 1997-09-17 | 1998-09-17 | Atm repeater |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6580707B1 (ja) |
| EP (1) | EP0939518A4 (ja) |
| JP (1) | JPH1198143A (ja) |
| CA (1) | CA2271879C (ja) |
| WO (1) | WO1999014896A1 (ja) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000341275A (ja) * | 1999-05-26 | 2000-12-08 | Nec Corp | フレーム処理装置及びその処理方法 |
| KR100579139B1 (ko) * | 1999-12-24 | 2006-05-12 | 한국전자통신연구원 | 비동기전송모드 기반의 스위칭 시스템을 위한 고속 인터넷프로토콜 패킷 포워딩 장치 및 그 방법과 그를 이용한 라우팅 시스템 |
| GB2368228B (en) * | 2000-10-18 | 2003-07-23 | 3Com Corp | Network unit with address cache for frequently occuring network conversations |
| US20020181463A1 (en) * | 2001-04-17 | 2002-12-05 | Knight Brian James | System and method for handling asynchronous transfer mode cells |
| US7167471B2 (en) * | 2001-08-28 | 2007-01-23 | International Business Machines Corporation | Network processor with single interface supporting tree search engine and CAM |
| US7362744B2 (en) * | 2002-08-15 | 2008-04-22 | International Business Machines Corporation | Database management system and method of using it to transmit packets |
| JP4195264B2 (ja) * | 2002-09-09 | 2008-12-10 | 株式会社アイピースクエア | 情報処理装置及び情報処理方法 |
| US7257082B2 (en) * | 2003-03-31 | 2007-08-14 | Ixia | Self-similar traffic generation |
| US7496688B2 (en) * | 2004-01-30 | 2009-02-24 | Ixia | Label switched data unit content evaluation |
| JP4564819B2 (ja) * | 2004-10-19 | 2010-10-20 | 日本電気株式会社 | データ送信装置、データ送信方法、データ送信プログラムおよび記録媒体 |
| CN100477658C (zh) * | 2005-06-08 | 2009-04-08 | 武汉虹信通信技术有限责任公司 | 通信服务器并发处理大数据量的方法 |
| CN100446508C (zh) * | 2005-12-30 | 2008-12-24 | 华为技术有限公司 | 一种实现报文转发的装置及方法 |
| JP4978025B2 (ja) * | 2006-02-24 | 2012-07-18 | 株式会社日立製作所 | ポインタの圧縮・伸張方法、これを実行するプログラム、及び、これを用いた計算機システム |
| US8472437B2 (en) * | 2010-02-15 | 2013-06-25 | Texas Instruments Incorporated | Wireless chip-to-chip switching |
| US20130343181A1 (en) * | 2012-06-21 | 2013-12-26 | Jonathan Stroud | Systems and methods of data processing using an fpga-implemented hash function |
| US20130343377A1 (en) * | 2012-06-21 | 2013-12-26 | Jonathan Stroud | Hash-based packet distribution in a computer system |
| US10776535B2 (en) | 2016-07-11 | 2020-09-15 | Keysight Technologies Singapore (Sales) Pte. Ltd. | Methods, systems and computer readable media for testing network devices using variable traffic burst profiles |
| US11388078B1 (en) | 2019-06-10 | 2022-07-12 | Keysight Technologies, Inc. | Methods, systems, and computer readable media for generating and using statistically varying network traffic mixes to test network devices |
| WO2024029092A1 (ja) * | 2022-08-05 | 2024-02-08 | 日本電信電話株式会社 | 通信装置、通信方法および通信プログラム |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06261078A (ja) * | 1993-03-03 | 1994-09-16 | Hitachi Ltd | テーブル検索方法及びルータ装置 |
| JPH0730587A (ja) * | 1993-07-14 | 1995-01-31 | Hitachi Ltd | フレーム中継制御方法、及びその装置 |
| JPH08102744A (ja) * | 1994-09-30 | 1996-04-16 | Kawasaki Steel Corp | 交換機、交換方法、およびネットワークシステム |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0689748B1 (en) | 1993-03-20 | 1998-09-16 | International Business Machines Corporation | Method and apparatus for extracting connection information from protocol headers |
| US5467349A (en) * | 1993-12-21 | 1995-11-14 | Trw Inc. | Address handler for an asynchronous transfer mode switch |
| US6088356A (en) * | 1997-06-30 | 2000-07-11 | Sun Microsystems, Inc. | System and method for a multi-layer network element |
| US6118760A (en) * | 1997-06-30 | 2000-09-12 | Sun Microsystems, Inc. | Management of entries in a network element forwarding memory |
| US6034958A (en) * | 1997-07-11 | 2000-03-07 | Telefonaktiebolaget Lm Ericsson | VP/VC lookup function |
-
1997
- 1997-09-17 JP JP25216197A patent/JPH1198143A/ja active Pending
-
1998
- 1998-09-17 US US09/308,133 patent/US6580707B1/en not_active Expired - Fee Related
- 1998-09-17 WO PCT/JP1998/004195 patent/WO1999014896A1/ja not_active Ceased
- 1998-09-17 EP EP98943030A patent/EP0939518A4/en not_active Withdrawn
- 1998-09-17 CA CA002271879A patent/CA2271879C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06261078A (ja) * | 1993-03-03 | 1994-09-16 | Hitachi Ltd | テーブル検索方法及びルータ装置 |
| JPH0730587A (ja) * | 1993-07-14 | 1995-01-31 | Hitachi Ltd | フレーム中継制御方法、及びその装置 |
| JPH08102744A (ja) * | 1994-09-30 | 1996-04-16 | Kawasaki Steel Corp | 交換機、交換方法、およびネットワークシステム |
Non-Patent Citations (2)
| Title |
|---|
| IEICE TECHNICAL REPORT, DENSHI JOUHOU TSUUSHIN GAKKAI, JP, 15 March 1996 (1996-03-15), JP, pages 175, XP002920271, ISSN: 0913-5685 * |
| See also references of EP0939518A4 * |
Also Published As
| Publication number | Publication date |
|---|---|
| US6580707B1 (en) | 2003-06-17 |
| EP0939518A1 (en) | 1999-09-01 |
| EP0939518A4 (en) | 2005-07-20 |
| CA2271879C (en) | 2003-08-12 |
| JPH1198143A (ja) | 1999-04-09 |
| CA2271879A1 (en) | 1999-03-25 |
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