WO1999044356A2 - Camera de television a haute definition et formateur - Google Patents

Camera de television a haute definition et formateur Download PDF

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Publication number
WO1999044356A2
WO1999044356A2 PCT/US1999/004196 US9904196W WO9944356A2 WO 1999044356 A2 WO1999044356 A2 WO 1999044356A2 US 9904196 W US9904196 W US 9904196W WO 9944356 A2 WO9944356 A2 WO 9944356A2
Authority
WO
WIPO (PCT)
Prior art keywords
camera
formatter
digital
video signal
flexible
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1999/004196
Other languages
English (en)
Other versions
WO1999044356A3 (fr
Inventor
John V. Weaver
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LIBERTY IMAGING Inc
Original Assignee
LIBERTY IMAGING Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LIBERTY IMAGING Inc filed Critical LIBERTY IMAGING Inc
Priority to KR1020007009553A priority Critical patent/KR20010041419A/ko
Priority to JP2000533998A priority patent/JP2002536851A/ja
Priority to EP99909635A priority patent/EP1210816A4/fr
Publication of WO1999044356A2 publication Critical patent/WO1999044356A2/fr
Anticipated expiration legal-status Critical
Publication of WO1999044356A3 publication Critical patent/WO1999044356A3/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0125—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level one of the standards being a high definition standard
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/55—Optical parts specially adapted for electronic image sensors; Mounting thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/80—Camera processing pipelines; Components thereof
    • H04N23/81—Camera processing pipelines; Components thereof for suppressing or minimising disturbance in the image signal generation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
    • H04N7/012—Conversion between an interlaced and a progressive signal

Definitions

  • This invention relates to television cameras and related equipment that capture images in high-definition form.
  • Electronic video cameras provide a method of converting scenes, objects, movie film, actors, etc., to electronic video signals that may be viewed, recorded, transformed, and transmitted to one or multiple receiver sites in a realistic manner.
  • the unique architecture of the present invention provides an improved capability to capture and manipulate visual information so that it may be used by television stations to originate broadcast-quality (contribution quality) images in full motion and full color.
  • the present invention includes a camera architecture that is capable of progressively scanning the scene, providing a complete picture for each frame of video output. Progressive scanning provides several advantages, such as: fewer motion artifacts associated with the scanning process, and a video output that is directly compatible with computer manipulation techniques.
  • the present invention increase the utility of the equipment associated with the production and distribution of high-definition television ("HDTV").
  • Such equipment may include, but is not limited to, high-definition cameras, tape recorders, switching units, special effect generators, and compression engines.
  • the increase in utility resides in the ability of the equipment to accept and distribute an electrical signal representing a HDTV picture in any of a variety of industry-accepted formats and convert that signal to a common format.
  • the internal signal of the camera may be in a particular format, but the user might need another format.
  • the present invention includes a programmable formatter that may convert a video signal to user specified format (or formats).
  • the present invention includes a high definition digital television camera comprising: an optical sensor that generates a digital output; a front-end electronics section that receives and processes the digital output from the optical sensor and produces a digital video signal; a back-end electronics section that receives and processes the digital video signal that is generated by the front- end electronics section and produces a format specified by the camera user, wherein the back-end electronics section includes a flexible formatter capable of converting the digital video signal to a plurality of different formats.
  • the flexible formatter may comprise one or more field programmable gate array (s).
  • the field programmable gate array may convert the digital video signal from progressive to interlaced format.
  • the flexible formatter may include a storage media for storing the digital video signal during conversion.
  • the flexible formatter may further include a digital to analog converter for converting the digital video signal to analog format.
  • the flexible formatter may further comprise a programming port for receiving control data that controls the formatter and determines the formats for the digital video signal.
  • the flexible formatter may comprise a general purpose video processor.
  • the flexible formatter may further comprise a storage media for storing the digital video signal during conversion.
  • the flexible formatter may further comprise a read only memory device for storing program code that controls the video processor and controls the conversion of the digital video signal.
  • the flexible formatter that includes a video processor may also further comprise a digital to analog converter for converting the digital video signal to analog format.
  • the camera's optical sensor may include an optical lens and optical filters.
  • the optical sensor may include an optical prism assembly. The optical sensor may be controlled by control signals that are provided by an optical decoder.
  • the camera's front-end electronics section may include a logic circuit that corrects for defective pixels.
  • the front-end electronics section may include a logic circuit that corrects for shading of the video signal .
  • the camera may include a digital accumulator that provides automatic gain control.
  • the camera may also comprise programmable random-access memories for compensating for non-linearities in the optical sensors and for transforming the color of the sensor' s digital output.
  • Figure 1 is a block diagram illustrating the optical and initial electrical portions of the invention.
  • Figure 2 is a block diagram showing the details of the front-end electronics.
  • Figure 3 is a block diagram showing details of the architecture for the back-end electronics of the camera and its relationship with the studio equipment.
  • Figure 4 shows the invention implemented using a field-programmable logic array.
  • Figure 5 shows an alternative method for the implementation of the invention using one or more processors.
  • Fig. 1 illustrates the optical and initial electrical portions of the invention.
  • the front-end optics and electronics are used with all versions of cameras produced with this unique architecture.
  • Light from the scene enters the lens 1 that is designed for high-quality video production.
  • the lens has three servo-controlled settings: iris, focus, and zoom (effective focal length).
  • Input commands from the operator or the camera control unit (CCU) can change these three settings.
  • the control signals are received on the system control bus 16 and decoded by the optical decoder electronics 10. Signals from the optical decoder electronics 10 then control the three lens settings through line 13.
  • Behind the lens are provisions for two sets of filter wheels 2 and 3, a quarter-waveplate 4, and a low- pass spatial optical filter 5.
  • the filters in the first wheel 2 can be used for color correction, while those in the second wheel 3 are neutral density filters to reduce the light intensity to the photosensors in bright sunlight conditions.
  • the quarter-wave plate and the spatial low-pass filter reduce video artifacts (moire patters) that would be generated under certain conditions by the tessilated structure of the photosensors.
  • the present invention includes an optical prism assembly 6 that serves two purposes: it splits the incoming light into three beams directed at the photosensors 7, 8, and 9, and it contains dichotic filters on its inner two surfaces to provide the correct spectral response of the photosensors.
  • the dichotic filters are arranged such that red light from the scene impinges on photosensor 7, blue light impinges on photosensor 9, and green light passes through the two filters to impinge on photosensor 8.
  • Photosensors 7, 8, and 9 are pixel arrays of CMOS devices with structures similar to memories, which may be addressed to scan over the device area by address lines 12, also controlled by the decoded electronics 10.
  • the control electronics also provide the photosensor chips with signals that control the black level, the gain of the sensor (its sensitivity to light), and the integration time of the sensor.
  • CMOS photosensors As the optically active section of the CMOS devices are scanned, digitized signals are generated by the CMOS photosensors. The digital value produced at the output of each photosensor is proportional to the light intensity at each pixel.
  • the three photosensors provide three digital outputs (nominally 10 to 12 bits each, for a total of 30 to 36 bits) that represent the color tristimulus video signals.
  • the outputs of the sensors are directed to the front- end electronics section 11 that performs the basic signal processing necessary to provide a video signal of professional quality. Details of front-end electronics are given in Fig. 2.
  • the front-end electronics may be used in all versions of cameras designed with this unique architecture.
  • the order of the signal path through the processing electronics may change slightly depending on the application of the camera (e.g., medical imaging, entertainment, movie films, etc.).
  • the tristimulus signals 15 from the photosensors (shown in Fig. 1 as photosensors 7, 8, and 9) are initially presented to the defective-pixel correction logic 201.
  • This logic block modifies the value of any pixel that is designated defective. Pixels are designated defective by tests performed at the time of manufacture of the camera, or during testing routines after the camera system is deployed.
  • a non- volatile memory 202 contains the address of each defective pixel.
  • the logic interpolates the defective pixel's value from the value of the pixel on either side of the defective one. In this manner, a defective pixel assumes the luminance that is the average along the horizontal line of nearest neighboring pixels.
  • Video from the defective pixel logic is presented to the shading correction logic 203.
  • the shading correction ensures that the signal out of this block has a zero value when the light level into the camera is zero. It removes the Offsets' or systematic errors that may impair the dynamic range of the video signal.
  • the shading correction unit subtracts a constant, prestored value from each of the digital inputs presented to the shading correction unit. The prestored values are read into the correction unit over the system control bus 16.
  • the automatic gain control (“AGC”) signal generator 204 provides a digital output that is proportional to the illumination in the central portion of the video picture.
  • the AGC functions as a simple digital accumulator which sums the outputs of the red, green, and blue channels over a set of pixels on a frame-by-frame basis.
  • the digital AGC data is accumulated over time (an integration period) to provide a measure of the general illumination of a scene.
  • the data from the output of the AGC is used by other sections of the camera, especially by the lens section to control the iris of the lens. In this manner, the video output of the camera stays relatively constant with changes in illumination.
  • the weighting of the AGC output can be programmed to meet different demands. For example, the bottom of the frame can contribute more heavily than the top of the frame when scanning a scene where the ground illumination changes more rapidly than the sky illumination.
  • the non-linearity compensation 205 may be programmable random-access memory
  • RAM random access memory
  • the number of bits (nominally 10 or 12) is the same for input and output.
  • the data in the RAM determine the transfer function between the digital input and the digital output for each of the three colors.
  • the data in the RAM are provided by the system control bus and compensates for non-linearities that are inherent in the photosensors.
  • the color transformation matrix 206 permits the exchange of any color for any other color.
  • the color transformation matrix operates on equal number of bits for both input and output (typically 30 or 36). However, the color transformation RAM permits any two colors to affect a third color. In this manner, any color at its input (R, G, B') can be recapped to any other color (R", G", B").
  • the present invention allows for the introduction of non-linearities in the optical signal in order to improve picture quality. This introduction is accomplished by the gamma correction RAM.
  • the gamma correction RAM 207 is similar in construction to the non-linearity compensation RAM.
  • the gamma correction RAM holds data that permit the operator to adjust the input and output black levels, the maximum gain of the gamma curve at black, and the overall gamma value.
  • the transfer curve that defines the input versus output for the gamma correction is calculated using an exponential relationship involving the number of bits (typically 10 or 12), the black level, and the clamp level.
  • Finite Impulse Response provides a method to keep out-of-band signals from being propagated to the output of the camera.
  • the finite response filter is based on a multiply-accumulate function to prevent artifacts created by the digital processing from propagating further in the system.
  • the response characteristic of the FIR filter is determined by coefficients loaded into the multiplier registers by the control bus.
  • Fig. 3 shows details of the architecture for the back-end electronics of the camera and its relationship with the studio equipment.
  • the back-end electronics implements the optional features that provide for flexibility of use and minimize the risk of obsolescence for the camera equipment.
  • the incoming video signal 301 is routed to the format converter 302.
  • the format converter consists of a large programmable-logic array and associated memory that can convert the camera's internal parallel format to other formats that are more compatible with the production, post-production, and transmission standards. From the format converter, the video signal can be recorded or transmitted via either of two down-links: wireless or fiber-optic cable.
  • the camera is fitted with a digital data recorder 303 that can record the audio and video information.
  • a digital data recorder 303 that can record the audio and video information.
  • the use of a high-density, low-cost media such as magnetic or optical tape, disks, or solid state recording technology, provides a method to record and play back the audio and video information captured by the camera.
  • An alternative to the direct recording of video signals is the transmission of the signals through a radio frequency (“RF") wireless telemetry down-link 314 to a control room.
  • RF radio frequency
  • a pair of short-range wireless transceivers 304, 308 provide a digital link between the camera and ⁇ if necessary — the studio equipment and between the studio's camera control unit 307 and the camera. Because of the high data rate for the camera-to-studio transmission, the carrier frequency of the link is typically in the 2.4 GHZ band (or higher frequency) and typical operating power is on the order of .25 Watt to 1 Watt, the wireless link is intended for short-haul applications such as sports events, real-time news broadcasts, and studio applications where a cable is not desired.
  • the wireless transceiver also provides for the studio camera control unit to up-link data from the studio camera control unit 307 to the camera.
  • the fiber-optic interface between the camera 305 and the control room 309 is intended for camera to control room communications in studios where cable may be accommodated. Digital fiber-optic connections offer a wide bandwidth for video down-link with high reliability of transmission.
  • the fiber-optic link 359 also supports the transmission of the commands from the studio's camera control unit 307 on the up-link.
  • the local camera control unit 306 is attached to the camera and generates the signals that are carried on the system control bus 16 and preset the mode of operation of the hardware shown in Fig. 2.
  • a similar and redundant unit may be located in the studio control room for remote operation of the camera, if desired.
  • the camera control unit provides signals that conform to industry-standard serial bus much as the Inter IC or I 2 C-Bus by Phillips. Data can be transferred at a rate of up to 100 kbits/s in the standard mode, or up to 400 kbits/s in the fast mode.
  • the present invention also includes a novel formatter 302 capable of implementing at least two approaches to the conversion process.
  • one or more field programmable logic devices may be used as logic gates and registers necessary for converting signals from one standard format to another.
  • This programmable logic approach has the advantage of speed (short propagation time between input signal and output signal) and cost effectiveness.
  • the disadvantage of the approach is that it requires specialized design tools to implement the designs.
  • the design tools typically comprise software to configure the devices for particular applications.
  • the design for converting from one standard format to another need only be created once but may be implemented in many signal processors (e.g., HDTV cameras).
  • a second approach, shown in Fig. 5, includes the use of a general-purpose video processor.
  • Video processors are currently available from several manufactures, including Philips. Data may be read into a memory, processed by the general purpose processor, and then read out of memory. If processing speed is not sufficient to accomplish the conversion within one frame time of the picture, then multiple processors may be used to increase the processing bandwidth. This approach includes the use of software code for controlling the television signal conversion from one standard format to another.
  • Fig. 4 shows the Field Programmable Logic Array ("FPLA”)-Based Flexible Formatter 302.
  • FPLA Field Programmable Logic Array
  • the digital video signal input is shown at 301 entering the FPL A 401.
  • the array may consist of a large number of interconnected gates, the interconnection of which can be programmed through data inputs 409 to create a logic network that implements the digital video format conversion. Some conversions, such as from progressive to interlaced signals, require a means to temporarily store the progressive video signal such that the conversion can be accomplished. This means is provided by the video read/write memory 403.
  • the video memory is connected to the FPL A through data, address, and control lines 404.
  • a digital to analog converter 405 may also be connected to the outputs of the FPLA via data and control lines 406.
  • a direct digital connection can be made to the outputs of the FPLA at 408.
  • the FPLA is programmed to convert from one particular format to another by the data provided at the FPLA programming port 409. This input accepts the signals that program the interconnections of the gates.
  • Fig. 5 shows an alternative embodiment of the flexible formatter 302 of the present invention.
  • the formatter disclosed in Fig. 5 is a processor-based flexible formatter capable of accomplishing the same conversion result as the FPLA based formatter. However it uses different components to make the conversion.
  • the digital video input signal 301 is presented to the video processor or processors for storage in a video memory 403, for operation by the software code stored in the program read-only memory 503.
  • the data, address, and control lines for the video memory and the program memory are shown as 404 and 504, respectively. If the conversion is from a digital format to another digital format, the output 408 comes from a data port of the processor directly. If an analog signal 407 is required, the digital representation of the signal is converted to analog by the digital-to-analog converter 405 controlled by its interface 406. The control of the conversion is accomplished by storing the conversion algorithm in the program read-only memory at port 503.
  • the flexible formatter 302 of the present invention may convert the digital video signal 301 to any of a number of different user-specified formats.
  • the digital video signal 301 will be in 1280 x 720 progressive format, but also may be in 720 x 480 progressive.
  • the output signal 408 may be produced in a number of different formats including NTSC, PAL, 720 x 483 progressive, 720 x 480 progressive, 640 x 360 progressive, 360 x 256 progressive, 1920 x 1080 interlaced, 720 x 483 interlaced.
  • the formatter 302 of the present invention may include a plurality of output ports so that multiple signals may be produced simultaneously.
  • the present invention includes a formatter that may produce an NTSC, interlaced and progressive format simultaneously in order to accommodate television broadcast facilities that do not transmit HDTV signals exclusively.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Graphics (AREA)
  • Studio Devices (AREA)
  • Color Television Image Signal Generators (AREA)
  • Television Systems (AREA)

Abstract

L'invention concerne une caméra de télévision dont l'architecture permet d'explorer progressivement la scène filmée, donnant ainsi une représentation complète de chaque image de sortie vidéo. Ladite caméra produit un format numérique à haute définition susceptible d'être converti en l'un quelconque des formats acceptés dans l'industrie. L'invention concerne également un formateur flexible permettant à l'utilisateur de spécifier le format requis.
PCT/US1999/004196 1998-02-27 1999-02-26 Camera de television a haute definition et formateur Ceased WO1999044356A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020007009553A KR20010041419A (ko) 1998-02-27 1999-02-26 고화질 텔레비전 카메라 및 포맷터
JP2000533998A JP2002536851A (ja) 1998-02-27 1999-02-26 高画像品質テレビジョンカメラおよびフォーマッタ
EP99909635A EP1210816A4 (fr) 1998-02-27 1999-02-26 Camera de television a haute definition et formateur

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7628198P 1998-02-27 1998-02-27
US60/076,281 1998-02-27

Publications (2)

Publication Number Publication Date
WO1999044356A2 true WO1999044356A2 (fr) 1999-09-02
WO1999044356A3 WO1999044356A3 (fr) 2002-03-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/004196 Ceased WO1999044356A2 (fr) 1998-02-27 1999-02-26 Camera de television a haute definition et formateur

Country Status (4)

Country Link
EP (1) EP1210816A4 (fr)
JP (1) JP2002536851A (fr)
KR (1) KR20010041419A (fr)
WO (1) WO1999044356A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4661222B2 (ja) * 2005-01-05 2011-03-30 ソニー株式会社 ビデオカメラ
JP2006211633A (ja) * 2005-01-27 2006-08-10 Neucore Technol Inc ビット・スライス出力モードを持つアナログ・フロントエンド・タイミング発生器（ａｆｅ／ｔｇ）

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3382973B2 (ja) * 1992-02-07 2003-03-04 オリンパス光学工業株式会社 電子内視鏡装置
US5521639A (en) * 1992-04-30 1996-05-28 Sony Corporation Solid-state imaging apparatus including a reference pixel in the optically-black region
DE4220236A1 (de) * 1992-06-20 1993-12-23 Bosch Gmbh Robert Videokamera mit einem Halbleiterbildsensor
JPH06276526A (ja) * 1993-03-22 1994-09-30 Hitachi Denshi Ltd カラー着順およびタイム判定装置
EP0690618A1 (fr) * 1994-06-27 1996-01-03 Nikon Corporation Appareil de prise de vues affichant simultanément des images de formats analogiques différents sur un seul moniteur
US5668596A (en) * 1996-02-29 1997-09-16 Eastman Kodak Company Digital imaging device optimized for color performance
US5614948A (en) * 1996-04-26 1997-03-25 Intel Corporation Camera having an adaptive gain control

Also Published As

Publication number Publication date
EP1210816A2 (fr) 2002-06-05
JP2002536851A (ja) 2002-10-29
KR20010041419A (ko) 2001-05-15
EP1210816A4 (fr) 2002-06-05
WO1999044356A3 (fr) 2002-03-28

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