WO2000004585A3 - Chipträgeranordnung sowie verfahren zur herstellung einer chipträgeranordnung mit elektrischem test - Google Patents

Chipträgeranordnung sowie verfahren zur herstellung einer chipträgeranordnung mit elektrischem test Download PDF

Info

Publication number
WO2000004585A3
WO2000004585A3 PCT/DE1999/002110 DE9902110W WO0004585A3 WO 2000004585 A3 WO2000004585 A3 WO 2000004585A3 DE 9902110 W DE9902110 W DE 9902110W WO 0004585 A3 WO0004585 A3 WO 0004585A3
Authority
WO
WIPO (PCT)
Prior art keywords
chip carrier
carrier device
chip
production
electrical test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE1999/002110
Other languages
English (en)
French (fr)
Other versions
WO2000004585A2 (de
Inventor
Hartmut Rohde
Gerhild Wendland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pac Tech Packaging Technologies GmbH
Smart Pac GmbH Technology Services
Original Assignee
Pac Tech Packaging Technologies GmbH
Smart Pac GmbH Technology Services
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pac Tech Packaging Technologies GmbH, Smart Pac GmbH Technology Services filed Critical Pac Tech Packaging Technologies GmbH
Priority to KR1020017000181A priority Critical patent/KR20010074675A/ko
Priority to JP2000560614A priority patent/JP3693287B2/ja
Priority to US09/743,993 priority patent/US6642727B1/en
Publication of WO2000004585A2 publication Critical patent/WO2000004585A2/de
Publication of WO2000004585A3 publication Critical patent/WO2000004585A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Chipträgeranordnung (10) für eine gehäuste Chipanordnung mit einem Chipträger (11), der auf einer Chipkontaktseite (24) eine Leiterbahnstruktur (12) mit zu einer Außenkontaktseite (25) des Chipträgers reichenden und zumindest einem Chip (18) mit jeweils einer Durchkontaktierung (14) zugeordneten Anschlußfläche (17) aufweist, wobei der Chipträger (11) weitere mit der Leiterbahnstruktur (12) verbundene Durchkontaktierungen (14) aufweist, die zur Kontaktierung mit Prüfanschlüssen (32) einer Prüfplatine (29, 30) dienen.
PCT/DE1999/002110 1998-07-15 1999-07-09 Chipträgeranordnung sowie verfahren zur herstellung einer chipträgeranordnung mit elektrischem test Ceased WO2000004585A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020017000181A KR20010074675A (ko) 1998-07-15 1999-07-09 칩 캐리어 장치 및 전기 테스트를 가지는 칩 캐리어장치의 제조방법
JP2000560614A JP3693287B2 (ja) 1998-07-15 1999-07-09 チップキャリア配置体を製造する方法
US09/743,993 US6642727B1 (en) 1998-07-15 1999-07-09 Chip carrier device and method for the production of a chip carrier device with an electrical test

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19831634.8 1998-07-15
DE19831634A DE19831634B4 (de) 1998-07-15 1998-07-15 Chipträgeranordnung sowie Verfahren zur Herstellung einer Chipträgeranordnung mit elektrischem Test

Publications (2)

Publication Number Publication Date
WO2000004585A2 WO2000004585A2 (de) 2000-01-27
WO2000004585A3 true WO2000004585A3 (de) 2000-04-20

Family

ID=7874064

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/002110 Ceased WO2000004585A2 (de) 1998-07-15 1999-07-09 Chipträgeranordnung sowie verfahren zur herstellung einer chipträgeranordnung mit elektrischem test

Country Status (5)

Country Link
US (1) US6642727B1 (de)
JP (1) JP3693287B2 (de)
KR (1) KR20010074675A (de)
DE (1) DE19831634B4 (de)
WO (1) WO2000004585A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10014379A1 (de) 2000-03-23 2001-10-11 Infineon Technologies Ag Verfahren und Vorrichtung zum Verbinden mindestens eines Chips mit einer Umverdrahtungsanordnung
US7214886B2 (en) * 2003-11-25 2007-05-08 International Business Machines Corporation High performance chip carrier substrate
JP6402962B2 (ja) * 2013-07-17 2018-10-10 パナソニックＩｐマネジメント株式会社 高周波モジュール
DE102020215388A1 (de) * 2020-12-04 2022-06-09 First Sensor AG Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren
CN112904180B (zh) * 2021-01-22 2022-04-19 长鑫存储技术有限公司 芯片测试板及芯片测试方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975765A (en) * 1988-07-22 1990-12-04 Contraves Ag Highly integrated circuit and method for the production thereof
EP0564865A1 (de) * 1992-04-06 1993-10-13 Motorola, Inc. Halbleiteranordnung mit Kontakten für Testzwecke und Herstellungsmethode für dieselben
US5378981A (en) * 1993-02-02 1995-01-03 Motorola, Inc. Method for testing a semiconductor device on a universal test circuit substrate
JPH0922929A (ja) * 1995-07-04 1997-01-21 Ricoh Co Ltd Ｂｇａパッケージ半導体素子及びその検査方法
US5731709A (en) * 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US5763947A (en) * 1996-01-31 1998-06-09 International Business Machines Corporation Integrated circuit chip package having configurable contacts and a removable connector
US5767528A (en) * 1996-02-20 1998-06-16 Fujitsu Limited Semiconductor device including pad portion for testing

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4772936A (en) * 1984-09-24 1988-09-20 United Technologies Corporation Pretestable double-sided tab design
US4806409A (en) * 1987-05-20 1989-02-21 Olin Corporation Process for providing an improved electroplated tape automated bonding tape and the product produced thereby
US5036380A (en) * 1988-03-28 1991-07-30 Digital Equipment Corp. Burn-in pads for tab interconnects
JP2812627B2 (ja) * 1992-10-30 1998-10-22 三菱電機株式会社 テープキャリア、半導体装置試験方法及び装置
US5598036A (en) * 1995-06-15 1997-01-28 Industrial Technology Research Institute Ball grid array having reduced mechanical stress

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975765A (en) * 1988-07-22 1990-12-04 Contraves Ag Highly integrated circuit and method for the production thereof
EP0564865A1 (de) * 1992-04-06 1993-10-13 Motorola, Inc. Halbleiteranordnung mit Kontakten für Testzwecke und Herstellungsmethode für dieselben
US5378981A (en) * 1993-02-02 1995-01-03 Motorola, Inc. Method for testing a semiconductor device on a universal test circuit substrate
JPH0922929A (ja) * 1995-07-04 1997-01-21 Ricoh Co Ltd Ｂｇａパッケージ半導体素子及びその検査方法
US5986460A (en) * 1995-07-04 1999-11-16 Ricoh Company, Ltd. BGA package semiconductor device and inspection method therefor
US5731709A (en) * 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US5763947A (en) * 1996-01-31 1998-06-09 International Business Machines Corporation Integrated circuit chip package having configurable contacts and a removable connector
US5767528A (en) * 1996-02-20 1998-06-16 Fujitsu Limited Semiconductor device including pad portion for testing

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
DATABASE WPI Section Ch Week 199713, Derwent World Patents Index; Class L03, AN 1997-142794, XP002130044 *

Also Published As

Publication number Publication date
JP3693287B2 (ja) 2005-09-07
JP2002520879A (ja) 2002-07-09
KR20010074675A (ko) 2001-08-08
DE19831634B4 (de) 2005-02-03
WO2000004585A2 (de) 2000-01-27
DE19831634A1 (de) 2000-01-27
US6642727B1 (en) 2003-11-04

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